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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <displayport.h>
Data Fields | |
struct tegra_dc * | dc |
struct tegra_dc_sor_data | sor |
void * | aux_base |
struct tegra_dc_dp_link_config | link_cfg |
u8 | revision |
int | enabled |
Definition at line 320 of file displayport.h.
void* tegra_dc_dp_data::aux_base |
Definition at line 323 of file displayport.h.
Referenced by dp_init(), tegra_dpaux_readl(), and tegra_dpaux_writel().
struct tegra_dc* tegra_dc_dp_data::dc |
Definition at line 321 of file displayport.h.
Referenced by dp_enable(), dp_init(), tegra_dc_sor_config_panel(), and tegra_dp_lower_link_config().
int tegra_dc_dp_data::enabled |
Definition at line 326 of file displayport.h.
Referenced by dp_enable(), and dp_init().
struct tegra_dc_dp_link_config tegra_dc_dp_data::link_cfg |
Definition at line 323 of file displayport.h.
Referenced by _tegra_dp_lower_link_config(), dp_enable(), dp_init(), tegra_dc_dp_calc_config(), tegra_dc_dp_check_sink(), tegra_dc_dp_dump_link_cfg(), tegra_dc_dp_full_link_training(), tegra_dc_dp_init_max_link_cfg(), tegra_dc_sor_config_panel(), tegra_dp_channel_eq(), tegra_dp_channel_eq_status(), tegra_dp_clk_recovery(), tegra_dp_clock_recovery_status(), tegra_dp_link_config(), tegra_dp_lower_link_config(), tegra_dp_lt_adjust(), tegra_dp_lt_config(), tegra_dp_set_lane_count(), tegra_dp_tpg(), and tegra_dp_wait_aux_training().
u8 tegra_dc_dp_data::revision |
Definition at line 325 of file displayport.h.
Referenced by dp_enable().
struct tegra_dc_sor_data tegra_dc_dp_data::sor |
Definition at line 321 of file displayport.h.
Referenced by dp_enable(), dp_init(), tegra_dc_dp_check_sink(), tegra_dc_dp_fast_link_training(), tegra_dc_dp_full_link_training(), tegra_dc_dp_set_assr(), tegra_dp_do_link_training(), tegra_dp_link_config(), tegra_dp_lt_config(), tegra_dp_set_lane_count(), tegra_dp_set_link_bandwidth(), and tegra_dp_tpg().