coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smihandler.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <
cpu/x86/smm.h
>
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#include <
ec/google/chromeec/smm.h
>
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#include <
intelblocks/smihandler.h
>
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#include <baseboard/ec.h>
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void
mainboard_smi_espi_handler
(
void
)
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{
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chromeec_smi_process_events
();
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}
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void
mainboard_smi_sleep
(
u8
slp_typ)
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{
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if
(!
CONFIG
(EC_GOOGLE_CHROMEEC))
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return
;
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chromeec_smi_sleep
(slp_typ,
MAINBOARD_EC_S3_WAKE_EVENTS
,
MAINBOARD_EC_S5_WAKE_EVENTS
);
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}
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int
mainboard_smi_apmc
(
u8
apmc)
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{
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if
(
CONFIG
(EC_GOOGLE_CHROMEEC))
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chromeec_smi_apmc
(apmc,
MAINBOARD_EC_SCI_EVENTS
,
MAINBOARD_EC_SMI_EVENTS
);
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return
0;
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}
mainboard_smi_sleep
void __weak mainboard_smi_sleep(u8 slp_typ)
Definition:
smihandler.c:210
mainboard_smi_apmc
int __weak mainboard_smi_apmc(u8 data)
Definition:
smihandler.c:209
CONFIG
@ CONFIG
Definition:
dsi_common.h:201
chromeec_smi_sleep
void chromeec_smi_sleep(int slp_type, uint64_t s3_mask, uint64_t s5_mask)
Definition:
smihandler.c:48
chromeec_smi_process_events
void chromeec_smi_process_events(void)
Definition:
smihandler.c:29
chromeec_smi_apmc
void chromeec_smi_apmc(int apmc, uint64_t sci_mask, uint64_t smi_mask)
Definition:
smihandler.c:89
smm.h
smm.h
MAINBOARD_EC_S5_WAKE_EVENTS
#define MAINBOARD_EC_S5_WAKE_EVENTS
Definition:
ec.h:32
MAINBOARD_EC_SCI_EVENTS
#define MAINBOARD_EC_SCI_EVENTS
Definition:
ec.h:12
MAINBOARD_EC_SMI_EVENTS
#define MAINBOARD_EC_SMI_EVENTS
Definition:
ec.h:28
MAINBOARD_EC_S3_WAKE_EVENTS
#define MAINBOARD_EC_S3_WAKE_EVENTS
Definition:
ec.h:37
mainboard_smi_espi_handler
void mainboard_smi_espi_handler(void)
Definition:
smihandler.c:26
smihandler.h
u8
uint8_t u8
Definition:
stdint.h:45
src
mainboard
intel
shadowmountain
smihandler.c
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