|
| enum | mipi_dsi_pixel_format {
MIPI_DSI_FMT_RGB888
, MIPI_DSI_FMT_RGB666
, MIPI_DSI_FMT_RGB666_PACKED
, MIPI_DSI_FMT_RGB565
,
MIPI_DSI_FMT_RGB888
, MIPI_DSI_FMT_RGB666
, MIPI_DSI_FMT_RGB666_PACKED
, MIPI_DSI_FMT_RGB565
,
MIPI_DSI_FMT_RGB888
, MIPI_DSI_FMT_RGB666
, MIPI_DSI_FMT_RGB666_PACKED
, MIPI_DSI_FMT_RGB565
} |
| |
| enum | {
MIPI_DSI_MODE_VIDEO = BIT(0)
, MIPI_DSI_MODE_VIDEO_BURST = BIT(1)
, MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2)
, MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3)
,
MIPI_DSI_MODE_VIDEO_HSE = BIT(4)
, MIPI_DSI_MODE_VIDEO_HFP = BIT(5)
, MIPI_DSI_MODE_VIDEO_HBP = BIT(6)
, MIPI_DSI_MODE_VIDEO_HSA = BIT(7)
,
MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8)
, MIPI_DSI_MODE_EOT_PACKET = BIT(9)
, MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10)
, MIPI_DSI_MODE_LPM = BIT(11)
,
MIPI_DSI_MODE_LINE_END = BIT(12)
} |
| |
| enum | {
LPRX_RD_RDY_INT_FLAG = BIT(0)
, CMD_DONE_INT_FLAG = BIT(1)
, TE_RDY_INT_FLAG = BIT(2)
, VM_DONE_INT_FLAG = BIT(3)
,
EXT_TE_RDY_INT_FLAG = BIT(4)
, DSI_BUSY = BIT(31)
} |
| |
| enum | { DSI_RESET = BIT(0)
, DSI_EN = BIT(1)
, DPHY_RESET = BIT(2)
, DSI_DUAL = BIT(4)
} |
| |
| enum | {
MODE = 3
, CMD_MODE = 0
, SYNC_PULSE_MODE = 1
, SYNC_EVENT_MODE = 2
,
BURST_MODE = 3
, FRM_MODE = BIT(16)
, MIX_MODE = BIT(17)
} |
| |
| enum | { EOTP_DISABLE = BIT(6)
, NON_CONTINUOUS_CLK = BIT(16)
} |
| |
| enum | {
DSI_PS_WC = 0x3fff
, DSI_PS_SEL = (3 << 16)
, PACKED_PS_16BIT_RGB565 = (0 << 16)
, LOOSELY_PS_18BIT_RGB666 = (1 << 16)
,
PACKED_PS_18BIT_RGB666 = (2 << 16)
, PACKED_PS_24BIT_RGB888 = (3 << 16)
, DSI_PSCON_CUSTOM_HEADER_SHIFT = 26
} |
| |
| enum | { DSI_SIZE_CON_HEIGHT_SHIFT = 16
, DSI_SIZE_CON_WIDTH_SHIFT = 0
} |
| |
| enum | { CMDQ_SIZE = 0x3f
} |
| |
| enum | { LC_HS_TX_EN = BIT(0)
, LC_ULPM_EN = BIT(1)
, LC_WAKEUP_EN = BIT(2)
} |
| |
| enum | { LD0_RM_TRIG_EN = BIT(0)
, LD0_ULPM_EN = BIT(1)
, LD0_WAKEUP_EN = BIT(2)
} |
| |
| enum | { LPX = (0xff << 0)
, HS_PRPR = (0xff << 8)
, HS_ZERO = (0xff << 16)
, HS_TRAIL = (0xff << 24)
} |
| |
| enum | { TA_GO = (0xff << 0)
, TA_SURE = (0xff << 8)
, TA_GET = (0xff << 16)
, DA_HS_EXIT = (0xff << 24)
} |
| |
| enum | { CONT_DET = (0xff << 0)
, CLK_ZERO = (0xf << 16)
, CLK_TRAIL = (0xff << 24)
} |
| |
| enum | { CLK_HS_PRPR = (0xff << 0)
, CLK_HS_POST = (0xff << 8)
, CLK_HS_EXIT = (0xf << 16)
} |
| |
| enum | { VM_CMD_EN = BIT(0)
, TS_VFP_EN = BIT(5)
} |
| |
| enum | {
CONFIG = (0xff << 0)
, SHORT_PACKET = 0
, LONG_PACKET = 2
, BTA = BIT(2)
,
DATA_ID = (0xff << 8)
, DATA_0 = (0xff << 16)
, DATA_1 = (0xff << 24)
} |
| |
| enum | { DSI_FORCE_COMMIT_USE_MMSYS = BIT(0)
, DSI_FORCE_COMMIT_ALWAYS = BIT(1)
} |
| |
| void mtk_dsi_configure_mipi_tx |
( |
u32 |
data_rate, |
|
|
u32 |
lanes |
|
) |
| |
PLL PCW config PCW bit 24~30 = integer part of pcw PCW bit 0~23 = fractional part of pcw pcw = data_Rate*4*txdiv/(Ref_clk*2); Post DIV =4, so need data_Rate*4 Ref_clk is 26MHz
Definition at line 10 of file mtk_mipi_dphy.c.
References AD_DSI_PLL_SDM_ISO_EN, AD_DSI_PLL_SDM_PWR_ON, assert, BIT, mipi_tx_regs::ck_ckmode_en, mipi_tx_regs::ck_sw_ctl_en, CLK26M_HZ, clrbits32, clrsetbits32, mipi_tx_regs::d0_sw_ctl_en, mipi_tx_regs::d1_sw_ctl_en, mipi_tx_regs::d2_sw_ctl_en, mipi_tx_regs::d3_sw_ctl_en, mipi_tx_regs::dsi_bg_con, DSI_CK_CKMODE_EN, mipi_tx_regs::dsi_clock_lane, mipi_tx_regs::dsi_con, mipi_tx_regs::dsi_data_lane, mipi_tx_regs::dsi_pll_con0, mipi_tx_regs::dsi_pll_con1, mipi_tx_regs::dsi_pll_con2, mipi_tx_regs::dsi_pll_pwr, DSI_SW_CTL_EN, mipi_tx_regs::dsi_top_con, mipi_tx_regs::lane_con, LDOOUT_EN, MHz, mipi_tx, mipi_tx0, MTK_DSI_DATA_RATE_MIN_MHZ, mipi_tx_regs::pll_con0, mipi_tx_regs::pll_con1, mipi_tx_regs::pll_con4, mipi_tx_regs::pll_pwr, read32(), RG_DSI0_CKG_LDOOUT_EN, RG_DSI0_LDOCORE_EN, RG_DSI0_MPPLL_PLL_EN, RG_DSI0_MPPLL_PREDIV, RG_DSI0_MPPLL_SDM_FRA_EN, RG_DSI0_MPPLL_SDM_SSC_EN, RG_DSI0_MPPLL_TXDIV0, RG_DSI0_MPPLL_TXDIV1, RG_DSI_BG_CKEN, RG_DSI_BG_CORE_EN, RG_DSI_LNT_HS_BIAS_EN, RG_DSI_LNT_IMP_CAL_CODE, RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON, RG_DSI_PAD_TIE_LOW_EN, RG_DSI_PLL_EN, RG_DSI_PLL_POSDIV, RG_DSI_V02_SEL, RG_DSI_V032_SEL, RG_DSI_V04_SEL, RG_DSI_V072_SEL, RG_DSI_V10_SEL, RG_DSI_V12_SEL, setbits32, udelay(), and write32().
Referenced by mtk_dsi_init().
1.9.1