6 #include <bdk-devicetree.h>
8 const struct bdk_devicetree_key_value
devtree[] = {
9 {
"DDR-CONFIG-DQX-CTL",
"0x4"},
10 {
"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2",
"0xc0c0303"},
11 {
"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1",
"0x1030203"},
12 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0",
"0x4"},
13 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0",
"0x4"},
14 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2",
"0x4"},
15 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0",
"0x2"},
16 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1",
"0x2"},
17 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2",
"0x2"},
18 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS4",
"0x1"},
19 {
"DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1",
"0x1"},
20 {
"DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2",
"0x2"},
21 {
"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0",
"0x4"},
22 {
"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2",
"0x4"},
23 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0",
"0x1"},
24 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0",
"0x5"},
25 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2",
"0x5"},
26 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0",
"0x2"},
27 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1",
"0x2"},
28 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2",
"0x1"},
29 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0",
"0x6"},
30 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1",
"0x6"},
31 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0",
"0x22"},
32 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0",
"0x1f"},
33 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2",
"0x1f"},
34 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0",
"0x19"},
35 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1",
"0x19"},
36 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2",
"0x19"},
37 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0",
"0x1f"},
38 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1",
"0x1f"},
39 {
"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1",
"0x7"},
40 {
"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2",
"0x3"},
41 {
"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1",
"0x3"},
42 {
"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2",
"0x7"},
43 {
"DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1",
"0x7"},
44 {
"DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2",
"0x4080102"},
45 {
"DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1",
"0x1010202"},
46 {
"DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX",
"0x1"},
47 {
"DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX",
"0x7"},
48 {
"DDR-CONFIG-CUSTOM-MIN-RODT-CTL",
"0x1"},
49 {
"DDR-CONFIG-CUSTOM-MAX-RODT-CTL",
"0x7"},
50 {
"DDR-CONFIG-CUSTOM-OFFSET-EN",
"0x1"},
51 {
"DDR-CONFIG-CUSTOM-OFFSET",
"0x2"},
52 {
"DDR-CONFIG-CUSTOM-DDR2T",
"0x1"},
53 {
"DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT",
"0x2"},
54 {
"DDR-CONFIG-CUSTOM-FPRCH2",
"0x2"},
55 {
"PHY-ADDRESS.N0.BGX0.P0",
"0x00001000"},
56 {
"PHY-ADDRESS.N0.BGX2.P0",
"0x00001000"},
57 {
"BGX-ENABLE.N0.BGX0.P0",
"1"},
58 {
"BGX-ENABLE.N0.BGX0.P1",
"0"},
59 {
"BGX-ENABLE.N0.BGX0.P2",
"0"},
60 {
"BGX-ENABLE.N0.BGX0.P3",
"0"},
61 {
"BGX-ENABLE.N0.BGX1.P0",
"0"},
62 {
"BGX-ENABLE.N0.BGX1.P1",
"0"},
63 {
"BGX-ENABLE.N0.BGX2.P0",
"1"},
64 {
"BDK-NUM-PACKET-BUFFERS",
"0x1000"},
65 {
"BDK-PACKET-BUFFER-SIZE",
"0x400"},
66 {
"BDK-SHOW-LINK-STATUS",
"1"},
67 {
"BDK-COREMASK",
"0"},
68 {
"BDK-BOOT-MENU-TIMEOUT",
"0x05"},
69 {
"BDK-BOOT-PATH-OPTION",
"0"},
70 {
"BDK-CONFIG-TRACE",
"1"},
72 {
"QLM-AUTO-CONFIG",
"0"},
73 {
"QLM-DIP-AUTO-CONFIG",
"0"},
74 {
"QLM-MODE.N0.QLM0",
"PCIE_1X1"},
75 {
"QLM-MODE.N0.QLM1",
"SGMII_2X1"},
76 {
"QLM-MODE.N0.QLM2",
"PCIE_1X2"},
77 {
"QLM-MODE.N0.QLM3",
"SATA_2X1"},
78 {
"QLM-FREQ.N0.QLM0",
"6000"},
79 {
"QLM-FREQ.N0.QLM1",
"1250"},
80 {
"QLM-FREQ.N0.QLM2",
"6000"},
81 {
"QLM-FREQ.N0.QLM3",
"6000"},
82 {
"QLM-CLK.N0.QLM0",
"2"},
83 {
"QLM-CLK.N0.QLM1",
"2"},
84 {
"QLM-CLK.N0.QLM2",
"2"},
85 {
"QLM-CLK.N0.QLM3",
"2"},
86 {
"DDR-SPEED.N0",
"1600"},
87 {
"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0",
"0x1050"},
88 {
"USB-REFCLK-SRC.N0.PORT0",
"0"},
89 {
"GPIO-PIN-SELECT-GPIO45",
"0x2"},
90 {
"GPIO-PIN-SELECT-GPIO46",
"0x250"},
const struct bdk_devicetree_key_value devtree[]