6 #include <bdk-devicetree.h>
8 const struct bdk_devicetree_key_value
devtree[] = {
9 {
"DDR-TEST-BOOT",
"1"},
10 {
"DDR-CONFIG-DQX-CTL",
"0x4"},
11 {
"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2",
"0xc0c0303"},
12 {
"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1",
"0x1030203"},
13 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0",
"0x4"},
14 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0",
"0x4"},
15 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2",
"0x4"},
16 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0",
"0x2"},
17 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1",
"0x2"},
18 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2",
"0x2"},
19 {
"DDR-CONFIG-MODE1-RTT-WR.RANKS4",
"0x1"},
20 {
"DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1",
"0x1"},
21 {
"DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2",
"0x2"},
22 {
"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0",
"0x4"},
23 {
"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2",
"0x4"},
24 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0",
"0x1"},
25 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0",
"0x5"},
26 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2",
"0x5"},
27 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0",
"0x2"},
28 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1",
"0x2"},
29 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2",
"0x1"},
30 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0",
"0x6"},
31 {
"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1",
"0x6"},
32 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0",
"0x22"},
33 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0",
"0x1f"},
34 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2",
"0x1f"},
35 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0",
"0x19"},
36 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1",
"0x19"},
37 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2",
"0x19"},
38 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0",
"0x1f"},
39 {
"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1",
"0x1f"},
40 {
"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1",
"0x7"},
41 {
"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2",
"0x3"},
42 {
"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1",
"0x3"},
43 {
"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2",
"0x7"},
44 {
"DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1",
"0x7"},
45 {
"DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2",
"0x4080102"},
46 {
"DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1",
"0x1010202"},
47 {
"DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX",
"0x1"},
48 {
"DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX",
"0x7"},
49 {
"DDR-CONFIG-CUSTOM-MIN-RODT-CTL",
"0x1"},
50 {
"DDR-CONFIG-CUSTOM-MAX-RODT-CTL",
"0x7"},
51 {
"DDR-CONFIG-CUSTOM-CK-CTL",
"0x4"},
52 {
"DDR-CONFIG-CUSTOM-CMD-CTL",
"0x4"},
53 {
"DDR-CONFIG-CUSTOM-CTL-CTL",
"0x4"},
54 {
"DDR-CONFIG-CUSTOM-OFFSET-EN",
"0x1"},
55 {
"DDR-CONFIG-CUSTOM-OFFSET",
"0x2"},
56 {
"DDR-CONFIG-CUSTOM-DDR2T",
"0x1"},
57 {
"DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT",
"0x2"},
58 {
"DDR-CONFIG-CUSTOM-FPRCH2",
"0x2"},
59 {
"PHY-ADDRESS.N0.BGX0.P0",
"0xff000010"},
60 {
"PHY-ADDRESS.N0.BGX0.P1",
"0xff000011"},
61 {
"PHY-ADDRESS.N0.BGX0.P2",
"0xff000012"},
62 {
"PHY-ADDRESS.N0.BGX0.P3",
"0xff000013"},
63 {
"PHY-ADDRESS.N0.BGX1.P0",
"0xff002014"},
64 {
"PHY-ADDRESS.N0.BGX1.P1",
"0xff002014"},
65 {
"PHY-ADDRESS.N0.BGX2.P0",
"0xff000000"},
66 {
"BGX-ENABLE.N0.BGX0.P0",
"1"},
67 {
"BGX-ENABLE.N0.BGX0.P1",
"1"},
68 {
"BGX-ENABLE.N0.BGX0.P2",
"1"},
69 {
"BGX-ENABLE.N0.BGX0.P3",
"1"},
70 {
"BGX-ENABLE.N0.BGX1.P0",
"1"},
71 {
"BGX-ENABLE.N0.BGX1.P1",
"1"},
72 {
"BGX-ENABLE.N0.BGX2.P0",
"1"},
73 {
"BDK-NUM-PACKET-BUFFERS",
"0x1000"},
74 {
"BDK-PACKET-BUFFER-SIZE",
"0x400"},
75 {
"BDK-SHOW-LINK-STATUS",
"1"},
76 {
"BDK-COREMASK",
"0"},
78 {
"QLM-AUTO-CONFIG",
"0"},
79 {
"QLM-DIP-AUTO-CONFIG",
"1"},
80 {
"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0",
"0x1050"},
81 {
"USB-PWR-GPIO.N0.PORT0",
"12"},
82 {
"USB-PWR-GPIO-POLARITY.N0.PORT0",
"0"},
83 {
"USB-REFCLK-SRC.N0.PORT0",
"0"},
84 {
"GPIO-PIN-SELECT-GPIO15",
"0x24f"},
85 {
"GPIO-PIN-SELECT-GPIO16",
"0x24e"},
86 {
"GPIO-PIN-SELECT-GPIO17",
"0x24b"},
87 {
"GPIO-PIN-SELECT-GPIO18",
"0x247"},
88 {
"GPIO-PIN-SELECT-GPIO19",
"0x24d"},
89 {
"GPIO-PIN-SELECT-GPIO20",
"0x24c"},
90 {
"GPIO-PIN-SELECT-GPIO37",
"0x24a"},
91 {
"GPIO-PIN-SELECT-GPIO38",
"0x246"},
92 {
"GPIO-PIN-SELECT-GPIO7",
"0xe1"},
93 {
"GPIO-PIN-SELECT-GPIO24",
"0xeb"},
94 {
"GPIO-PIN-SELECT-GPIO27",
"0xed"},
95 {
"GPIO-PIN-SELECT-GPIO28",
"0xe3"},
96 {
"GPIO-PIN-SELECT-GPIO29",
"0xe0"},
97 {
"GPIO-PIN-SELECT-GPIO30",
"0xe2"},
98 {
"GPIO-PIN-SELECT-GPIO40",
"0x112"},
99 {
"GPIO-PIN-SELECT-GPIO41",
"0x113"},
100 {
"GPIO-PIN-SELECT-GPIO42",
"0x114"},
101 {
"GPIO-PIN-SELECT-GPIO43",
"0x115"},
102 {
"GPIO-PIN-SELECT-GPIO44",
"0x116"},
103 {
"GPIO-PIN-SELECT-GPIO45",
"0x117"},
104 {
"GPIO-PIN-SELECT-GPIO46",
"0x118"},
105 {
"GPIO-PIN-SELECT-GPIO47",
"0x119"},
106 {
"GPIO-POLARITY-GPIO7",
"1"},
107 {
"GPIO-POLARITY-GPIO27",
"1"},
108 {
"GPIO-POLARITY-GPIO28",
"1"},
109 {
"GPIO-POLARITY-GPIO30",
"1"},
const struct bdk_devicetree_key_value devtree[]