coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
psp_smm_gen2.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/smi.h>
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#include <
amdblocks/acpimmio.h
>
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#include <
amdblocks/psp.h
>
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#include <
amdblocks/smi.h
>
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void
soc_fill_smm_trig_info
(
struct
smm_trigger_info
*trig)
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{
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if
(!trig)
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return
;
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trig->
address
= (
uintptr_t
)
acpimmio_smi
+
SMI_REG_SMITRIG0
;
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trig->
address_type
=
SMM_TRIGGER_MEM
;
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trig->
value_width
=
SMM_TRIGGER_DWORD
;
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trig->
value_and_mask
= ~
SMITRIG0_PSP
;
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trig->
value_or_mask
=
SMITRIG0_PSP
;
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}
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void
soc_fill_smm_reg_info
(
struct
smm_register_info
*reg)
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{
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if
(!reg)
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return
;
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reg->
smi_enb
.
address
= (
uintptr_t
)
acpimmio_smi
+
SMI_REG_SMITRIG0
;
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reg->
smi_enb
.
address_type
=
SMM_TRIGGER_MEM
;
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reg->
smi_enb
.
value_width
=
SMM_TRIGGER_DWORD
;
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reg->
smi_enb
.
reg_bit_mask
=
SMITRG0_SMIENB
;
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reg->
smi_enb
.
expect_value
= 0;
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reg->
eos
.
address
= (
uintptr_t
)
acpimmio_smi
+
SMI_REG_SMITRIG0
;
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reg->
eos
.
address_type
=
SMM_TRIGGER_MEM
;
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reg->
eos
.
value_width
=
SMM_TRIGGER_DWORD
;
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reg->
eos
.
reg_bit_mask
=
SMITRG0_EOS
;
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reg->
eos
.
expect_value
=
SMITRG0_EOS
;
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reg->
psp_smi_en
.
address
= (
uintptr_t
)
acpimmio_smi
+
SMI_REG_CONTROL0
;
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reg->
psp_smi_en
.
address
+=
sizeof
(
uint32_t
) *
SMITYPE_PSP
/ 16;
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reg->
psp_smi_en
.
address_type
=
SMM_TRIGGER_MEM
;
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reg->
psp_smi_en
.
value_width
=
SMM_TRIGGER_DWORD
;
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reg->
psp_smi_en
.
reg_bit_mask
=
SMI_MODE_MASK
<< (2 *
SMITYPE_PSP
% 16);
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reg->
psp_smi_en
.
expect_value
=
SMI_MODE_SMI
<< (2 *
SMITYPE_PSP
% 16);
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}
acpimmio.h
acpimmio_smi
uint8_t *MAYBE_CONST acpimmio_smi
psp.h
SMM_TRIGGER_DWORD
#define SMM_TRIGGER_DWORD
Definition:
psp.h:13
SMM_TRIGGER_MEM
#define SMM_TRIGGER_MEM
Definition:
psp.h:9
soc_fill_smm_trig_info
void soc_fill_smm_trig_info(struct smm_trigger_info *trig)
Definition:
psp_smm_gen2.c:8
soc_fill_smm_reg_info
void soc_fill_smm_reg_info(struct smm_register_info *reg)
Definition:
psp_smm_gen2.c:20
SMITRG0_EOS
#define SMITRG0_EOS
Definition:
smi.h:165
SMI_MODE_MASK
#define SMI_MODE_MASK
Definition:
smi.h:180
SMITYPE_PSP
#define SMITYPE_PSP
Definition:
smi.h:80
SMI_REG_CONTROL0
#define SMI_REG_CONTROL0
Definition:
smi.h:169
SMITRG0_SMIENB
#define SMITRG0_SMIENB
Definition:
smi.h:167
SMI_REG_SMITRIG0
#define SMI_REG_SMITRIG0
Definition:
smi.h:163
SMITRIG0_PSP
#define SMITRIG0_PSP
Definition:
smi.h:164
smi.h
SMI_MODE_SMI
@ SMI_MODE_SMI
Definition:
smi.h:10
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
uintptr_t
unsigned long uintptr_t
Definition:
stdint.h:21
smm_register_info
Definition:
psp.h:31
smm_register_info::eos
struct smm_register eos
Definition:
psp.h:33
smm_register_info::psp_smi_en
struct smm_register psp_smi_en
Definition:
psp.h:34
smm_register_info::smi_enb
struct smm_register smi_enb
Definition:
psp.h:32
smm_register::address
uint64_t address
Definition:
psp.h:24
smm_register::address_type
uint32_t address_type
Definition:
psp.h:25
smm_register::value_width
uint32_t value_width
Definition:
psp.h:26
smm_register::expect_value
uint32_t expect_value
Definition:
psp.h:28
smm_register::reg_bit_mask
uint32_t reg_bit_mask
Definition:
psp.h:27
smm_trigger_info
Definition:
psp.h:15
smm_trigger_info::value_and_mask
uint32_t value_and_mask
Definition:
psp.h:19
smm_trigger_info::address_type
uint32_t address_type
Definition:
psp.h:17
smm_trigger_info::value_width
uint32_t value_width
Definition:
psp.h:18
smm_trigger_info::value_or_mask
uint32_t value_or_mask
Definition:
psp.h:20
smm_trigger_info::address
uint64_t address
Definition:
psp.h:16
src
soc
amd
common
block
psp
psp_smm_gen2.c
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