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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
#include <ec/lenovo/h8/h8.h>
#include <southbridge/intel/lynxpoint/pch.h>
Go to the source code of this file.
Macros | |
#define | GPE_EC_SCI 1 |
#define | GPE_EC_WAKE 13 |
#define | GPI_DISABLE 0x00 |
#define | GPI_IS_SMI 0x01 |
#define | GPI_IS_SCI 0x02 |
#define | GPI_IS_NMI 0x03 |
Functions | |
static void | mainboard_smi_handle_ec_sci (void) |
void | mainboard_smi_gpi (u32 gpi_sts) |
static void | gpi_route_interrupt (u8 gpi, u8 mode) |
int | mainboard_smi_apmc (u8 data) |
void | mainboard_smi_sleep (u8 slp_typ) |
#define GPE_EC_SCI 1 |
Definition at line 11 of file smihandler.c.
#define GPE_EC_WAKE 13 |
Definition at line 12 of file smihandler.c.
#define GPI_DISABLE 0x00 |
Definition at line 33 of file smihandler.c.
#define GPI_IS_NMI 0x03 |
Definition at line 36 of file smihandler.c.
#define GPI_IS_SCI 0x02 |
Definition at line 35 of file smihandler.c.
#define GPI_IS_SMI 0x01 |
Definition at line 34 of file smihandler.c.
Definition at line 38 of file smihandler.c.
References GPIO_ROUT, PCI_DEV, pci_read_config32(), and pci_write_config32().
Referenced by mainboard_smi_apmc(), and mainboard_smi_sleep().
int mainboard_smi_apmc | ( | u8 | data | ) |
Definition at line 48 of file smihandler.c.
References APM_CNT_ACPI_DISABLE, APM_CNT_ACPI_ENABLE, ec_set_ports(), ec_write(), GPE_EC_SCI, GPI_IS_SCI, GPI_IS_SMI, and gpi_route_interrupt().
Definition at line 26 of file smihandler.c.
References GPE_EC_SCI, and mainboard_smi_handle_ec_sci().
Definition at line 14 of file smihandler.c.
References BIOS_DEBUG, ec_query(), EC_SC, EC_SCI_EVT, inb(), and printk.
Referenced by mainboard_smi_gpi().
Definition at line 74 of file smihandler.c.
References ec_read(), GPE_EC_WAKE, GPI_IS_SCI, and gpi_route_interrupt().