![]() |
coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
|
Go to the source code of this file.
Enumerations | |
enum | { L2CTLR_ECC_PARITY = 0x1 << 21 , L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6 , L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6 , L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0 , L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 } |
enum | { L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27 , L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7 , L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 } |
Functions | |
static void | configure_l2ctlr (void) |
static void | configure_l2actlr (void) |
void | configure_l2_cache (void) |
anonymous enum |
anonymous enum |
Definition at line 45 of file cache.c.
References configure_l2actlr(), and configure_l2ctlr().
Referenced by romstage(), and verstage_mainboard_init().
Definition at line 34 of file cache.c.
References L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL, L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT, L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE, read_l2actlr(), val, and write_l2actlr().
Referenced by configure_l2_cache().
Definition at line 22 of file cache.c.
References L2CTLR_DATA_RAM_LATENCY_CYCLES_3, L2CTLR_DATA_RAM_LATENCY_MASK, L2CTLR_ECC_PARITY, L2CTLR_TAG_RAM_LATENCY_CYCLES_3, L2CTLR_TAG_RAM_LATENCY_MASK, read_l2ctlr(), val, and write_l2ctlr().
Referenced by configure_l2_cache().