coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
sdram-ddr3-nanya-2GB.inc
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1 {
2  /* 4 Nanya NT5CC256M16DP chips */
3  {
4  {
5  .rank = 0x1,
6  .col = 0xA,
7  .bk = 0x3,
8  .bw = 0x2,
9  .dbw = 0x1,
10  .row_3_4 = 0x0,
11  .cs0_row = 0xF,
12  .cs1_row = 0xF
13  },
14  {
15  .rank = 0x1,
16  .col = 0xA,
17  .bk = 0x3,
18  .bw = 0x2,
19  .dbw = 0x1,
20  .row_3_4 = 0x0,
21  .cs0_row = 0xF,
22  .cs1_row = 0xF
23  }
24  },
25  {
26  .togcnt1u = 0x29A,
27  .tinit = 0xC8,
28  .trsth = 0x1F4,
29  .togcnt100n = 0x42,
30  .trefi = 0x4E,
31  .tmrd = 0x4,
32  .trfc = 0xEA,
33  .trp = 0xA,
34  .trtw = 0x5,
35  .tal = 0x0,
36  .tcl = 0xA,
37  .tcwl = 0x7,
38  .tras = 0x19,
39  .trc = 0x24,
40  .trcd = 0xA,
41  .trrd = 0x7,
42  .trtp = 0x5,
43  .twr = 0xA,
44  .twtr = 0x5,
45  .texsr = 0x200,
46  .txp = 0x5,
47  .txpdll = 0x10,
48  .tzqcs = 0x40,
49  .tzqcsi = 0x0,
50  .tdqs = 0x1,
51  .tcksre = 0x7,
52  .tcksrx = 0x7,
53  .tcke = 0x4,
54  .tmod = 0xC,
55  .trstl = 0x43,
56  .tzqcl = 0x100,
57  .tmrr = 0x0,
58  .tckesr = 0x5,
59  .tdpd = 0x0
60  },
61  {
62  .dtpr0 = 0x48F9AAB4,
63  .dtpr1 = 0xEA0910,
64  .dtpr2 = 0x1002C200,
65  .mr[0] = 0xA60,
66  .mr[1] = 0x40,
67  .mr[2] = 0x10,
68  .mr[3] = 0x0
69  },
70  .noc_timing = 0x30B25564,
71  .noc_activate = 0x627,
72  .ddrconfig = 3,
73  .ddr_freq = 666*MHz,
74  .dramtype = DDR3,
75  .num_channels = 2,
76  .stride = 9,
77  .odt = 1
78 },
MHz
#define MHz
Definition: helpers.h:80
DDR3
@ DDR3
Definition: gm45.h:53