coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
amdblocks/acpimmio.h
>
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#include <arch/io.h>
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#include <
bootblock_common.h
>
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#include <
device/pnp_ops.h
>
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#include <
superio/ite/common/ite.h
>
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#include <
superio/ite/it8623e/it8623e.h
>
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#if CONFIG_UART_FOR_CONSOLE == 0
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#define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP1)
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#elif CONFIG_UART_FOR_CONSOLE == 1
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#define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP2)
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#else
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#error "Invalid value for CONFIG_UART_FOR_CONSOLE"
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#endif
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#define GPIO_DEV PNP_DEV(0x2e, IT8623E_GPIO)
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#define CLKIN_DEV PNP_DEV(0x2e, IT8623E_GPIO)
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#define ENVC_DEV PNP_DEV(0x2e, IT8623E_EC)
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/* Sets up EC configuration as per vendor defaults */
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static
void
ite_evc_conf
(
pnp_devfn_t
dev)
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{
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pnp_set_enable
(dev, 0);
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ite_reg_write
(dev, 0x70, 0x00);
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ite_reg_write
(dev, 0xf0, 0x00);
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ite_reg_write
(dev, 0xf1, 0x00);
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ite_reg_write
(dev, 0xf2, 0x06);
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ite_reg_write
(dev, 0xf3, 0x00);
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ite_reg_write
(dev, 0xf4, 0x00);
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ite_reg_write
(dev, 0xf5, 0x36);
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ite_reg_write
(dev, 0xf6, 0x03);
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ite_reg_write
(dev, 0xf9, 0x48);
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ite_reg_write
(dev, 0xfa, 0x00);
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ite_reg_write
(dev, 0xfb, 0x10);
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pnp_set_enable
(dev, 1);
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}
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/*
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* Sets up GPIO configuration as per vendor defaults
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* SIO defaults are unknown therefore all GPIO pins are configured
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*/
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static
void
ite_gpio_conf
(
pnp_devfn_t
dev)
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{
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ite_reg_write
(dev, 0x23, 0x08);
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ite_reg_write
(dev, 0x25, 0x10);
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ite_reg_write
(dev, 0x26, 0x00);
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ite_reg_write
(dev, 0x27, 0x80);
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ite_reg_write
(dev, 0x28, 0x45);
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ite_reg_write
(dev, 0x29, 0x00);
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ite_reg_write
(dev, 0x2a, 0x00);
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ite_reg_write
(dev, 0x2b, 0x48);
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ite_reg_write
(dev, 0x2c, 0x10);
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ite_reg_write
(dev, 0x2d, 0x80);
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ite_reg_write
(dev, 0x71, 0x00);
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ite_reg_write
(dev, 0x72, 0x00);
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ite_reg_write
(dev, 0x73, 0x38);
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ite_reg_write
(dev, 0x74, 0x00);
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ite_reg_write
(dev, 0xb0, 0x00);
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ite_reg_write
(dev, 0xb1, 0x00);
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ite_reg_write
(dev, 0xb2, 0x00);
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ite_reg_write
(dev, 0xb3, 0x00);
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ite_reg_write
(dev, 0xb4, 0x00);
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ite_reg_write
(dev, 0xb8, 0x00);
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ite_reg_write
(dev, 0xb9, 0x00);
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ite_reg_write
(dev, 0xba, 0x00);
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ite_reg_write
(dev, 0xbb, 0x00);
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ite_reg_write
(dev, 0xbc, 0x00);
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ite_reg_write
(dev, 0xbd, 0x00);
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ite_reg_write
(dev, 0xc0, 0x01);
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ite_reg_write
(dev, 0xc1, 0x00);
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ite_reg_write
(dev, 0xc2, 0x00);
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ite_reg_write
(dev, 0xc3, 0x00);
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ite_reg_write
(dev, 0xc4, 0x00);
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ite_reg_write
(dev, 0xc8, 0x01);
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ite_reg_write
(dev, 0xc9, 0x00);
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ite_reg_write
(dev, 0xca, 0x00);
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ite_reg_write
(dev, 0xcb, 0x00);
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ite_reg_write
(dev, 0xcc, 0x00);
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ite_reg_write
(dev, 0xcd, 0x20);
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ite_reg_write
(dev, 0xce, 0x00);
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ite_reg_write
(dev, 0xcf, 0x00);
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ite_reg_write
(dev, 0xe0, 0x00);
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ite_reg_write
(dev, 0xe1, 0x00);
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ite_reg_write
(dev, 0xe2, 0x00);
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ite_reg_write
(dev, 0xe3, 0x00);
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ite_reg_write
(dev, 0xe4, 0x00);
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ite_reg_write
(dev, 0xe9, 0x21);
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ite_reg_write
(dev, 0xf0, 0x00);
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ite_reg_write
(dev, 0xf1, 0x00);
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ite_reg_write
(dev, 0xf2, 0x00);
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ite_reg_write
(dev, 0xf3, 0x00);
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ite_reg_write
(dev, 0xf4, 0x00);
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ite_reg_write
(dev, 0xf5, 0x00);
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ite_reg_write
(dev, 0xf6, 0x00);
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ite_reg_write
(dev, 0xf7, 0x00);
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ite_reg_write
(dev, 0xf8, 0x00);
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ite_reg_write
(dev, 0xf9, 0x00);
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ite_reg_write
(dev, 0xfa, 0x00);
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ite_reg_write
(dev, 0xfb, 0x00);
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}
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void
bootblock_mainboard_early_init
(
void
)
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{
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u32
val
, i;
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/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
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pm_write8
(0xea, 0x1);
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/* Configure ClkDrvStr1 settings */
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misc_write32
(0x24, 0x030800aa);
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/* Configure MiscClkCntl1 settings */
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misc_write32
(0x40, 0x000c4050);
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/* Configure SIO as made under vendor BIOS */
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ite_gpio_conf
(
GPIO_DEV
);
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ite_evc_conf
(
ENVC_DEV
);
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/* Enable serial output on it8623e */
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ite_conf_clkin
(
CLKIN_DEV
,
ITE_UART_CLK_PREDIVIDE_48
);
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ite_enable_serial
(
SERIAL_DEV
, CONFIG_TTYS0_BASE);
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ite_kill_watchdog
(
GPIO_DEV
);
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/*
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* On Larne, after LpcClkDrvSth is set, it needs some time to be stable,
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* because of the buffer ICS551M
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*/
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for
(i = 0; i < 200000; i++)
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val
=
inb
(0xcd6);
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}
acpimmio.h
misc_write32
static void misc_write32(uint8_t reg, uint32_t value)
Definition:
acpimmio.h:281
pm_write8
static void pm_write8(uint8_t reg, uint8_t value)
Definition:
acpimmio.h:181
bootblock_common.h
inb
u8 inb(u16 port)
it8623e.h
ite_enable_serial
void ite_enable_serial(pnp_devfn_t dev, u16 iobase)
Definition:
early_serial.c:61
ite_reg_write
void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value)
Definition:
early_serial.c:41
ite_kill_watchdog
void ite_kill_watchdog(pnp_devfn_t dev)
Definition:
early_serial.c:129
ite_conf_clkin
void ite_conf_clkin(pnp_devfn_t dev, u8 predivide)
Definition:
early_serial.c:55
ite.h
ITE_UART_CLK_PREDIVIDE_48
#define ITE_UART_CLK_PREDIVIDE_48
Definition:
ite.h:9
bootblock_mainboard_early_init
__weak void bootblock_mainboard_early_init(void)
Definition:
bootblock.c:16
GPIO_DEV
#define GPIO_DEV
Definition:
bootblock.c:18
ite_evc_conf
static void ite_evc_conf(pnp_devfn_t dev)
Definition:
bootblock.c:23
ite_gpio_conf
static void ite_gpio_conf(pnp_devfn_t dev)
Definition:
bootblock.c:44
ENVC_DEV
#define ENVC_DEV
Definition:
bootblock.c:20
CLKIN_DEV
#define CLKIN_DEV
Definition:
bootblock.c:19
SERIAL_DEV
#define SERIAL_DEV
Definition:
bootblock.c:11
pnp_set_enable
void pnp_set_enable(struct device *dev, int enable)
Definition:
pnp_device.c:64
pnp_ops.h
pnp_devfn_t
u32 pnp_devfn_t
Definition:
pnp_type.h:8
u32
uint32_t u32
Definition:
stdint.h:51
val
u8 val
Definition:
sys.c:300
src
mainboard
asus
am1i-a
bootblock.c
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