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meminit.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_ELKHARTLAKE_MEMINIT_H_
4 #define _SOC_ELKHARTLAKE_MEMINIT_H_
5 
6 #include <fsp/soc_binding.h>
7 #include <types.h>
8 
9 /* Number of dq bits controlled per dqs */
10 #define DQ_BITS_PER_DQS 8
11 
12 /* Number of memory packages, where a "package" represents a 64-bit solution */
13 #define DDR_NUM_PACKAGES 2
14 
15 /* Number of DQ byte mappings */
16 #define DDR_NUM_BYTE_MAPPINGS 6
17 
18 /* Number of memory DIMM slots available on Elkhart Lake */
19 #define NUM_DIMM_SLOT 4
20 
21 /* 64-bit Channel identification */
22 enum {
26 };
27 
28 struct spd_by_pointer {
29  size_t spd_data_len;
31 };
32 
34  READ_SPD_CBFS, /* Find SPD file in CBFS. */
35  READ_SMBUS, /* Read on-module SPD by SMBUS. */
36  READ_SPD_MEMPTR /* Find SPD data from pointer. */
37 };
38 
39 struct spd_info {
41  union spd_data_by {
42  /* To read on-module SPD when read_type is READ_SMBUS. */
44 
45  /* To identify SPD file when read_type is READ_SPD_CBFS. */
46  int spd_index;
47 
48  /* To find SPD data when read_type is READ_SPD_MEMPTR. */
50  } spd_spec;
51 };
52 
53 /* Board-specific memory dq mapping information */
54 struct mb_cfg {
55 
56  /*
57  * For each channel, there are 6 sets of DQ byte mappings,
58  * where each set has a package 0 and a package 1 value (package 0
59  * represents the first 64-bit lpddr4 chip combination, and package 1
60  * represents the second 64-bit lpddr4 chip combination).
61  * The first three sets are for CLK, CMD, and CTL.
62  * The fsp package actually expects 6 sets, even though the last 3 sets
63  * are not used in EHL.
64  * We let the meminit_dq_dqs_map routine take care of clearing the
65  * unused fields for the caller.
66  * Note that dq_map is only used by LPDDR; it does not need to be
67  * initialized for designs using DDR4.
68  */
70 
71  /*
72  * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
73  * mapping of a dq bit on the CPU to the bit it's connected to on
74  * the memory part. The array index represents the dqs bit number
75  * on the memory part, and the values in the array represent which
76  * pin on the CPU that DRAM pin connects to.
77  * dqs_map is only used by LPDDR; same comments apply as for dq_map
78  * above.
79  */
81 
82  /*
83  * Rcomp resistor values. These values represent the resistance in
84  * ohms of the three rcomp resistors attached to the DDR_COMP_0,
85  * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
86  */
88 
89  /*
90  * Rcomp target values. These will typically be the following
91  * values for Elkhart Lake : { 60, 40, 30, 20, 30 }
92  */
94 
95  /*
96  * Indicates whether memory is interleaved.
97  * Set to 1 for an interleaved design,
98  * set to 0 for non-interleaved design.
99  */
101 
102  /*
103  * VREF_CA configuration.
104  * Set to 0 VREF_CA goes to both CH_A and CH_B,
105  * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
106  * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
107  */
109 
110  /*
111  * Early Command Training Enable/Disable Control
112  * 1 = enable, 0 = disable
113  */
115 
116  /* Board type */
117  uint8_t UserBd;
118 };
119 
120 /*
121  * Initialize default memory configurations for Elkhart Lake.
122  */
123 
124 void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
125  const struct spd_info *spd_info, bool half_populated);
126 
127 #endif /* _SOC_ELKHARTLAKE_MEMINIT_H_ */
void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated)
Definition: meminit.c:238
mem_info_read_type
@ DDR_CH0
Definition: meminit.h:23
@ DDR_NUM_CHANNELS
Definition: meminit.h:25
@ DDR_CH1
Definition: meminit.h:24
#define DDR_NUM_PACKAGES
Definition: meminit.h:13
#define DQ_BITS_PER_DQS
Definition: meminit.h:10
#define DDR_NUM_BYTE_MAPPINGS
Definition: meminit.h:16
@ READ_SPD_MEMPTR
Definition: meminit.h:36
@ READ_SMBUS
Definition: meminit.h:35
@ READ_SPD_CBFS
Definition: meminit.h:34
#define NUM_DIMM_SLOT
Definition: meminit.h:19
#define FSP_M_CONFIG
Definition: fsp_upd.h:8
static const struct mb_cfg board_cfg
Definition: romstage.c:8
unsigned short uint16_t
Definition: stdint.h:11
unsigned long uintptr_t
Definition: stdint.h:21
unsigned char uint8_t
Definition: stdint.h:8
Definition: meminit.h:71
uint16_t rcomp_targets[5]
Definition: meminit.h:93
uint8_t dq_pins_interleaved
Definition: meminit.h:100
uint8_t dqs_map[CONFIG_DATA_BUS_WIDTH/BITS_PER_BYTE]
Definition: meminit.h:90
uint8_t vref_ca_config
Definition: meminit.h:108
uint8_t ect
Definition: meminit.h:114
uint8_t UserBd
Definition: meminit.h:103
uint16_t rcomp_resistor[3]
Definition: meminit.h:87
uint8_t dq_map[CONFIG_DATA_BUS_WIDTH]
Definition: meminit.h:80
uintptr_t spd_data_ptr
Definition: spd.h:11
union spd_info::spd_data_by spd_spec
enum mem_info_read_type read_type
struct spd_by_pointer spd_data_ptr_info