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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
| #define | POST_RESET_VECTOR_CORRECT 0x01 |
| Entry into 'crt0.s'. More... | |
| #define | POST_ENTER_PROTECTED_MODE 0x10 |
| Entry into protected mode. More... | |
| #define | POST_PREPARE_RAMSTAGE 0x11 |
| Start copying coreboot to RAM with decompression if compressed. More... | |
| #define | POST_RAMSTAGE_IS_PREPARED 0x12 |
| Copy/decompression finished; jumping to RAM. More... | |
| #define | POST_ENTRY_C_START 0x13 |
| Entry into c_start. More... | |
| #define | POST_MEM_PREINIT_PREP_START 0x34 |
| Pre-memory init preparation start. More... | |
| #define | POST_MEM_PREINIT_PREP_END 0x36 |
| Pre-memory init preparation end. More... | |
| #define | POST_CONSOLE_READY 0x39 |
| Console is initialized. More... | |
| #define | POST_CONSOLE_BOOT_MSG 0x40 |
| Console boot message succeeded. More... | |
| #define | POST_ENABLING_CACHE 0x60 |
| Before enabling the cache. More... | |
| #define | POST_PRE_HARDWAREMAIN 0x6e |
| Pre call to RAM stage main() More... | |
| #define | POST_ENTRY_HARDWAREMAIN 0x6f |
| Entry into coreboot in RAM stage main() More... | |
| #define | POST_BS_PRE_DEVICE 0x70 |
| Before Device Probe. More... | |
| #define | POST_BS_DEV_INIT_CHIPS 0x71 |
| Initializing Chips. More... | |
| #define | POST_BS_DEV_ENUMERATE 0x72 |
| Starting Device Enumeration. More... | |
| #define | POST_BS_DEV_RESOURCES 0x73 |
| Device Resource Allocation. More... | |
| #define | POST_BS_DEV_ENABLE 0x74 |
| Device Enable. More... | |
| #define | POST_BS_DEV_INIT 0x75 |
| Device Initialization. More... | |
| #define | POST_BS_POST_DEVICE 0x76 |
| After Device Probe. More... | |
| #define | POST_BS_OS_RESUME_CHECK 0x77 |
| OS Resume Check. More... | |
| #define | POST_BS_OS_RESUME 0x78 |
| OS Resume. More... | |
| #define | POST_BS_WRITE_TABLES 0x79 |
| Write Tables. More... | |
| #define | POST_BS_PAYLOAD_LOAD 0x7a |
| Load Payload. More... | |
| #define | POST_BS_PAYLOAD_BOOT 0x7b |
| Boot Payload. More... | |
| #define | POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88 |
| Before calling FSP Notify (end of firmware) More... | |
| #define | POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89 |
| After calling FSP Notify (end of firmware) More... | |
| #define | POST_FSP_TEMP_RAM_INIT 0x90 |
| Before calling FSP TempRamInit. More... | |
| #define | POST_FSP_TEMP_RAM_EXIT 0x91 |
| Before calling FSP TempRamExit. More... | |
| #define | POST_FSP_MEMORY_INIT 0x92 |
| Before calling FSP MemoryInit. More... | |
| #define | POST_FSP_SILICON_INIT 0x93 |
| Before calling FSP SiliconInit. More... | |
| #define | POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94 |
| Before calling FSP Notify (after PCI enumeration) More... | |
| #define | POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95 |
| Before calling FSP Notify (ready to boot) More... | |
| #define | POST_OS_ENTER_PTS 0x96 |
| Indicate OS _PTS entry. More... | |
| #define | POST_OS_ENTER_WAKE 0x97 |
| Indicate OS _WAK entry. More... | |
| #define | POST_FSP_MEMORY_EXIT 0x98 |
| After calling FSP MemoryInit. More... | |
| #define | POST_FSP_SILICON_EXIT 0x99 |
| After calling FSP SiliconInit. More... | |
| #define | POST_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0 |
| Before calling FSP Multiphase SiliconInit. More... | |
| #define | POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1 |
| After calling FSP Multiphase SiliconInit. More... | |
| #define | POST_FSP_NOTIFY_AFTER_ENUMERATE 0xa2 |
| After calling FSP Notify (after PCI enumeration) More... | |
| #define | POST_FSP_NOTIFY_AFTER_FINALIZE 0xa3 |
| After calling FSP Notify (ready to boot) More... | |
| #define | POST_INVALID_ROM 0xe0 |
| Invalid or corrupt ROM. More... | |
| #define | POST_INVALID_CBFS 0xe1 |
| Invalid or corrupt CBFS. More... | |
| #define | POST_INVALID_VENDOR_BINARY 0xe2 |
| Vendor binary error. More... | |
| #define | POST_RAM_FAILURE 0xe3 |
| RAM failure. More... | |
| #define | POST_HW_INIT_FAILURE 0xe4 |
| Hardware initialization failure. More... | |
| #define | POST_VIDEO_FAILURE 0xe5 |
| Video failure. More... | |
| #define | POST_TPM_FAILURE 0xed |
| TPM failure. More... | |
| #define | POST_DEAD_CODE 0xee |
| Not supposed to get here. More... | |
| #define | POST_RESUME_FAILURE 0xef |
| Resume from suspend failed. More... | |
| #define | POST_JUMPING_TO_PAYLOAD 0xf3 |
| Jumping to payload. More... | |
| #define | POST_ENTER_ELF_BOOT 0xf8 |
| Entry into elf boot. More... | |
| #define | POST_OS_RESUME 0xfd |
| Final code before OS resumes. More... | |
| #define | POST_OS_BOOT 0xfe |
| Final code before OS boots. More... | |
| #define | POST_DIE 0xff |
| Elfload fail or die() called. More... | |
| #define POST_BS_DEV_ENABLE 0x74 |
| #define POST_BS_DEV_ENUMERATE 0x72 |
Starting Device Enumeration.
Boot State Machine: bs_dev_enumerate()
Definition at line 141 of file post_codes.h.
| #define POST_BS_DEV_INIT 0x75 |
Device Initialization.
Boot State Machine: bs_dev_init()
Definition at line 162 of file post_codes.h.
| #define POST_BS_DEV_INIT_CHIPS 0x71 |
Initializing Chips.
Boot State Machine: bs_dev_init_chips()
Definition at line 134 of file post_codes.h.
| #define POST_BS_DEV_RESOURCES 0x73 |
Device Resource Allocation.
Boot State Machine: bs_dev_resources()
Definition at line 148 of file post_codes.h.
| #define POST_BS_OS_RESUME 0x78 |
| #define POST_BS_OS_RESUME_CHECK 0x77 |
OS Resume Check.
Boot State Machine: bs_os_resume_check()
Definition at line 176 of file post_codes.h.
| #define POST_BS_PAYLOAD_BOOT 0x7b |
| #define POST_BS_PAYLOAD_LOAD 0x7a |
| #define POST_BS_POST_DEVICE 0x76 |
After Device Probe.
Boot State Machine: bs_post_device()
Definition at line 169 of file post_codes.h.
| #define POST_BS_PRE_DEVICE 0x70 |
Before Device Probe.
Boot State Machine: bs_pre_device()
Definition at line 127 of file post_codes.h.
| #define POST_BS_WRITE_TABLES 0x79 |
| #define POST_CONSOLE_BOOT_MSG 0x40 |
Console boot message succeeded.
First console message has been successfully sent through the console backend driver.
Definition at line 98 of file post_codes.h.
| #define POST_CONSOLE_READY 0x39 |
Console is initialized.
The console is initialized and is ready for usage
Definition at line 90 of file post_codes.h.
| #define POST_DEAD_CODE 0xee |
Not supposed to get here.
A function that should not have returned, returned
Check the console output for details.
Definition at line 376 of file post_codes.h.
| #define POST_DIE 0xff |
Elfload fail or die() called.
coreboot was not able to load the payload, no payload was detected or die() was called.
If this code appears before entering ramstage, then most likely ramstage is corrupted, and reflashing of the ROM chip is needed.
If this code appears after ramstage, there is a problem with the payload If the payload was built out-of-tree, check that it was compiled as a coreboot payload
Check the console output to see exactly where the failure occurred.
Definition at line 431 of file post_codes.h.
| #define POST_ENABLING_CACHE 0x60 |
| #define POST_ENTER_ELF_BOOT 0xf8 |
Entry into elf boot.
This POST code is called right before invoking jmp_to_elf_entry() jmp_to_elf_entry() invokes the payload, and should never return
Definition at line 400 of file post_codes.h.
| #define POST_ENTER_PROTECTED_MODE 0x10 |
Entry into protected mode.
Preparing to enter protected mode. This is POSTed right before changing to protected mode.
Definition at line 45 of file post_codes.h.
| #define POST_ENTRY_C_START 0x13 |
Entry into c_start.
c_start.S is the first code executing in ramstage.
Definition at line 67 of file post_codes.h.
| #define POST_ENTRY_HARDWAREMAIN 0x6f |
Entry into coreboot in RAM stage main()
This is the first call in hardwaremain.c. If this code is POSTed, then ramstage has successfully loaded and started executing.
Definition at line 120 of file post_codes.h.
| #define POST_FSP_MEMORY_EXIT 0x98 |
After calling FSP MemoryInit.
FSP binary returned from MemoryInit phase
Definition at line 281 of file post_codes.h.
| #define POST_FSP_MEMORY_INIT 0x92 |
Before calling FSP MemoryInit.
Going to call into FSP binary for MemoryInit phase
Definition at line 239 of file post_codes.h.
| #define POST_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0 |
Before calling FSP Multiphase SiliconInit.
Going to call into FSP binary for Multiple phase SI Init
Definition at line 295 of file post_codes.h.
| #define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1 |
After calling FSP Multiphase SiliconInit.
FSP binary returned from Multiple phase SI Init
Definition at line 302 of file post_codes.h.
| #define POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89 |
After calling FSP Notify (end of firmware)
Going to call into FSP binary for Notify phase (end of firmware)
Definition at line 218 of file post_codes.h.
| #define POST_FSP_NOTIFY_AFTER_ENUMERATE 0xa2 |
After calling FSP Notify (after PCI enumeration)
Going to call into FSP binary for Notify phase (after PCI enumeration)
Definition at line 309 of file post_codes.h.
| #define POST_FSP_NOTIFY_AFTER_FINALIZE 0xa3 |
After calling FSP Notify (ready to boot)
Going to call into FSP binary for Notify phase (ready to boot)
Definition at line 316 of file post_codes.h.
| #define POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88 |
Before calling FSP Notify (end of firmware)
Going to call into FSP binary for Notify phase (end of firmware)
Definition at line 211 of file post_codes.h.
| #define POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94 |
Before calling FSP Notify (after PCI enumeration)
Going to call into FSP binary for Notify phase (after PCI enumeration)
Definition at line 253 of file post_codes.h.
| #define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95 |
Before calling FSP Notify (ready to boot)
Going to call into FSP binary for Notify phase (ready to boot)
Definition at line 260 of file post_codes.h.
| #define POST_FSP_SILICON_EXIT 0x99 |
After calling FSP SiliconInit.
FSP binary returned from SiliconInit phase
Definition at line 288 of file post_codes.h.
| #define POST_FSP_SILICON_INIT 0x93 |
Before calling FSP SiliconInit.
Going to call into FSP binary for SiliconInit phase
Definition at line 246 of file post_codes.h.
| #define POST_FSP_TEMP_RAM_EXIT 0x91 |
Before calling FSP TempRamExit.
Going to call into FSP binary for TempRamExit phase
Definition at line 232 of file post_codes.h.
| #define POST_FSP_TEMP_RAM_INIT 0x90 |
Before calling FSP TempRamInit.
Going to call into FSP binary for TempRamInit phase
Definition at line 225 of file post_codes.h.
| #define POST_HW_INIT_FAILURE 0xe4 |
Hardware initialization failure.
Set when a required hardware component was not found or is unsupported.
Definition at line 353 of file post_codes.h.
| #define POST_INVALID_CBFS 0xe1 |
Invalid or corrupt CBFS.
Set if firmware failed to find or validate a resource that is stored in CBFS.
Definition at line 330 of file post_codes.h.
| #define POST_INVALID_ROM 0xe0 |
Invalid or corrupt ROM.
Set if firmware failed to find or validate a resource that is stored in ROM.
Definition at line 323 of file post_codes.h.
| #define POST_INVALID_VENDOR_BINARY 0xe2 |
Vendor binary error.
Set if firmware failed to find or validate a vendor binary, or the binary generated a fatal error.
Definition at line 338 of file post_codes.h.
| #define POST_JUMPING_TO_PAYLOAD 0xf3 |
Jumping to payload.
Called right before jumping to a payload. If the boot sequence stops with this code, chances are the payload freezes.
Definition at line 392 of file post_codes.h.
| #define POST_MEM_PREINIT_PREP_END 0x36 |
Pre-memory init preparation end.
Post code emitted in romstage after returning from SoC/mainboard callbacks to prepare params for FSP memory init.
Definition at line 83 of file post_codes.h.
| #define POST_MEM_PREINIT_PREP_START 0x34 |
Pre-memory init preparation start.
Post code emitted in romstage before making callbacks to allow SoC/mainboard to prepare params for FSP memory init.
Definition at line 75 of file post_codes.h.
| #define POST_OS_BOOT 0xfe |
Final code before OS boots.
This may not be called depending on the payload used.
Definition at line 414 of file post_codes.h.
| #define POST_OS_ENTER_PTS 0x96 |
| #define POST_OS_ENTER_WAKE 0x97 |
| #define POST_OS_RESUME 0xfd |
Final code before OS resumes.
Called right before jumping to the OS resume vector.
Definition at line 407 of file post_codes.h.
| #define POST_PRE_HARDWAREMAIN 0x6e |
Pre call to RAM stage main()
POSTed right before RAM stage main() is called from c_start.S
Definition at line 112 of file post_codes.h.
| #define POST_PREPARE_RAMSTAGE 0x11 |
Start copying coreboot to RAM with decompression if compressed.
POSTed before ramstage is about to be loaded into memory
Definition at line 52 of file post_codes.h.
| #define POST_RAM_FAILURE 0xe3 |
RAM failure.
Set if RAM could not be initialized. This includes RAM is missing, unsupported RAM configuration, or RAM failure.
Definition at line 346 of file post_codes.h.
| #define POST_RAMSTAGE_IS_PREPARED 0x12 |
Copy/decompression finished; jumping to RAM.
This is called after ramstage is loaded in memory, and before the code jumps there. This represents the end of romstage.
Definition at line 60 of file post_codes.h.
| #define POST_RESET_VECTOR_CORRECT 0x01 |
Entry into 'crt0.s'.
reset code jumps to here
First instruction that gets executed after the reset vector jumps. This indicates that the reset vector points to the correct code segment.
Definition at line 37 of file post_codes.h.
| #define POST_RESUME_FAILURE 0xef |
Resume from suspend failed.
This post code is sent when the firmware is expected to resume it is unable to do so.
Definition at line 384 of file post_codes.h.
| #define POST_TPM_FAILURE 0xed |
TPM failure.
An error with the TPM, either unexpected state or communications failure.
Definition at line 367 of file post_codes.h.
| #define POST_VIDEO_FAILURE 0xe5 |
1.9.1