3 #ifndef SOC_MEDIATEK_MT8195_INFRACFG_H
4 #define SOC_MEDIATEK_MT8195_INFRACFG_H
6 #include <soc/addressmap.h>
check_member(mt8173_infracfg_regs, infra_pdn0, 0x40)
static struct mt8195_infracfg_ao_regs *const mt8195_infracfg_ao
u32 gcpu_aor_sbc_pubk_hv5
u32 infra_topaxi_protecten_mm_sta0
u32 gcpu_aor_sbc_pubk_hv4
u32 infra_topaxi_aslice_ctrl_3
u32 infra_nna0_master_gals_ctrl
u32 infra_mci_cg_mfg_sec_sta
u32 infra_topaxi_protecten
u32 infra_ao_sec_rst_con1
u32 infra_topaxi_protecten_set
u32 infra_globalcon_dcmctl
u32 infra_globalcon_rst0_sta
u32 infra_topaxi_protecten_vdnr
u32 infra_topaxi_protecten_vdnr_sta0_2
u32 infra_topaxi_protecten_mm_clr_2
u32 gcpu_aor_sbc_pubk_hv10
u32 mcu2ifr_reg_parity_dbg_aw_2
u32 infra_globalcon_rst2_set
u32 infra_top_master_sideband
u32 infra_topaxi_bus_dbg_con_ao
u32 infra_topaxi_protecten_vdnr_sta0_1
u32 infra_topaxi_aslice_ctrl_4
u32 infra_topaxi_aslice_ctrl
u32 infra_ao_cksys_apb_async_sta
u32 infra_topaxi_protecten_sta1_2
u32 infra_topaxi_protecten_vdnr_set_1
u32 infra_topaxi_protecten_vdnr_set
u32 gcpu_aor_sbc_pubk_hv8
u32 infra_topaxi_protecten_sta1
u32 infra_topaxi_cbip_aslice_ctrl
u32 infra_topaxi_protecten_mm_set_2
u32 infra_topaxi_protecten_mm_sta1_2
u32 gcpu_aor_sbc_pubk_hv9
u32 infra_topaxi_protecten_sub_infra_vdnr_sta1
u32 infra_globalcon_rst3_sta
u32 infra_topaxi_protecten_sta1_1
u32 infra_conn2ap_int_mask
u32 infra_topaxi_protecten_mcu
u32 infra_topaxi_protecten_sta0_2
u32 infra_topaxi_protecten_sta0
u32 mcu2emi_m0_parity_dbg_aw_1
u32 infra_mcu2apu_asl0_ctl
u32 infra_globalcon_rst1_clr
u32 infra_topaxi_protecten_sta0_1
u32 infra_mfg_master_m0_gals_ctrl
u32 infra_topaxi_protecten_vdnr_1
u32 infra_topaxi_aslice_ctrl_2
u32 infra_topaxi_protecten_set_2
u32 infra_topaxi_protecten_vdnr_sta1
u32 infra_topaxi_aslice_ctrl_1
u32 infra_topaxi_protecten_1_set
u32 gcpu_aor_lock_sbc_pubk_hv
u32 infra_apu_slave_gals_ctrl
u32 gcpu_aor_sbc_pubk_hv11
u32 infra_globalcon_rst3_set
u32 infra_ao_sec_rst_con3
u32 infra_globalcon_rst0_clr
u32 infra_mcu_decoder_infra_ctl
u32 infra_globalcon_rst4_sta
u32 mcu2ifr_reg_parity_dbg_ar_1
u32 infra_ao_scpsys_apb_async_sta
u32 infra_topaxi_protecten_vdnr_clr
u32 infra_topaxi_protecten_mcu_clr
u32 infra_mci_trans_con_read
u32 infra_mcu_decoder_sta0
u32 mcu2emi_m1_parity_dbg_aw_1
u32 infra_mci_id_remap_con
u32 mcu2ifr_reg_parity_dbg_aw_1
u32 infra_mcu_path_sync_ctl
u32 infra_apu_master_m1_gals_ctl
u32 infra_mcu2reg_asl0_ctl
u32 gcpu_aor_sbc_pubk_hv0
u32 infra_mfg_master_m1_gals_ctrl
u32 infra_topaxi_emi_gmc_l2c_ctrl
u32 infra_mcu_pwr_ctl_mask
u32 infra_globalcon_rst4_set
u32 infra_topaxi_protecten_1
u32 infra_topaxi_cbip_slice_ctrl
u32 infra_globalcon_rst1_sta
u32 infra_nna1_slave_gals_ctrl
u32 infra_ao_sec_rst_con4
u32 infra_mci_emi_trans_con
u32 infra_topaxi_protecten_mm_set
u32 gcpu_aor_sbc_pubk_hv1
u32 infra_topaxi_protecten_sub_infra_vdnr_sta0
u32 infra_topaxi_protecten_vdnr_clr_2
u32 infra_topaxi_protecten_sub_infra_vdnr_set
u32 mcu2emi_m0_parity_dbg_ar_2
u32 infra_nna1_master_gals_ctrl
u32 infra_topaxi_protecten_sub_infra_vdnr
u32 mcu2emi_m0_parity_dbg_ar_1
u32 infra_topaxi_protecten_mcu_sta1
u32 ifr_l3c2mcu_parity_dbg_r_1
u32 infra_topaxi_protecten_mm_sta1
u32 infra_mcu_decoder_sta1
u32 infra_topaxi_protecten_vdnr_sta1_2
u32 mcu2emi_m0_parity_dbg_aw_2
u32 infra_globalcon_rst2_sta
u32 infra_topaxi_protecten_clr_2
u32 infra_apu_master_m0_gals_ctl
u32 peri_cci_sideband_con
u32 infra_globalcon_rst1_set
u32 infra_topaxi_protecten_mm_2
u32 mcu2emi_m1_parity_dbg_ar_2
u32 infra_topaxi_protecten_vdnr_set_2
u32 infra_topaxi_protecten_mm_clr
u32 gcpu_aor_sbc_pubk_hv7
u32 infra_topaxi_fmem_mdhw_ctrl
u32 infra_globalcon_rst3_clr
u32 mcu2ifr_reg_parity_dbg_ar_2
u32 gcpu_aor_sbc_pubk_hv2
u32 infra_topaxi_protecten_2
u32 infra_ao_pmic_wrap_tx_apb_async_sta
u32 infra_topaxi_protecten_mcu_set
u32 infra_topaxi_protecten_vdnr_sta0
u32 infra_ao_sec_rst_con0
u32 infra_topaxi_cbip_slice_ctrl_2
u32 infra_mfg_slave_gals_ctrl
u32 infra_nna0_slave_gals_ctrl
u32 infra_topaxi_protecten_vdnr_sta1_1
u32 infra_topaxi_protecten_mcu_sta0
u32 infra_topaxi_mdbus_ctl
u32 infra_globalcon_rst2_clr
u32 infra_topaxi_cbip_slice_ctrl_1
u32 infra_globalcon_rst4_clr
u32 gcpu_aor_sbc_pubk_hv6
u32 infra_ao_md32_tx_apb_async_sta
u32 infra_mci_trans_con_write
u32 infra_ao_md32_rx_apb_async_sta
u32 infra_topaxi_protecten_clr
u32 mcu2emi_m1_parity_dbg_ar_1
u32 infra_top_master_sideband_1
u32 infra_topaxi_protecten_mm_sta0_2
u32 gcpu_aor_sbc_pubk_hv3
u32 infra_topaxi_protecten_sub_infra_vdnr_clr
u32 mcu2emi_m1_parity_dbg_aw_2
u32 infra_topaxi_protecten_1_clr
u32 infra_topaxi_protecten_vdnr_2
u32 infra_topaxi_protecten_mm
u32 infra_ao_sec_rst_con2
u32 infra_topaxi_protecten_vdnr_clr_1
u32 infra_idle_async_bit_en_0
u32 infra_aximem_idle_bit_en_0
u32 infra_globalcon_rst0_set