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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <acpi/acpi.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/device.h>
#include <drivers/tpm/cr50.h>
#include <ec/ec.h>
#include <security/tpm/tss.h>
#include <soc/soc_chip.h>
#include <vb2_api.h>
Go to the source code of this file.
Functions | |
static void | mainboard_update_soc_chip_config (void) |
static void | mainboard_init (void *chip_info) |
void __weak | variant_devtree_update (void) |
static void | mainboard_dev_init (struct device *dev) |
static unsigned long | mainboard_write_acpi_tables (const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) |
static void | mainboard_enable (struct device *dev) |
Variables | |
struct chip_operations | mainboard_ops |
Definition at line 55 of file mainboard.c.
References mainboard_ec_init().
Referenced by mainboard_enable().
Definition at line 66 of file mainboard.c.
References device_operations::init, mainboard_dev_init(), mainboard_write_acpi_tables(), and device::ops.
Definition at line 32 of file mainboard.c.
References CONFIG, gpio_configure_pads_with_override(), mainboard_update_soc_chip_config(), variant_base_gpio_table(), variant_devtree_update(), and variant_override_gpio_table().
Definition at line 13 of file mainboard.c.
References BIOS_ERR, BIOS_INFO, config_of_soc, cr50_is_long_interrupt_pulse_enabled(), soc_intel_jasperlake_config::gpio_override_pm, soc_intel_jasperlake_config::gpio_pm, memset(), printk, and tlcl_lib_init().
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static |
Definition at line 60 of file mainboard.c.
Referenced by mainboard_enable().
Definition at line 50 of file mainboard.c.
struct chip_operations mainboard_ops |
Definition at line 66 of file mainboard.c.