coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <gpio.h>
6 #include <soc/gpio.h>
8 
9 static const struct soc_amd_gpio berknip_bid1_gpio_set_stage_ram[] = {
10  /* PEN_DETECT_ODL - no used */
11  PAD_NC(GPIO_4),
12  /* PEN_POWER_EN - no used */
13  PAD_NC(GPIO_5),
14  /* DMIC_SEL */
15  PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
16  /* USB_OC4_L - USB_A1 */
17  PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE),
18  /* USB_OC2_L - USB A0 */
19  PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE),
20  /* EN_PWR_WIFI */
21  PAD_GPO(GPIO_29, HIGH),
22  /* EN_PWR_TOUCHPAD_PS2 */
23  PAD_GPO(GPIO_67, HIGH),
24  /* MST_GPIO_2 (Fw Update HDMI hub) */
26  /* EN_DEV_BEEP_L */
27  PAD_GPO(GPIO_89, HIGH),
28  /* MST_GPIO_3 (Fw Update HDMI hub) */
30  /* USI_RESET */
31  PAD_GPO(GPIO_140, HIGH),
32 };
33 
34 static const struct soc_amd_gpio berknip_bid2_gpio_set_stage_ram[] = {
35  /* PEN_DETECT_ODL - no used */
36  PAD_NC(GPIO_4),
37  /* PEN_POWER_EN - no used */
38  PAD_NC(GPIO_5),
39  /* EN_DEV_BEEP_L */
40  PAD_GPO(GPIO_89, HIGH),
41  /* TP */
42  PAD_NC(GPIO_90),
43  /* USI_RESET */
44  PAD_GPO(GPIO_140, HIGH),
45 };
46 
47 static const struct soc_amd_gpio berknip_gpio_set_stage_ram[] = {
48  /* PEN_DETECT_ODL - no used */
49  PAD_NC(GPIO_4),
50  /* PEN_POWER_EN - no used */
51  PAD_NC(GPIO_5),
52 };
53 
54 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
55 {
56  uint32_t board_version;
57 
58  /*
59  * If board version cannot be read, assume that this is an older revision of the board
60  * and so apply overrides. If board version is provided by the EC, then apply overrides
61  * if version < 2.
62  */
63  if (google_chromeec_cbi_get_board_version(&board_version) != 0)
64  board_version = 1;
65 
66  if (board_version <= 1) {
69  } else if (board_version <= 2) {
72  }
73 
76 }
#define GPIO_18
Definition: gpio_ftns.h:17
#define ARRAY_SIZE(a)
Definition: helpers.h:12
int google_chromeec_cbi_get_board_version(uint32_t *version)
Definition: ec.c:870
#define PULL_NONE
Definition: buildOpts.c:72
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition: gpio.c:450
static const struct soc_amd_gpio berknip_bid2_gpio_set_stage_ram[]
Definition: gpio.c:34
static const struct soc_amd_gpio berknip_bid1_gpio_set_stage_ram[]
Definition: gpio.c:9
static const struct soc_amd_gpio berknip_gpio_set_stage_ram[]
Definition: gpio.c:47
#define GPIO_90
Definition: gpio.h:66
#define GPIO_89
Definition: gpio.h:65
#define GPIO_5
Definition: gpio.h:26
#define GPIO_67
Definition: gpio.h:53
#define GPIO_4
Definition: gpio.h:25
#define GPIO_140
Definition: gpio.h:87
#define GPIO_29
Definition: gpio.h:45
#define GPIO_86
Definition: gpio.h:62
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define PAD_GPO(pin, direction)
Definition: gpio_defs.h:220
#define PAD_NF(pin, func, pull)
Definition: gpio_defs.h:208
#define PAD_GPI(pin, pull)
Definition: gpio_defs.h:216
#define GPIO_14
Definition: gpio.h:35
#define GPIO_13
Definition: gpio.h:34
unsigned int uint32_t
Definition: stdint.h:14