Macros
#define	ABASE 0x40

#define	ACTL 0x44

#define	PWRM_EN (1 << 8)

#define	ACPI_EN (1 << 7)

#define	SCI_IRQ_SEL (7 << 0)

#define	SCIS_IRQ9 0

#define	SCIS_IRQ10 1

#define	SCIS_IRQ11 2

#define	SCIS_IRQ20 4

#define	SCIS_IRQ21 5

#define	SCIS_IRQ22 6

#define	SCIS_IRQ23 7

#define	PWRMBASE 0x48

#define	GEN_PMCON_A 0xa0

#define	DC_PP_DIS (1 << 30)

#define	DSX_PP_DIS (1 << 29)

#define	AG3_PP_EN (1 << 28)

#define	SX_PP_EN (1 << 27)

#define	DISB (1 << 23)

#define	MEM_SR (1 << 21)

#define	MS4V (1 << 18)

#define	GBL_RST_STS (1 << 16)

#define	ALLOW_ICLK_PLL_SD_INC0 (1 << 15)

#define	MPHY_CRICLK_GATE_OVER (1 << 14)

#define	ALLOW_OPI_PLL_SD_INC0 (1 << 13)

#define	ALLOW_SPXB_CG_INC0 (1 << 12)

#define	BIOS_PCI_EXP_EN (1 << 10)

#define	PWRBTN_LVL (1 << 9)

#define	ALLOW_L1LOW_C0 (1 << 7)

#define	ALLOW_L1LOW_OPI_ON (1 << 6)

#define	SMI_LOCK (1 << 4)

#define	GEN_PMCON_B 0xa4

#define	SLP_STR_POL_LOCK (1 << 18)

#define	ACPI_BASE_LOCK (1 << 17)

#define	SUS_PWR_FLR (1 << 14)

#define	WOL_EN_OVRD (1 << 13)

#define	DIS_SLP_X_STRCH_SUS_UP (1 << 12)

#define	SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10)

#define	SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)

#define	SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)

#define	SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)

#define	SLP_S3_MIN_ASST_WDTH_2S (3 << 10)

#define	HOST_RST_STS (1 << 9)

#define	S4MAW_MASK (0x3 << 4)

#define	S4MAW_1S (1 << 4)

#define	S4MAW_2S (2 << 4)

#define	S4MAW_3S (3 << 4)

#define	S4MAW_4S (0 << 4)

#define	S4ASE (1 << 3)

#define	RTC_BATTERY_DEAD (1 << 2)

#define	PWR_FLR (1 << 1)

#define	SLEEP_AFTER_POWER_FAIL (1 << 0)

#define	ETR3 0xac

#define	ETR3_CF9LOCK (1 << 31)

#define	ETR3_CF9GR (1 << 20)

#define	SCI_IRQ_ADJUST 0

#define	IRQ_REG ACTL

#define	S3_PWRGATE_POL 0x28

#define	S3DC_GATE_SUS (1 << 1)

#define	S3AC_GATE_SUS (1 << 0)

#define	S4_PWRGATE_POL 0x2c

#define	S4DC_GATE_SUS (1 << 1)

#define	S4AC_GATE_SUS (1 << 0)

#define	S5_PWRGATE_POL 0x30

#define	S5DC_GATE_SUS (1 << 15)

#define	S5AC_GATE_SUS (1 << 14)

#define	DSX_CFG 0x34

#define	DSX_CFG_MASK 0x7

#define	DSX_EN_WAKE_PIN (1 << 2)

#define	DSX_DIS_AC_PRESENT_PD (1 << 1)

#define	DSX_EN_LAN_WAKE_PIN (1 << 0)

#define	PMSYNC_TPR_CFG 0xc4

#define	PMSYNC_LOCK (1 << 31)

#define	PCH_PWRM_ACPI_TMR_CTL 0xfc

#define	ACPI_TIM_DIS (1 << 1)

#define	GPIO_GPE_CFG 0x120

#define	GPE0_DWX_MASK 0xf

#define	GPE0_DW_SHIFT(x) (4*(x))

#define	GBLRST_CAUSE0 0x124

#define	GBLRST_CAUSE1 0x128

#define	SLP_S0_RES 0x13c

#define	CPPMVRIC 0x31c

#define	XTALSDQDIS (1 << 22)

Macro Definition Documentation

◆ ABASE

#define ABASE 0x40

Definition at line 7 of file pmc.h.

◆ ACPI_BASE_LOCK

#define ACPI_BASE_LOCK (1 << 17)

Definition at line 40 of file pmc.h.

◆ ACPI_EN

#define ACPI_EN (1 << 7)

Definition at line 10 of file pmc.h.

◆ ACPI_TIM_DIS

#define ACPI_TIM_DIS (1 << 1)

Definition at line 83 of file pmc.h.

◆ ACTL

#define ACTL 0x44

Definition at line 8 of file pmc.h.

◆ AG3_PP_EN

#define AG3_PP_EN (1 << 28)

Definition at line 23 of file pmc.h.

◆ ALLOW_ICLK_PLL_SD_INC0

#define ALLOW_ICLK_PLL_SD_INC0 (1 << 15)

Definition at line 29 of file pmc.h.

◆ ALLOW_L1LOW_C0

#define ALLOW_L1LOW_C0 (1 << 7)

Definition at line 35 of file pmc.h.

◆ ALLOW_L1LOW_OPI_ON

#define ALLOW_L1LOW_OPI_ON (1 << 6)

Definition at line 36 of file pmc.h.

◆ ALLOW_OPI_PLL_SD_INC0

#define ALLOW_OPI_PLL_SD_INC0 (1 << 13)

Definition at line 31 of file pmc.h.

◆ ALLOW_SPXB_CG_INC0

#define ALLOW_SPXB_CG_INC0 (1 << 12)

Definition at line 32 of file pmc.h.

◆ BIOS_PCI_EXP_EN

#define BIOS_PCI_EXP_EN (1 << 10)

Definition at line 33 of file pmc.h.

◆ CPPMVRIC

#define CPPMVRIC 0x31c

Definition at line 90 of file pmc.h.

◆ DC_PP_DIS

#define DC_PP_DIS (1 << 30)

Definition at line 21 of file pmc.h.

◆ DIS_SLP_X_STRCH_SUS_UP

#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)

Definition at line 43 of file pmc.h.

◆ DISB

#define DISB (1 << 23)

Definition at line 25 of file pmc.h.

◆ DSX_CFG

#define DSX_CFG 0x34

Definition at line 75 of file pmc.h.

◆ DSX_CFG_MASK

#define DSX_CFG_MASK 0x7

Definition at line 76 of file pmc.h.

◆ DSX_DIS_AC_PRESENT_PD

#define DSX_DIS_AC_PRESENT_PD (1 << 1)

Definition at line 78 of file pmc.h.

◆ DSX_EN_LAN_WAKE_PIN

#define DSX_EN_LAN_WAKE_PIN (1 << 0)

Definition at line 79 of file pmc.h.

◆ DSX_EN_WAKE_PIN

#define DSX_EN_WAKE_PIN (1 << 2)

Definition at line 77 of file pmc.h.

◆ DSX_PP_DIS

#define DSX_PP_DIS (1 << 29)

Definition at line 22 of file pmc.h.

◆ ETR3

#define ETR3 0xac

Definition at line 59 of file pmc.h.

◆ ETR3_CF9GR

#define ETR3_CF9GR (1 << 20)

Definition at line 61 of file pmc.h.

◆ ETR3_CF9LOCK

#define ETR3_CF9LOCK (1 << 31)

Definition at line 60 of file pmc.h.

◆ GBL_RST_STS

#define GBL_RST_STS (1 << 16)

Definition at line 28 of file pmc.h.

◆ GBLRST_CAUSE0

#define GBLRST_CAUSE0 0x124

Definition at line 87 of file pmc.h.

◆ GBLRST_CAUSE1

#define GBLRST_CAUSE1 0x128

Definition at line 88 of file pmc.h.

◆ GEN_PMCON_A

#define GEN_PMCON_A 0xa0

Definition at line 20 of file pmc.h.

◆ GEN_PMCON_B

#define GEN_PMCON_B 0xa4

Definition at line 38 of file pmc.h.

◆ GPE0_DW_SHIFT

#define GPE0_DW_SHIFT ( x ) (4*(x))

Definition at line 86 of file pmc.h.

◆ GPE0_DWX_MASK

#define GPE0_DWX_MASK 0xf

Definition at line 85 of file pmc.h.

◆ GPIO_GPE_CFG

#define GPIO_GPE_CFG 0x120

Definition at line 84 of file pmc.h.

◆ HOST_RST_STS

#define HOST_RST_STS (1 << 9)

Definition at line 49 of file pmc.h.

◆ IRQ_REG

#define IRQ_REG ACTL

Definition at line 63 of file pmc.h.

◆ MEM_SR

#define MEM_SR (1 << 21)

Definition at line 26 of file pmc.h.

◆ MPHY_CRICLK_GATE_OVER

#define MPHY_CRICLK_GATE_OVER (1 << 14)

Definition at line 30 of file pmc.h.

◆ MS4V

#define MS4V (1 << 18)

Definition at line 27 of file pmc.h.

◆ PCH_PWRM_ACPI_TMR_CTL

#define PCH_PWRM_ACPI_TMR_CTL 0xfc

Definition at line 82 of file pmc.h.

◆ PMSYNC_LOCK

#define PMSYNC_LOCK (1 << 31)

Definition at line 81 of file pmc.h.

◆ PMSYNC_TPR_CFG

#define PMSYNC_TPR_CFG 0xc4

Definition at line 80 of file pmc.h.

◆ PWR_FLR

#define PWR_FLR (1 << 1)

Definition at line 57 of file pmc.h.

◆ PWRBTN_LVL

#define PWRBTN_LVL (1 << 9)

Definition at line 34 of file pmc.h.

◆ PWRM_EN

#define PWRM_EN (1 << 8)

Definition at line 9 of file pmc.h.

◆ PWRMBASE

#define PWRMBASE 0x48

Definition at line 19 of file pmc.h.

◆ RTC_BATTERY_DEAD

#define RTC_BATTERY_DEAD (1 << 2)

Definition at line 56 of file pmc.h.

◆ S3_PWRGATE_POL

#define S3_PWRGATE_POL 0x28

Definition at line 66 of file pmc.h.

◆ S3AC_GATE_SUS

#define S3AC_GATE_SUS (1 << 0)

Definition at line 68 of file pmc.h.

◆ S3DC_GATE_SUS

#define S3DC_GATE_SUS (1 << 1)

Definition at line 67 of file pmc.h.

◆ S4_PWRGATE_POL

#define S4_PWRGATE_POL 0x2c

Definition at line 69 of file pmc.h.

◆ S4AC_GATE_SUS

#define S4AC_GATE_SUS (1 << 0)

Definition at line 71 of file pmc.h.

◆ S4ASE

#define S4ASE (1 << 3)

Definition at line 55 of file pmc.h.

◆ S4DC_GATE_SUS

#define S4DC_GATE_SUS (1 << 1)

Definition at line 70 of file pmc.h.

◆ S4MAW_1S

#define S4MAW_1S (1 << 4)

Definition at line 51 of file pmc.h.

◆ S4MAW_2S

#define S4MAW_2S (2 << 4)

Definition at line 52 of file pmc.h.

◆ S4MAW_3S

#define S4MAW_3S (3 << 4)

Definition at line 53 of file pmc.h.

◆ S4MAW_4S

#define S4MAW_4S (0 << 4)

Definition at line 54 of file pmc.h.

◆ S4MAW_MASK

#define S4MAW_MASK (0x3 << 4)

Definition at line 50 of file pmc.h.

◆ S5_PWRGATE_POL

#define S5_PWRGATE_POL 0x30

Definition at line 72 of file pmc.h.

◆ S5AC_GATE_SUS

#define S5AC_GATE_SUS (1 << 14)

Definition at line 74 of file pmc.h.

◆ S5DC_GATE_SUS

#define S5DC_GATE_SUS (1 << 15)

Definition at line 73 of file pmc.h.

◆ SCI_IRQ_ADJUST

#define SCI_IRQ_ADJUST 0

Definition at line 62 of file pmc.h.

◆ SCI_IRQ_SEL

#define SCI_IRQ_SEL (7 << 0)

Definition at line 11 of file pmc.h.

◆ SCIS_IRQ10

#define SCIS_IRQ10 1

Definition at line 13 of file pmc.h.

◆ SCIS_IRQ11

#define SCIS_IRQ11 2

Definition at line 14 of file pmc.h.

◆ SCIS_IRQ20

#define SCIS_IRQ20 4

Definition at line 15 of file pmc.h.

◆ SCIS_IRQ21

#define SCIS_IRQ21 5

Definition at line 16 of file pmc.h.

◆ SCIS_IRQ22

#define SCIS_IRQ22 6

Definition at line 17 of file pmc.h.

◆ SCIS_IRQ23

#define SCIS_IRQ23 7

Definition at line 18 of file pmc.h.

◆ SCIS_IRQ9

#define SCIS_IRQ9 0

Definition at line 12 of file pmc.h.

◆ SLEEP_AFTER_POWER_FAIL

#define SLEEP_AFTER_POWER_FAIL (1 << 0)

Definition at line 58 of file pmc.h.

◆ SLP_S0_RES

#define SLP_S0_RES 0x13c

Definition at line 89 of file pmc.h.

◆ SLP_S3_MIN_ASST_WDTH_1MS

#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)

Definition at line 46 of file pmc.h.

◆ SLP_S3_MIN_ASST_WDTH_2S

#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)

Definition at line 48 of file pmc.h.

◆ SLP_S3_MIN_ASST_WDTH_50MS

#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)

Definition at line 47 of file pmc.h.

◆ SLP_S3_MIN_ASST_WDTH_60USEC

#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)

Definition at line 45 of file pmc.h.

◆ SLP_S3_MIN_ASST_WDTH_MASK

#define SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10)

Definition at line 44 of file pmc.h.

◆ SLP_STR_POL_LOCK

#define SLP_STR_POL_LOCK (1 << 18)

Definition at line 39 of file pmc.h.

◆ SMI_LOCK

#define SMI_LOCK (1 << 4)

Definition at line 37 of file pmc.h.

◆ SUS_PWR_FLR

#define SUS_PWR_FLR (1 << 14)

Definition at line 41 of file pmc.h.

◆ SX_PP_EN

#define SX_PP_EN (1 << 27)

Definition at line 24 of file pmc.h.

◆ WOL_EN_OVRD

#define WOL_EN_OVRD (1 << 13)

Definition at line 42 of file pmc.h.

◆ XTALSDQDIS

#define XTALSDQDIS (1 << 22)

Definition at line 91 of file pmc.h.

Macros