coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smi.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_MEDIATEK_MT8183_SMI_H
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#define SOC_MEDIATEK_MT8183_SMI_H
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#include <soc/addressmap.h>
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#include <types.h>
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struct
mt8183_smi_regs
{
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u32
reserved1
[64];
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u32
smi_l1len
;
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u32
smi_l1arb0
;
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u32
smi_l1arb1
;
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u32
smi_l1arb2
;
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u32
smi_l1arb3
;
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u32
smi_l1arb4
;
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u32
smi_l1arb5
;
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u32
smi_l1arb6
;
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u32
smi_l1arb7
;
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u32
reserved2
[31];
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u32
smi_mon_axi_ena
;
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u32
smi_mon_axi_clr
;
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u32
reserved3
[1];
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u32
smi_mon_axi_type
;
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u32
smi_mon_axi_con
;
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u32
reserved4
[3];
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u32
smi_mon_axi_act_cnt
;
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u32
smi_mon_axi_req_cnt
;
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u32
smi_mon_axi_ostd_cnt
;
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u32
smi_mon_axi_bea_cnt
;
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u32
smi_mon_axi_byt_cnt
;
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u32
smi_mon_axi_cp_cnt
;
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u32
smi_mon_axi_dp_cnt
;
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u32
smi_mon_axi_cp_max
;
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u32
smi_mon_axi_cos_max
;
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u32
reserved5
[15];
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u32
smi_bus_sel
;
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u32
reserved6
[1];
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u32
smi_wrr_reg0
;
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u32
smi_wrr_reg1
;
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u32
smi_read_fifo_th
;
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u32
smi_m4u_th
;
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u32
smi_fifo_th1
;
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u32
smi_fifo_th2
;
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u32
smi_preultra_mask0
;
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u32
smi_preultra_mask1
;
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u32
reserved7
[46];
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u32
smi_dcm
;
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u32
smi_ela
;
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u32
smi_m1_rultra_wrr0
;
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u32
smi_m1_rultra_wrr1
;
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u32
smi_m1_wultra_wrr0
;
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u32
smi_m1_wultra_wrr1
;
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u32
smi_m2_rultra_wrr0
;
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u32
smi_m2_rultra_wrr1
;
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u32
smi_m2_wultra_wrr0
;
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u32
smi_m2_wultra_wrr1
;
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u32
reserved8
[38];
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u32
smi_common_clamp_en
;
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u32
smi_common_clamp_en_set
;
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u32
smi_common_clamp_en_clr
;
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u32
reserved9
[13];
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u32
smi_debug_s0
;
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u32
smi_debug_s1
;
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u32
smi_debug_s2
;
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u32
smi_debug_s3
;
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u32
smi_debug_s4
;
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u32
smi_debug_s5
;
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u32
smi_debug_s6
;
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u32
smi_debug_s7
;
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u32
reserved10
[4];
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u32
smi_debug_m0
;
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u32
smi_debug_m1
;
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u32
reserved11
[2];
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u32
smi_debug_misc
;
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u32
smi_dummy
;
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u32
reserved12
[46];
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u32
smi_hist_rec0
;
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u32
smi_hist_rec_data0
;
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u32
smi_hist_rec_data1
;
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u32
smi_hist_rec_data2
;
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u32
smi_hist_rec_data3
;
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u32
smi_hist_rec_data4
;
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u32
smi_hist_rec_data5
;
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u32
smi_hist_rec_data6
;
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u32
smi_hist_rec_data7
;
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u32
smi_hist_rec_data8
;
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u32
smi_hist_rec_data9
;
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};
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check_member
(
mt8183_smi_regs
, smi_l1len, 0x0100);
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check_member
(
mt8183_smi_regs
, smi_mon_axi_ena, 0x01a0);
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check_member
(
mt8183_smi_regs
, smi_mon_axi_act_cnt, 0x01c0);
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check_member
(
mt8183_smi_regs
, smi_bus_sel, 0x0220);
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check_member
(
mt8183_smi_regs
, smi_dcm, 0x0300);
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check_member
(
mt8183_smi_regs
, smi_common_clamp_en, 0x03c0);
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check_member
(
mt8183_smi_regs
, smi_debug_s0, 0x0400);
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check_member
(
mt8183_smi_regs
, smi_debug_m0, 0x0430);
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check_member
(
mt8183_smi_regs
, smi_debug_misc, 0x0440);
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check_member
(
mt8183_smi_regs
, smi_hist_rec0, 0x0500);
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check_member
(
mt8183_smi_regs
, smi_hist_rec_data9, 0x0528);
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static
struct
mt8183_smi_regs
*
const
mt8183_smi
= (
void
*)
SMI_BASE
;
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#endif
/* SOC_MEDIATEK_MT8183_SMI_H */
mt8183_smi
static struct mt8183_smi_regs *const mt8183_smi
Definition:
smi.h:103
check_member
check_member(mt8183_smi_regs, smi_l1len, 0x0100)
SMI_BASE
#define SMI_BASE
Definition:
smi.h:16
u32
uint32_t u32
Definition:
stdint.h:51
mt8183_smi_regs
Definition:
smi.h:9
mt8183_smi_regs::smi_l1arb6
u32 smi_l1arb6
Definition:
smi.h:18
mt8183_smi_regs::smi_hist_rec0
u32 smi_hist_rec0
Definition:
smi.h:78
mt8183_smi_regs::smi_mon_axi_act_cnt
u32 smi_mon_axi_act_cnt
Definition:
smi.h:27
mt8183_smi_regs::smi_hist_rec_data5
u32 smi_hist_rec_data5
Definition:
smi.h:84
mt8183_smi_regs::smi_m2_wultra_wrr1
u32 smi_m2_wultra_wrr1
Definition:
smi.h:57
mt8183_smi_regs::smi_wrr_reg0
u32 smi_wrr_reg0
Definition:
smi.h:39
mt8183_smi_regs::reserved4
u32 reserved4[3]
Definition:
smi.h:26
mt8183_smi_regs::smi_mon_axi_clr
u32 smi_mon_axi_clr
Definition:
smi.h:22
mt8183_smi_regs::smi_l1arb1
u32 smi_l1arb1
Definition:
smi.h:13
mt8183_smi_regs::smi_hist_rec_data0
u32 smi_hist_rec_data0
Definition:
smi.h:79
mt8183_smi_regs::smi_common_clamp_en_clr
u32 smi_common_clamp_en_clr
Definition:
smi.h:61
mt8183_smi_regs::smi_debug_m1
u32 smi_debug_m1
Definition:
smi.h:73
mt8183_smi_regs::smi_l1arb3
u32 smi_l1arb3
Definition:
smi.h:15
mt8183_smi_regs::smi_mon_axi_ostd_cnt
u32 smi_mon_axi_ostd_cnt
Definition:
smi.h:29
mt8183_smi_regs::smi_hist_rec_data3
u32 smi_hist_rec_data3
Definition:
smi.h:82
mt8183_smi_regs::smi_mon_axi_cp_cnt
u32 smi_mon_axi_cp_cnt
Definition:
smi.h:32
mt8183_smi_regs::smi_l1len
u32 smi_l1len
Definition:
smi.h:11
mt8183_smi_regs::smi_l1arb2
u32 smi_l1arb2
Definition:
smi.h:14
mt8183_smi_regs::smi_mon_axi_req_cnt
u32 smi_mon_axi_req_cnt
Definition:
smi.h:28
mt8183_smi_regs::smi_hist_rec_data7
u32 smi_hist_rec_data7
Definition:
smi.h:86
mt8183_smi_regs::smi_debug_s2
u32 smi_debug_s2
Definition:
smi.h:65
mt8183_smi_regs::smi_fifo_th2
u32 smi_fifo_th2
Definition:
smi.h:44
mt8183_smi_regs::reserved1
u32 reserved1[64]
Definition:
smi.h:10
mt8183_smi_regs::smi_debug_s5
u32 smi_debug_s5
Definition:
smi.h:68
mt8183_smi_regs::smi_preultra_mask1
u32 smi_preultra_mask1
Definition:
smi.h:46
mt8183_smi_regs::smi_debug_s6
u32 smi_debug_s6
Definition:
smi.h:69
mt8183_smi_regs::smi_hist_rec_data9
u32 smi_hist_rec_data9
Definition:
smi.h:88
mt8183_smi_regs::smi_l1arb4
u32 smi_l1arb4
Definition:
smi.h:16
mt8183_smi_regs::smi_l1arb7
u32 smi_l1arb7
Definition:
smi.h:19
mt8183_smi_regs::smi_debug_misc
u32 smi_debug_misc
Definition:
smi.h:75
mt8183_smi_regs::smi_l1arb5
u32 smi_l1arb5
Definition:
smi.h:17
mt8183_smi_regs::reserved2
u32 reserved2[31]
Definition:
smi.h:20
mt8183_smi_regs::smi_m2_rultra_wrr0
u32 smi_m2_rultra_wrr0
Definition:
smi.h:54
mt8183_smi_regs::smi_wrr_reg1
u32 smi_wrr_reg1
Definition:
smi.h:40
mt8183_smi_regs::smi_hist_rec_data8
u32 smi_hist_rec_data8
Definition:
smi.h:87
mt8183_smi_regs::reserved7
u32 reserved7[46]
Definition:
smi.h:47
mt8183_smi_regs::smi_preultra_mask0
u32 smi_preultra_mask0
Definition:
smi.h:45
mt8183_smi_regs::smi_debug_m0
u32 smi_debug_m0
Definition:
smi.h:72
mt8183_smi_regs::smi_hist_rec_data2
u32 smi_hist_rec_data2
Definition:
smi.h:81
mt8183_smi_regs::reserved9
u32 reserved9[13]
Definition:
smi.h:62
mt8183_smi_regs::smi_mon_axi_bea_cnt
u32 smi_mon_axi_bea_cnt
Definition:
smi.h:30
mt8183_smi_regs::smi_m2_rultra_wrr1
u32 smi_m2_rultra_wrr1
Definition:
smi.h:55
mt8183_smi_regs::reserved10
u32 reserved10[4]
Definition:
smi.h:71
mt8183_smi_regs::smi_mon_axi_type
u32 smi_mon_axi_type
Definition:
smi.h:24
mt8183_smi_regs::smi_dcm
u32 smi_dcm
Definition:
smi.h:48
mt8183_smi_regs::smi_common_clamp_en
u32 smi_common_clamp_en
Definition:
smi.h:59
mt8183_smi_regs::smi_l1arb0
u32 smi_l1arb0
Definition:
smi.h:12
mt8183_smi_regs::smi_hist_rec_data1
u32 smi_hist_rec_data1
Definition:
smi.h:80
mt8183_smi_regs::reserved11
u32 reserved11[2]
Definition:
smi.h:74
mt8183_smi_regs::smi_debug_s0
u32 smi_debug_s0
Definition:
smi.h:63
mt8183_smi_regs::smi_debug_s7
u32 smi_debug_s7
Definition:
smi.h:70
mt8183_smi_regs::smi_hist_rec_data4
u32 smi_hist_rec_data4
Definition:
smi.h:83
mt8183_smi_regs::smi_m2_wultra_wrr0
u32 smi_m2_wultra_wrr0
Definition:
smi.h:56
mt8183_smi_regs::smi_m1_wultra_wrr1
u32 smi_m1_wultra_wrr1
Definition:
smi.h:53
mt8183_smi_regs::smi_m1_rultra_wrr1
u32 smi_m1_rultra_wrr1
Definition:
smi.h:51
mt8183_smi_regs::smi_mon_axi_cp_max
u32 smi_mon_axi_cp_max
Definition:
smi.h:34
mt8183_smi_regs::smi_debug_s4
u32 smi_debug_s4
Definition:
smi.h:67
mt8183_smi_regs::smi_hist_rec_data6
u32 smi_hist_rec_data6
Definition:
smi.h:85
mt8183_smi_regs::reserved8
u32 reserved8[38]
Definition:
smi.h:58
mt8183_smi_regs::smi_mon_axi_ena
u32 smi_mon_axi_ena
Definition:
smi.h:21
mt8183_smi_regs::smi_ela
u32 smi_ela
Definition:
smi.h:49
mt8183_smi_regs::reserved12
u32 reserved12[46]
Definition:
smi.h:77
mt8183_smi_regs::smi_m4u_th
u32 smi_m4u_th
Definition:
smi.h:42
mt8183_smi_regs::smi_common_clamp_en_set
u32 smi_common_clamp_en_set
Definition:
smi.h:60
mt8183_smi_regs::smi_mon_axi_byt_cnt
u32 smi_mon_axi_byt_cnt
Definition:
smi.h:31
mt8183_smi_regs::smi_mon_axi_dp_cnt
u32 smi_mon_axi_dp_cnt
Definition:
smi.h:33
mt8183_smi_regs::smi_m1_wultra_wrr0
u32 smi_m1_wultra_wrr0
Definition:
smi.h:52
mt8183_smi_regs::smi_dummy
u32 smi_dummy
Definition:
smi.h:76
mt8183_smi_regs::reserved5
u32 reserved5[15]
Definition:
smi.h:36
mt8183_smi_regs::reserved3
u32 reserved3[1]
Definition:
smi.h:23
mt8183_smi_regs::smi_m1_rultra_wrr0
u32 smi_m1_rultra_wrr0
Definition:
smi.h:50
mt8183_smi_regs::smi_debug_s3
u32 smi_debug_s3
Definition:
smi.h:66
mt8183_smi_regs::smi_bus_sel
u32 smi_bus_sel
Definition:
smi.h:37
mt8183_smi_regs::smi_read_fifo_th
u32 smi_read_fifo_th
Definition:
smi.h:41
mt8183_smi_regs::smi_fifo_th1
u32 smi_fifo_th1
Definition:
smi.h:43
mt8183_smi_regs::smi_mon_axi_cos_max
u32 smi_mon_axi_cos_max
Definition:
smi.h:35
mt8183_smi_regs::reserved6
u32 reserved6[1]
Definition:
smi.h:38
mt8183_smi_regs::smi_mon_axi_con
u32 smi_mon_axi_con
Definition:
smi.h:25
mt8183_smi_regs::smi_debug_s1
u32 smi_debug_s1
Definition:
smi.h:64
src
soc
mediatek
mt8183
include
soc
smi.h
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