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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | MAX_DRAM_ADDRESS 0xFE000000 |
#define | SDMMC1_BASE 0xFF0C0000 |
#define | SDMMC0_BASE 0xFF0D0000 |
#define | EMMC_BASE 0xFF0F0000 |
#define | SARADC_BASE 0xFF100000 |
#define | SPI0_BASE 0xFF110000 |
#define | SPI1_BASE 0xFF120000 |
#define | SPI2_BASE 0xFF130000 |
#define | I2C1_BASE 0xFF140000 |
#define | I2C3_BASE 0xFF150000 |
#define | I2C4_BASE 0xFF160000 |
#define | I2C5_BASE 0xFF170000 |
#define | UART0_BASE 0xFF180000 |
#define | UART1_BASE 0xFF190000 |
#define | DMAC_PERI_BASE 0xFF250000 |
#define | TSADC_BASE 0xFF280000 |
#define | NANDC0_BASE 0xFF400000 |
#define | NANDC1_BASE 0xFF410000 |
#define | USB_HOST0_EHCI_BASE 0xFF500000 |
#define | USB_HOST0_OHCI_BASE 0xFF520000 |
#define | USB_HOST1_BASE 0xFF540000 |
#define | USB_OTG_BASE 0xFF580000 |
#define | DMAC_BUS_BASE 0xFF600000 |
#define | DDR_PCTL0_BASE 0xFF610000 |
#define | DDR_PCTL1_BASE 0xFF630000 |
#define | DDR_PUBL0_BASE 0xFF620000 |
#define | DDR_PUBL1_BASE 0xFF640000 |
#define | I2C0_BASE 0xFF650000 |
#define | I2C2_BASE 0xFF660000 |
#define | DW_PWM0123_BASE 0xFF670000 |
#define | RK_PWM_BASE 0xFF680000 |
#define | UART2_BASE 0xFF690000 |
#define | TIMER0_BASE 0xFF6B0000 |
#define | SRAM_BASE 0xFF700000 |
#define | PMU_BASE 0xFF730000 |
#define | GRF_SECURE_BASE 0xFF740000 |
#define | GPIO0_BASE 0xFF750000 |
#define | CRU_BASE 0xFF760000 |
#define | GRF_BASE 0xFF770000 |
#define | GPIO1_BASE 0xFF780000 |
#define | GPIO2_BASE 0xFF790000 |
#define | GPIO3_BASE 0xFF7A0000 |
#define | GPIO4_BASE 0xFF7B0000 |
#define | GPIO5_BASE 0xFF7C0000 |
#define | GPIO6_BASE 0xFF7D0000 |
#define | GPIO7_BASE 0xFF7E0000 |
#define | GPIO8_BASE 0xFF7F0000 |
#define | TIMER6_BASE 0xFF810000 |
#define | TIMER7_BASE 0xFF810020 |
#define | CRYPTO_BASE 0xFF8A0000 |
#define | VOP_BIG_BASE 0xFF930000 |
#define | VOP_LIT_BASE 0xFF940000 |
#define | EDP_BASE 0xFF970000 |
#define | HDMI_TX_BASE 0xFF980000 |
#define | SERVICE_CORE_BASE 0xFFA80000 |
#define | SERVICE_DMA_BASE 0xFFA90000 |
#define | SERVICE_GPU_BASE 0xFFAA0000 |
#define | SERVICE_PERI_BASE 0xFFAB0000 |
#define | SERVICE_BUS_BASE 0xFFAC0000 |
#define | SERVICE_VIO_BASE 0xFFAD0000 |
#define | SERVICE_VPU_BASE 0xFFAE0000 |
#define | SERVICE_HEVC_BASE 0xFFAF0000 |
#define | EFUSE_BASE 0xFFB40000 |
#define | CORE_GICD_BASE 0xFFC01000 |
#define | CORE_GICC_BASE 0xFFC02000 |
#define | CPU_AXI_BUS_BASE 0xFFE00000 |
#define | BOOT_ROM_BASE 0xFFFF0000 |
#define | BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0) |
#define | IC_BASES |
#define BOOT_ROM_BASE 0xFFFF0000 |
Definition at line 89 of file addressmap.h.
#define BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0) |
Definition at line 90 of file addressmap.h.
#define CORE_GICC_BASE 0xFFC02000 |
Definition at line 86 of file addressmap.h.
#define CORE_GICD_BASE 0xFFC01000 |
Definition at line 85 of file addressmap.h.
#define CPU_AXI_BUS_BASE 0xFFE00000 |
Definition at line 87 of file addressmap.h.
#define CRU_BASE 0xFF760000 |
Definition at line 52 of file addressmap.h.
#define CRYPTO_BASE 0xFF8A0000 |
Definition at line 66 of file addressmap.h.
#define DDR_PCTL0_BASE 0xFF610000 |
Definition at line 36 of file addressmap.h.
#define DDR_PCTL1_BASE 0xFF630000 |
Definition at line 37 of file addressmap.h.
#define DDR_PUBL0_BASE 0xFF620000 |
Definition at line 38 of file addressmap.h.
#define DDR_PUBL1_BASE 0xFF640000 |
Definition at line 39 of file addressmap.h.
#define DMAC_BUS_BASE 0xFF600000 |
Definition at line 34 of file addressmap.h.
#define DMAC_PERI_BASE 0xFF250000 |
Definition at line 23 of file addressmap.h.
#define DW_PWM0123_BASE 0xFF670000 |
Definition at line 43 of file addressmap.h.
#define EDP_BASE 0xFF970000 |
Definition at line 70 of file addressmap.h.
#define EFUSE_BASE 0xFFB40000 |
Definition at line 83 of file addressmap.h.
#define EMMC_BASE 0xFF0F0000 |
Definition at line 10 of file addressmap.h.
#define GPIO0_BASE 0xFF750000 |
Definition at line 51 of file addressmap.h.
#define GPIO1_BASE 0xFF780000 |
Definition at line 54 of file addressmap.h.
#define GPIO2_BASE 0xFF790000 |
Definition at line 55 of file addressmap.h.
#define GPIO3_BASE 0xFF7A0000 |
Definition at line 56 of file addressmap.h.
#define GPIO4_BASE 0xFF7B0000 |
Definition at line 57 of file addressmap.h.
#define GPIO5_BASE 0xFF7C0000 |
Definition at line 58 of file addressmap.h.
#define GPIO6_BASE 0xFF7D0000 |
Definition at line 59 of file addressmap.h.
#define GPIO7_BASE 0xFF7E0000 |
Definition at line 60 of file addressmap.h.
#define GPIO8_BASE 0xFF7F0000 |
Definition at line 61 of file addressmap.h.
#define GRF_BASE 0xFF770000 |
Definition at line 53 of file addressmap.h.
#define GRF_SECURE_BASE 0xFF740000 |
Definition at line 50 of file addressmap.h.
#define HDMI_TX_BASE 0xFF980000 |
Definition at line 72 of file addressmap.h.
#define I2C0_BASE 0xFF650000 |
Definition at line 41 of file addressmap.h.
#define I2C1_BASE 0xFF140000 |
Definition at line 17 of file addressmap.h.
#define I2C2_BASE 0xFF660000 |
Definition at line 42 of file addressmap.h.
#define I2C3_BASE 0xFF150000 |
Definition at line 18 of file addressmap.h.
#define I2C4_BASE 0xFF160000 |
Definition at line 19 of file addressmap.h.
#define I2C5_BASE 0xFF170000 |
Definition at line 20 of file addressmap.h.
#define IC_BASES |
Definition at line 91 of file addressmap.h.
#define MAX_DRAM_ADDRESS 0xFE000000 |
Definition at line 6 of file addressmap.h.
#define NANDC0_BASE 0xFF400000 |
Definition at line 26 of file addressmap.h.
#define NANDC1_BASE 0xFF410000 |
Definition at line 27 of file addressmap.h.
#define PMU_BASE 0xFF730000 |
Definition at line 49 of file addressmap.h.
#define RK_PWM_BASE 0xFF680000 |
Definition at line 44 of file addressmap.h.
#define SARADC_BASE 0xFF100000 |
Definition at line 11 of file addressmap.h.
#define SDMMC0_BASE 0xFF0D0000 |
Definition at line 9 of file addressmap.h.
#define SDMMC1_BASE 0xFF0C0000 |
Definition at line 8 of file addressmap.h.
#define SERVICE_BUS_BASE 0xFFAC0000 |
Definition at line 78 of file addressmap.h.
#define SERVICE_CORE_BASE 0xFFA80000 |
Definition at line 74 of file addressmap.h.
#define SERVICE_DMA_BASE 0xFFA90000 |
Definition at line 75 of file addressmap.h.
#define SERVICE_GPU_BASE 0xFFAA0000 |
Definition at line 76 of file addressmap.h.
#define SERVICE_HEVC_BASE 0xFFAF0000 |
Definition at line 81 of file addressmap.h.
#define SERVICE_PERI_BASE 0xFFAB0000 |
Definition at line 77 of file addressmap.h.
#define SERVICE_VIO_BASE 0xFFAD0000 |
Definition at line 79 of file addressmap.h.
#define SERVICE_VPU_BASE 0xFFAE0000 |
Definition at line 80 of file addressmap.h.
#define SPI0_BASE 0xFF110000 |
Definition at line 13 of file addressmap.h.
#define SPI1_BASE 0xFF120000 |
Definition at line 14 of file addressmap.h.
#define SPI2_BASE 0xFF130000 |
Definition at line 15 of file addressmap.h.
#define SRAM_BASE 0xFF700000 |
Definition at line 48 of file addressmap.h.
#define TIMER0_BASE 0xFF6B0000 |
Definition at line 46 of file addressmap.h.
#define TIMER6_BASE 0xFF810000 |
Definition at line 63 of file addressmap.h.
#define TIMER7_BASE 0xFF810020 |
Definition at line 64 of file addressmap.h.
#define TSADC_BASE 0xFF280000 |
Definition at line 24 of file addressmap.h.
#define UART0_BASE 0xFF180000 |
Definition at line 21 of file addressmap.h.
#define UART1_BASE 0xFF190000 |
Definition at line 22 of file addressmap.h.
#define UART2_BASE 0xFF690000 |
Definition at line 45 of file addressmap.h.
#define USB_HOST0_EHCI_BASE 0xFF500000 |
Definition at line 29 of file addressmap.h.
#define USB_HOST0_OHCI_BASE 0xFF520000 |
Definition at line 30 of file addressmap.h.
#define USB_HOST1_BASE 0xFF540000 |
Definition at line 31 of file addressmap.h.
#define USB_OTG_BASE 0xFF580000 |
Definition at line 32 of file addressmap.h.
#define VOP_BIG_BASE 0xFF930000 |
Definition at line 68 of file addressmap.h.
#define VOP_LIT_BASE 0xFF940000 |
Definition at line 69 of file addressmap.h.