coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
tpm_ppi.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _TPM_PPI_H_
4 #define _TPM_PPI_H_
5 
6 #include <device/device.h>
7 #include <boot/coreboot_tables.h>
8 
9 #if CONFIG(HAVE_ACPI_TABLES)
10 void tpm_ppi_acpi_fill_ssdt(const struct device *dev);
11 #else
12 static inline void tpm_ppi_acpi_fill_ssdt(const struct device *dev)
13 {
14 }
15 #endif
16 
17 /* Return codes */
18 /* Function 2 */
19 #define PPI2_RET_SUCCESS 0
20 #define PPI2_RET_NOT_SUPPORTED 1
21 #define PPI2_RET_GENERAL_FAILURE 2
22 
23 /* Function 3 */
24 #define PPI3_RET_SUCCESS 0
25 #define PPI3_RET_GENERAL_FAILURE 1
26 
27 /* Function 4 */
28 #define PPI4_RET_NONE 0
29 #define PPI4_RET_SHUTDOWN 1
30 #define PPI4_RET_REBOOT 2
31 #define PPI4_RET_OS_VENDOR_SPECIFIC 3
32 
33 /* Function 5 */
34 #define PPI5_RET_SUCCESS 0
35 #define PPI5_RET_GENERAL_FAILURE 1
36 
37 /* Function 6 */
38 #define PPI6_RET_NOT_IMPLEMENTED 3
39 
40 /* Function 7 */
41 #define PPI7_RET_SUCCESS 0
42 #define PPI7_RET_NOT_IMPLEMENTED 1
43 #define PPI7_RET_GENERAL_FAILURE 2
44 #define PPI7_RET_BLOCKED_BY_FIRMWARE 3
45 
46 /* Function 8 */
47 #define PPI8_RET_NOT_IMPLEMENTED 0
48 #define PPI8_RET_FIRMWARE_ONLY 1
49 #define PPI8_RET_BLOCKED_FOR_OS_BY_FW 2
50 #define PPI8_RET_ALLOWED_WITH_PP 3
51 #define PPI8_RET_ALLOWED 4
52 
53 /* TCG Physical Presence Interface */
54 #define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653"
55 /* TCG Memory Clear Interface */
56 #define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d"
57 
58 /*
59  * Physical Presence Interface Specification Version 1.30 Revision 00.52
60  * Table 1 Physical Presence Interface Operation Summary for TPM 1.2
61  */
62 #define TPM_NOOP 0
63 #define TPM_ENABLE 1
64 #define TPM_DISABLE 2
65 #define TPM_ACTIVATE 3
66 #define TPM_DEACTIVATE 4
67 #define TPM_CLEAR 5
68 #define TPM_ENABLE_ACTIVATE 6
69 #define TPM_DEACTIVATE_DISABLE 7
70 #define TPM_SETOWNERINSTALL_TRUE 8
71 #define TPM_SETOWNERINSTALL_FALSE 9
72 #define TPM_ENABLE_ACTIVATE_SETOWNERINSTALL_TRUE 10
73 #define TPM_SETOWNERINSTALL_FALSE_DEACTIVATE_DISABLE 11
74 #define TPM_CLEAR_ENABLE_ACTIVATE 14
75 #define TPM_SET_NOPPIPROVISION_FALSE 15
76 #define TPM_SET_NOPPIPROVISION_TRUE 16
77 #define TPM_SET_NOPPICLEAR_FALSE 17
78 #define TPM_SET_NOPPICLEAR_TRUE 18
79 #define TPM_SET_NOPPIMAINTAINANCE_FALSE 19
80 #define TPM_SET_NOPPIMAINTAINANCE_TRUE 20
81 #define TPM_ENABLE_ACTIVE_CLEAR 21
82 #define TPM_ENABLE_ACTIVE_CLEAR_ENABLE_ACTIVE 22
83 
84 /*
85  * Physical Presence Interface Specification Version 1.30 Revision 00.52
86  * Table 2 Physical Presence Interface Operation Summary for TPM 2.0
87  */
88 #define TPM2_NOOP 0
89 #define TPM2_ENABLE 1
90 #define TPM2_DISABLE 2
91 #define TPM2_CLEAR 5
92 #define TPM2_CLEAR_ENABLE_ACTIVE 14
93 #define TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE 17
94 #define TPM2_SET_PP_REQUIRED_FOR_CLEAR_FALSE 18
95 #define TPM2_ENABLE_CLEAR 21
96 #define TPM2_ENABLE_CLEAR2 22
97 #define TPM2_SET_PCR_BANKS 23
98 #define TPM2_CHANGE_EPS 24
99 #define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE 25
100 #define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE 26
101 #define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_FALSE 27
102 #define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE 28
103 #define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE 29
104 #define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE 30
105 #define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE 31
106 #define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE 32
107 #define TPM2_LOG_ALL_DIGEST 33
108 #define TPM2_DISABLE_ENDORSMENT_ENABLE_STORAGE_HISTORY 34
109 #define TPM2_ENABLE_BLOCK_SID 96
110 #define TPM2_DISABLE_BLOCK_SID 97
111 #define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE 98
112 #define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FALSE 99
113 #define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE 100
114 #define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FALSE 101
115 
116 #define VENDOR_SPECIFIC_OFFSET 0x80
117 
118  /*
119  * The layout of the buffer matches the QEMU virtual memory device that is generated
120  * by QEMU. See files 'hw/i386/acpi-build.c' and 'include/hw/acpi/tpm.h' for details.
121  */
123  uint8_t func[256]; /* Firmware sets values for each supported operation.
124  * See defined values below. */
125  uint8_t ppin; /* SMI interrupt to use. Set by firmware.
126  * Not supported. */
127  uint32_t ppip; /* ACPI function index to pass to SMM code.
128  * Set by ACPI. Not supported. */
129  uint32_t pprp; /* Result of last executed operation.
130  * Set by firmware. See function index 5 for values. */
131  uint32_t pprq; /* Operation request number to execute.
132  * See 'Physical Presence Interface Operation Summary'
133  * tables in specs. Set by ACPI. */
134  uint32_t pprm; /* Operation request optional parameter.
135  * Values depend on operation. Set by ACPI. */
136  uint32_t lppr; /* Last executed operation request number.
137  * Copied from pprq field by firmware. */
138  uint32_t fret; /* Result code from SMM function. Not supported. */
139  uint8_t res1[0x040]; /* Reserved */
140  uint8_t next_step; /* Operation to execute after reboot by firmware.
141  * Used by firmware. */
143 
144 void lb_tpm_ppi(struct lb_header *header);
145 
146 #endif /* _TPM_PPI_H_ */
struct arm64_kernel_header header
Definition: fit_payload.c:30
unsigned int uint32_t
Definition: stdint.h:14
unsigned char uint8_t
Definition: stdint.h:8
Definition: device.h:107
static void tpm_ppi_acpi_fill_ssdt(const struct device *dev)
Definition: tpm_ppi.h:12
void lb_tpm_ppi(struct lb_header *header)
Definition: ppi.c:707
struct cb_tpm_ppi_payload_handshake __packed