coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
qcom_qup_se.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_QCOM_QUP_SE_H__
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#define __SOC_QCOM_QUP_SE_H__
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#include <
device/mmio.h
>
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#include <
gpio.h
>
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#include <soc/addressmap.h>
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#include <timer.h>
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#include <types.h>
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enum
qup_se
{
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QUPV3_0_SE0
,
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QUPV3_0_SE1
,
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QUPV3_0_SE2
,
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QUPV3_0_SE3
,
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QUPV3_0_SE4
,
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QUPV3_0_SE5
,
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QUPV3_1_SE0
,
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QUPV3_1_SE1
,
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QUPV3_1_SE2
,
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QUPV3_1_SE3
,
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QUPV3_1_SE4
,
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QUPV3_1_SE5
,
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QUPV3_SE_MAX
,
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};
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struct
qup
{
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struct
qup_regs
*
regs
;
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gpio_t
pin
[6];
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u8
func
[6];
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};
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extern
struct
qup
qup
[12];
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#define MAX_OFFSET_CFG_REG 0x000001c0
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#endif
/* __SOC_QCOM_QUP_SE_H__ */
mmio.h
qup_se
qup_se
Definition:
qcom_qup_se.h:12
QUPV3_0_SE2
@ QUPV3_0_SE2
Definition:
qcom_qup_se.h:15
QUPV3_SE_MAX
@ QUPV3_SE_MAX
Definition:
qcom_qup_se.h:25
QUPV3_0_SE3
@ QUPV3_0_SE3
Definition:
qcom_qup_se.h:16
QUPV3_0_SE5
@ QUPV3_0_SE5
Definition:
qcom_qup_se.h:18
QUPV3_1_SE0
@ QUPV3_1_SE0
Definition:
qcom_qup_se.h:19
QUPV3_1_SE4
@ QUPV3_1_SE4
Definition:
qcom_qup_se.h:23
QUPV3_0_SE0
@ QUPV3_0_SE0
Definition:
qcom_qup_se.h:13
QUPV3_1_SE5
@ QUPV3_1_SE5
Definition:
qcom_qup_se.h:24
QUPV3_1_SE2
@ QUPV3_1_SE2
Definition:
qcom_qup_se.h:21
QUPV3_0_SE1
@ QUPV3_0_SE1
Definition:
qcom_qup_se.h:14
QUPV3_1_SE3
@ QUPV3_1_SE3
Definition:
qcom_qup_se.h:22
QUPV3_0_SE4
@ QUPV3_0_SE4
Definition:
qcom_qup_se.h:17
QUPV3_1_SE1
@ QUPV3_1_SE1
Definition:
qcom_qup_se.h:20
gpio.h
u8
uint8_t u8
Definition:
stdint.h:45
gpio_t
Definition:
gpio_base.h:7
qup_regs
Definition:
qup_se_handlers_common.h:203
qup
Definition:
qcom_qup_se.h:28
qup::regs
struct qup_regs * regs
Definition:
qcom_qup_se.h:29
qup::func
u8 func[6]
Definition:
qcom_qup_se.h:31
qup::pin
gpio_t pin[6]
Definition:
qcom_qup_se.h:30
src
soc
qualcomm
sc7180
include
soc
qcom_qup_se.h
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