15 #include <arch/stages.h>
29 asm volatile(
"sync; isync" :::
"memory");
31 asm volatile(
"or 1,1,%0; slbia 7; sync; isync" ::
"r"(hrmor) :
"memory");
__weak void stage_entry(uintptr_t stage_arg)
generic stage entry point.
#define ENV_ROMSTAGE_OR_BEFORE
static void write_spr(int spr, uint64_t val)
static uint64_t read_spr(int spr)
unsigned long long uint64_t