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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */ |
#define | MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */ |
#define | DSI_VIDEO_DST_FORMAT_RGB565 0 |
#define | DSI_VIDEO_DST_FORMAT_RGB666 1 |
#define | DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2 |
#define | DSI_VIDEO_DST_FORMAT_RGB888 3 |
Enumerations | |
enum | { DSI_VIDEO_MODE , DSI_CMD_MODE } |
Functions | |
enum cb_err | mdss_dsi_config (struct edid *edid, uint32_t num_of_lanes, uint32_t bpp) |
void | mdss_dsi_clock_config (void) |
void | mdss_dsi_video_mode_config (struct edid *edid, uint32_t bpp) |
enum cb_err | mdss_dsi_panel_initialize (const u8 *init_cmds) |
#define DSI_VIDEO_DST_FORMAT_RGB565 0 |
Definition at line 12 of file mipi_dsi.h.
#define DSI_VIDEO_DST_FORMAT_RGB666 1 |
Definition at line 13 of file mipi_dsi.h.
#define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2 |
Definition at line 14 of file mipi_dsi.h.
#define DSI_VIDEO_DST_FORMAT_RGB888 3 |
Definition at line 15 of file mipi_dsi.h.
#define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */ |
Definition at line 9 of file mipi_dsi.h.
#define MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */ |
Definition at line 10 of file mipi_dsi.h.
anonymous enum |
Enumerator | |
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DSI_VIDEO_MODE | |
DSI_CMD_MODE |
Definition at line 17 of file mipi_dsi.h.
Definition at line 154 of file dsi.c.
References dsi_regs::clk_ctrl, dsi0, DSI_AHBM_SCLK_ON, DSI_AHBS_HCLK_ON, DSI_BYTECLK_ON, DSI_DSICLK_ON, DSI_ESCCLK_ON, DSI_FORCE_ON_DYN_AHBM_HCLK, DSI_PCLK_ON, setbits32, and write32().
Referenced by mdss_dsi_host_init().
Definition at line 99 of file dsi.c.
References dsi_regs::ctrl, dsi0, DSI_CLKLN_EN, DSI_EN, DSI_EOF_BLLP_PWR, DSI_VIDEO_DST_FORMAT_RGB565, DSI_VIDEO_DST_FORMAT_RGB666, DSI_VIDEO_DST_FORMAT_RGB888, DSI_VIDEO_EN, edid_mode::ha, edid_mode::hbl, dsi_regs::hs_timer_ctrl, HS_TX_TO, edid_mode::hso, edid_mode::hspw, edid::mode, TIMER_RESOLUTION, TRAFFIC_MODE, edid_mode::va, edid_mode::vbl, dsi_regs::video_mode_active_h, dsi_regs::video_mode_active_hsync, dsi_regs::video_mode_active_total, dsi_regs::video_mode_active_v, dsi_regs::video_mode_active_vsync, dsi_regs::video_mode_active_vsync_vpos, dsi_regs::video_mode_ctrl, edid_mode::vso, edid_mode::vspw, and write32().