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◆ LPC_BC_BILD
#define LPC_BC_BILD (1 << 7) /* BILD */ |
◆ LPC_BC_EISS
#define LPC_BC_EISS (1 << 5) /* EISS */ |
◆ LPC_BC_LE
#define LPC_BC_LE (1 << 1) /* LE */ |
◆ LPC_BC_WPD
#define LPC_BC_WPD (1 << 0) /* WPD */ |
◆ LPC_BIOS_CNTL
#define LPC_BIOS_CNTL 0xdc |
◆ LPC_GENERIC_IO_RANGE
#define LPC_GENERIC_IO_RANGE |
( |
|
n | ) |
((((n) & 0x3) * 4) + 0x84) |
◆ LPC_GENERIC_MEM_RANGE
#define LPC_GENERIC_MEM_RANGE 0x98 |
◆ LPC_IO_DECODE
#define LPC_IO_DECODE 0x80 |
◆ LPC_IO_ENABLES
#define LPC_IO_ENABLES 0x82 |
◆ LPC_IOD_COMA_RANGE
#define LPC_IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA */ |
◆ LPC_IOD_COMA_RANGE_MASK
#define LPC_IOD_COMA_RANGE_MASK (7 << 0) |
◆ LPC_IOD_COMB_RANGE
#define LPC_IOD_COMB_RANGE (1 << 4) /* 0x2F8 - 0x2FF COMB */ |
◆ LPC_IOD_COMB_RANGE_MASK
#define LPC_IOD_COMB_RANGE_MASK (7 << 4) |
◆ LPC_LGIR_ADDR_MASK
#define LPC_LGIR_ADDR_MASK 0xfffc |
◆ LPC_LGIR_AMASK_MASK
#define LPC_LGIR_AMASK_MASK (0xfc << 16) |
◆ LPC_LGIR_EN
#define LPC_LGIR_EN (1 << 0) |
◆ LPC_LGIR_MAX_WINDOW_SIZE
#define LPC_LGIR_MAX_WINDOW_SIZE 256 |
◆ LPC_LGMR_ADDR_MASK
#define LPC_LGMR_ADDR_MASK 0xffff0000 |
◆ LPC_LGMR_EN
#define LPC_LGMR_EN (1 << 0) |
◆ LPC_LGMR_WINDOW_SIZE
#define LPC_LGMR_WINDOW_SIZE (64 * KiB) |
◆ LPC_PCCTL
#define LPC_PCCTL 0xE0 /* PCI Clock Control */ |
◆ LPC_PCCTL_CLKRUN_EN
#define LPC_PCCTL_CLKRUN_EN (1 << 0) |
◆ LPC_SCNT_EN
#define LPC_SCNT_EN (1 << 7) |
◆ LPC_SCNT_MODE
#define LPC_SCNT_MODE (1 << 6) |
◆ LPC_SERIRQ_CTL
#define LPC_SERIRQ_CTL 0x64 |