coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <
ec/google/chromeec/ec.h
>
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static
const
struct
soc_amd_gpio
bid_1_gpio_set_stage_ram
[] = {
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/* PEN_DETECT_ODL - no used */
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PAD_NC
(
GPIO_4
),
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/* PEN_POWER_EN - no used */
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PAD_NC
(
GPIO_5
),
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/* TP */
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PAD_NC
(
GPIO_32
),
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/* EN_DEV_BEEP_L */
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PAD_GPO
(
GPIO_89
, HIGH),
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/* USI_RESET */
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PAD_GPO
(
GPIO_140
, HIGH),
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};
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static
const
struct
soc_amd_gpio
dirinboz_gpio_set_stage_ram
[] = {
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/* PEN_DETECT_ODL - no used */
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PAD_NC
(
GPIO_4
),
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/* PEN_POWER_EN - no used */
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PAD_NC
(
GPIO_5
),
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};
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const
struct
soc_amd_gpio
*
variant_override_gpio_table
(
size_t
*size)
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{
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uint32_t
board_version;
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/*
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* If board version cannot be read, assume that this is an older revision of the board
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* and so apply overrides. If board version is provided by the EC, then apply overrides
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* if version < 2.
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*/
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if
(
google_chromeec_cbi_get_board_version
(&board_version) != 0)
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board_version = 1;
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if
(board_version < 2) {
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*size =
ARRAY_SIZE
(
bid_1_gpio_set_stage_ram
);
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return
bid_1_gpio_set_stage_ram
;
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}
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*size =
ARRAY_SIZE
(
dirinboz_gpio_set_stage_ram
);
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return
dirinboz_gpio_set_stage_ram
;
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}
GPIO_32
#define GPIO_32
Definition:
gpio_ftns.h:15
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
google_chromeec_cbi_get_board_version
int google_chromeec_cbi_get_board_version(uint32_t *version)
Definition:
ec.c:870
ec.h
variant_override_gpio_table
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition:
gpio.c:450
bid_1_gpio_set_stage_ram
static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[]
Definition:
gpio.c:9
dirinboz_gpio_set_stage_ram
static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[]
Definition:
gpio.c:22
GPIO_89
#define GPIO_89
Definition:
gpio.h:65
GPIO_5
#define GPIO_5
Definition:
gpio.h:26
GPIO_4
#define GPIO_4
Definition:
gpio.h:25
GPIO_140
#define GPIO_140
Definition:
gpio.h:87
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_GPO
#define PAD_GPO(pin, direction)
Definition:
gpio_defs.h:220
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
soc_amd_gpio
Definition:
gpio.h:11
src
mainboard
google
zork
variants
dirinboz
gpio.c
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