coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <gpio.h>
6 #include <soc/gpio.h>
8 
9 static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
10  /* PEN_DETECT_ODL - no used */
11  PAD_NC(GPIO_4),
12  /* PEN_POWER_EN - no used */
13  PAD_NC(GPIO_5),
14  /* TP */
15  PAD_NC(GPIO_32),
16  /* EN_DEV_BEEP_L */
17  PAD_GPO(GPIO_89, HIGH),
18  /* USI_RESET */
19  PAD_GPO(GPIO_140, HIGH),
20 };
21 
22 static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = {
23  /* PEN_DETECT_ODL - no used */
24  PAD_NC(GPIO_4),
25  /* PEN_POWER_EN - no used */
26  PAD_NC(GPIO_5),
27 };
28 
29 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
30 {
31  uint32_t board_version;
32 
33  /*
34  * If board version cannot be read, assume that this is an older revision of the board
35  * and so apply overrides. If board version is provided by the EC, then apply overrides
36  * if version < 2.
37  */
38  if (google_chromeec_cbi_get_board_version(&board_version) != 0)
39  board_version = 1;
40 
41  if (board_version < 2) {
44  }
45 
48 }
#define GPIO_32
Definition: gpio_ftns.h:15
#define ARRAY_SIZE(a)
Definition: helpers.h:12
int google_chromeec_cbi_get_board_version(uint32_t *version)
Definition: ec.c:870
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition: gpio.c:450
static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[]
Definition: gpio.c:9
static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[]
Definition: gpio.c:22
#define GPIO_89
Definition: gpio.h:65
#define GPIO_5
Definition: gpio.h:26
#define GPIO_4
Definition: gpio.h:25
#define GPIO_140
Definition: gpio.h:87
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define PAD_GPO(pin, direction)
Definition: gpio_defs.h:220
unsigned int uint32_t
Definition: stdint.h:14