coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <option.h>
4 #include <soc/cnl_memcfg_init.h>
5 #include <soc/gpio.h>
6 #include <soc/romstage.h>
7 #include <variant.h>
8 #include <variant/gpio.h>
9 
10 void mainboard_memory_init_params(FSPM_UPD *memupd)
11 {
12  const struct cnl_mb_cfg cfg = {
13  .spd = {
14  [0] = { READ_SMBUS, { 0x50 << 1 } },
15  [2] = { READ_SMBUS, { 0x52 << 1 } },
16  },
17  .rcomp_resistor = { 121, 75, 100 },
18  .rcomp_targets = { 50, 25, 20, 20, 26 },
19  .dq_pins_interleaved = 1,
20  .vref_ca_config = 2,
21  .ect = 0,
22  };
23  cannonlake_memcfg_init(&memupd->FspmConfig, &cfg);
24  memupd->FspmConfig.EccSupport = 1;
25  memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE;
26 
27  const uint8_t vtd = get_uint_option("vtd", 1);
28  memupd->FspmTestConfig.VtdDisable = !vtd;
29  const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading);
30  memupd->FspmConfig.HyperThreading = ht;
31 
33 
35 }
36 
37 __weak void variant_romstage_params(FSPM_UPD *const mupd)
38 {
39 }
void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, const struct cnl_mb_cfg *cnl_cfg)
@ READ_SMBUS
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition: romstage.c:22
void variant_configure_gpios(void)
Definition: gpio.c:238
__weak void variant_romstage_params(FSPM_UPD *const mupd)
Definition: romstage.c:37
unsigned int get_uint_option(const char *name, const unsigned int fallback)
Definition: option.c:116
const struct smm_save_state_ops *legacy_ops __weak
Definition: save_state.c:8
@ BOARD_TYPE_MOBILE
Definition: romstage.h:14
unsigned char uint8_t
Definition: stdint.h:8
struct spd_info spd[NUM_DIMM_SLOT]