coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
imc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
device/pci.h
>
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#include <
stdint.h
>
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#ifndef SOC_INTEL_COMMON_BLOCK_IMC_H
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#define SOC_INTEL_COMMON_BLOCK_IMC_H
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enum
smbus_command
{
IMC_READ
,
IMC_WRITE
};
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enum
access_width
{
IMC_DATA_BYTE
,
IMC_DATA_WORD
};
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enum
memory_controller_id
{
IMC_CONTROLLER_ID0
= 0,
IMC_CONTROLLER_ID1
};
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enum
device_type_id
{
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IMC_DEVICE_TSOD
= 0x3,
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IMC_DEVICE_WP_EEPROM
= 0x6,
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IMC_DEVICE_EEPROM
= 0xa
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};
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/* Initiate SMBus/I2C transaction to DIMM EEPROM */
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int
imc_smbus_spd_xfer
(
pci_devfn_t
dev,
uint8_t
slave_addr,
uint8_t
bus_addr,
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enum
device_type_id
dti,
enum
access_width
width
,
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enum
memory_controller_id
mcid,
enum
smbus_command
cmd,
void
*data);
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#endif
width
static int width
Definition:
bochs.c:42
pci.h
pci_devfn_t
u32 pci_devfn_t
Definition:
pci_type.h:8
smbus_command
smbus_command
Definition:
imc.h:9
IMC_READ
@ IMC_READ
Definition:
imc.h:9
IMC_WRITE
@ IMC_WRITE
Definition:
imc.h:9
access_width
access_width
Definition:
imc.h:11
IMC_DATA_WORD
@ IMC_DATA_WORD
Definition:
imc.h:11
IMC_DATA_BYTE
@ IMC_DATA_BYTE
Definition:
imc.h:11
memory_controller_id
memory_controller_id
Definition:
imc.h:13
IMC_CONTROLLER_ID1
@ IMC_CONTROLLER_ID1
Definition:
imc.h:13
IMC_CONTROLLER_ID0
@ IMC_CONTROLLER_ID0
Definition:
imc.h:13
device_type_id
device_type_id
Definition:
imc.h:15
IMC_DEVICE_EEPROM
@ IMC_DEVICE_EEPROM
Definition:
imc.h:18
IMC_DEVICE_WP_EEPROM
@ IMC_DEVICE_WP_EEPROM
Definition:
imc.h:17
IMC_DEVICE_TSOD
@ IMC_DEVICE_TSOD
Definition:
imc.h:16
imc_smbus_spd_xfer
int imc_smbus_spd_xfer(pci_devfn_t dev, uint8_t slave_addr, uint8_t bus_addr, enum device_type_id dti, enum access_width width, enum memory_controller_id mcid, enum smbus_command cmd, void *data)
stdint.h
uint8_t
unsigned char uint8_t
Definition:
stdint.h:8
src
soc
intel
common
block
include
intelblocks
imc.h
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