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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
#define CACHE_INCLUSIVE_MASK (0x1 << CACHE_INCLUSIVE_SHFT) |
#define CPUID_EBX_THREADS_MASK (0xff << CPUID_EBX_THREADS_SHIFT) |
#define L1_DAT_TLB_1G_ASSOC_MASK (0xf << L1_DAT_TLB_1G_ASSOC_SHFT) |
#define L1_DAT_TLB_1G_SIZE_MASK (0xfff << L1_DAT_TLB_1G_SIZE_SHFT) |
#define L1_DAT_TLB_2M4M_ASSOC_MASK (0xff << L1_DAT_TLB_2M4M_ASSOC_SHFT) |
#define L1_DAT_TLB_2M4M_SIZE_MASK (0xff << L1_DAT_TLB_2M4M_SIZE_SHFT) |
#define L1_DAT_TLB_4K_ASSOC_MASK (0xff << L1_DAT_TLB_4K_ASSOC_SHFT) |
#define L1_DAT_TLB_4K_SIZE_MASK (0xff << L1_DAT_TLB_4K_SIZE_SHFT) |
#define L1_DC_ASSOC_MASK (0xff << L1_DC_ASSOC_SHFT) |
#define L1_DC_LINE_SIZE_MASK (0xff << L1_DC_LINE_SIZE_SHFT) |
#define L1_DC_LINE_TAG_MASK (0xff << L1_DC_LINE_TAG_SHFT) |
#define L1_DC_SIZE_MASK (0xff << L1_DC_SIZE_SHFT) |
#define L1_IC_ASSOC_MASK (0xff << L1_IC_ASSOC_SHFT) |
#define L1_IC_LINE_SIZE_MASK (0xff << L1_IC_LINE_SIZE_SHFT) |
#define L1_IC_LINE_TAG_MASK (0xff << L1_IC_LINE_TAG_SHFT) |
#define L1_IC_SIZE_MASK (0xff << L1_IC_SIZE_SHFT) |
#define L1_INST_TLB_1G_ASSOC_MASK (0xf << L1_INST_TLB_1G_ASSOC_SHFT) |
#define L1_INST_TLB_1G_SIZE_MASK (0xfff << L1_INST_TLB_1G_SIZE_SHFT) |
#define L1_INST_TLB_2M4M_ASSOC_MASK (0xff << L1_INST_TLB_2M4M_ASSOC_SHFT) |
#define L1_INST_TLB_2M4M_SIZE_MASK (0xff << L1_INST_TLB_2M4M_SIZE_SHFT) |
#define L1_INST_TLB_4K_ASSOC_MASK (0xff << L1_INST_TLB_4K_ASSOC_SHFT) |
#define L1_INST_TLB_4K_SIZE_MASK (0xff << L1_INST_TLB_4K_SIZE_SHFT) |
#define L2_DAT_TLB_1G_ASSOC_MASK (0xf << L2_DAT_TLB_1G_ASSOC_SHFT) |
#define L2_DAT_TLB_1G_SIZE_MASK (0xfff << L2_DAT_TLB_1G_SIZE_SHFT) |
#define L2_DAT_TLB_2M4M_ASSOC_MASK (0xf << L2_DAT_TLB_2M4M_ASSOC_SHFT) |
#define L2_DAT_TLB_2M4M_SIZE_MASK (0xfff << L2_DAT_TLB_2M4M_SIZE_SHFT) |
#define L2_DAT_TLB_4K_ASSOC_MASK (0xf << L2_DAT_TLB_4K_ASSOC_SHFT) |
#define L2_DAT_TLB_4K_SIZE_MASK (0xfff << L2_DAT_TLB_4K_SIZE_SHFT) |
#define L2_DC_ASSOC_MASK (0xf << L2_DC_ASSOC_SHFT) |
#define L2_DC_LINE_SIZE_MASK (0xff << L2_DC_LINE_SIZE_SHFT) |
#define L2_DC_LINE_TAG_MASK (0xf << L2_DC_LINE_TAG_SHFT) |
#define L2_DC_SIZE_MASK (0xffff << L2_DC_SIZE_SHFT) |
#define L2_INST_TLB_1G_ASSOC_MASK (0xf << L2_INST_TLB_1G_ASSOC_SHFT) |
#define L2_INST_TLB_1G_SIZE_MASK (0xfff << L2_INST_TLB_1G_SIZE_SHFT) |
#define L2_INST_TLB_2M4M_ASSOC_MASK (0xf << L2_INST_TLB_2M4M_ASSOC_SHFT) |
#define L2_INST_TLB_2M4M_SIZE_MASK (0xfff << L2_INST_TLB_2M4M_SIZE_SHFT) |
#define L2_INST_TLB_4K_ASSOC_MASK (0xf << L2_INST_TLB_4K_ASSOC_SHFT) |
#define L2_INST_TLB_4K_SIZE_MASK (0xfff << L2_INST_TLB_4K_SIZE_SHFT) |
#define L3_DC_ASSOC_MASK (0xf << L3_DC_ASSOC_SHFT) |
#define L3_DC_LINE_SIZE_MASK (0xff << L3_DC_LINE_SIZE_SHFT) |
#define L3_DC_LINE_TAG_MASK (0xf << L3_DC_LINE_TAG_SHFT) |
#define L3_DC_SIZE_MASK (0x3fff << L3_DC_SIZE_SHFT) |
#define NUM_SHARE_CACHE_MASK (0xfff << NUM_SHARE_CACHE_SHFT) |