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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <stdint.h>
Go to the source code of this file.
Macros | |
| #define | AOSS_CC_BASE 0x0C2A0000 |
| #define | DISP_CC_BASE 0x0AF00000 |
| #define | GCC_BASE 0x00100000 |
| #define | L3_PLL_BASE 0x18284000 |
| #define | QSPI_BASE 0x088DC000 |
| #define | SHRM_SPROC_BASE 0x09051000 |
| #define | SILVER_PLL_BASE 0x18280000 |
| #define | TLMM_TILE_BASE 0x0F100000 |
| #define | QSPI_CS GPIO(15) |
| #define | QSPI_DATA_0 GPIO(12) |
| #define | QSPI_DATA_1 GPIO(13) |
| #define | QSPI_CLK GPIO(14) |
| #define | GPIO_FUNC_QSPI_DATA_0 GPIO12_FUNC_QSPI_DATA_0 |
| #define | GPIO_FUNC_QSPI_DATA_1 GPIO13_FUNC_QSPI_DATA_1 |
| #define | GPIO_FUNC_QSPI_CLK GPIO14_FUNC_QSPI_CLK |
| #define | SDC1_TLMM_CFG_ADDR 0x0F1B3000 |
| #define | SDC2_TLMM_CFG_ADDR 0x0F1B4000 |
| #define | QUP_SERIAL0_BASE 0x00980000 |
| #define | QUP_SERIAL1_BASE 0x00984000 |
| #define | QUP_SERIAL2_BASE 0x00988000 |
| #define | QUP_SERIAL3_BASE 0x0098C000 |
| #define | QUP_SERIAL4_BASE 0x00990000 |
| #define | QUP_SERIAL5_BASE 0x00994000 |
| #define | QUP_SERIAL6_BASE 0x00998000 |
| #define | QUP_SERIAL7_BASE 0x0099C000 |
| #define | QUP_WRAP0_BASE 0x009C0000 |
| #define | QUP_0_GSI_BASE 0x00904000 |
| #define | QUP_SERIAL8_BASE 0x00A80000 |
| #define | QUP_SERIAL9_BASE 0x00A84000 |
| #define | QUP_SERIAL10_BASE 0x00A88000 |
| #define | QUP_SERIAL11_BASE 0x00A8C000 |
| #define | QUP_SERIAL12_BASE 0x00A90000 |
| #define | QUP_SERIAL13_BASE 0x00A94000 |
| #define | QUP_SERIAL14_BASE 0x00A98000 |
| #define | QUP_SERIAL15_BASE 0x00A9C000 |
| #define | QUP_WRAP1_BASE 0x00AC0000 |
| #define | QUP_1_GSI_BASE 0x00A04000 |
| #define | EPSSTOP_EPSS_TOP 0x18598000 |
| #define | EPSSFAST_BASE_ADDR 0x18580000 |
| #define | HS_USB_PRIM_PHY_BASE 0x088e3000 |
| #define | QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 |
| #define | QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 |
| #define | QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 |
| #define | QMP_PHY_PCS_REG_BASE 0x088e9c00 |
| #define | USB_HOST_DWC3_BASE 0x0a60c100 |
| #define AOSS_CC_BASE 0x0C2A0000 |
Definition at line 8 of file addressmap.h.
| #define DISP_CC_BASE 0x0AF00000 |
Definition at line 9 of file addressmap.h.
| #define EPSSFAST_BASE_ADDR 0x18580000 |
Definition at line 59 of file addressmap.h.
| #define EPSSTOP_EPSS_TOP 0x18598000 |
Definition at line 58 of file addressmap.h.
| #define GCC_BASE 0x00100000 |
Definition at line 10 of file addressmap.h.
| #define GPIO_FUNC_QSPI_CLK GPIO14_FUNC_QSPI_CLK |
Definition at line 25 of file addressmap.h.
| #define GPIO_FUNC_QSPI_DATA_0 GPIO12_FUNC_QSPI_DATA_0 |
Definition at line 23 of file addressmap.h.
| #define GPIO_FUNC_QSPI_DATA_1 GPIO13_FUNC_QSPI_DATA_1 |
Definition at line 24 of file addressmap.h.
| #define HS_USB_PRIM_PHY_BASE 0x088e3000 |
Definition at line 64 of file addressmap.h.
| #define L3_PLL_BASE 0x18284000 |
Definition at line 11 of file addressmap.h.
| #define QMP_PHY_PCS_REG_BASE 0x088e9c00 |
Definition at line 68 of file addressmap.h.
| #define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 |
Definition at line 65 of file addressmap.h.
| #define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 |
Definition at line 67 of file addressmap.h.
| #define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 |
Definition at line 66 of file addressmap.h.
| #define QSPI_BASE 0x088DC000 |
Definition at line 12 of file addressmap.h.
| #define QSPI_CLK GPIO(14) |
Definition at line 21 of file addressmap.h.
| #define QSPI_CS GPIO(15) |
Definition at line 18 of file addressmap.h.
| #define QSPI_DATA_0 GPIO(12) |
Definition at line 19 of file addressmap.h.
| #define QSPI_DATA_1 GPIO(13) |
Definition at line 20 of file addressmap.h.
| #define QUP_0_GSI_BASE 0x00904000 |
Definition at line 44 of file addressmap.h.
| #define QUP_1_GSI_BASE 0x00A04000 |
Definition at line 56 of file addressmap.h.
| #define QUP_SERIAL0_BASE 0x00980000 |
Definition at line 35 of file addressmap.h.
| #define QUP_SERIAL10_BASE 0x00A88000 |
Definition at line 49 of file addressmap.h.
| #define QUP_SERIAL11_BASE 0x00A8C000 |
Definition at line 50 of file addressmap.h.
| #define QUP_SERIAL12_BASE 0x00A90000 |
Definition at line 51 of file addressmap.h.
| #define QUP_SERIAL13_BASE 0x00A94000 |
Definition at line 52 of file addressmap.h.
| #define QUP_SERIAL14_BASE 0x00A98000 |
Definition at line 53 of file addressmap.h.
| #define QUP_SERIAL15_BASE 0x00A9C000 |
Definition at line 54 of file addressmap.h.
| #define QUP_SERIAL1_BASE 0x00984000 |
Definition at line 36 of file addressmap.h.
| #define QUP_SERIAL2_BASE 0x00988000 |
Definition at line 37 of file addressmap.h.
| #define QUP_SERIAL3_BASE 0x0098C000 |
Definition at line 38 of file addressmap.h.
| #define QUP_SERIAL4_BASE 0x00990000 |
Definition at line 39 of file addressmap.h.
| #define QUP_SERIAL5_BASE 0x00994000 |
Definition at line 40 of file addressmap.h.
| #define QUP_SERIAL6_BASE 0x00998000 |
Definition at line 41 of file addressmap.h.
| #define QUP_SERIAL7_BASE 0x0099C000 |
Definition at line 42 of file addressmap.h.
| #define QUP_SERIAL8_BASE 0x00A80000 |
Definition at line 47 of file addressmap.h.
| #define QUP_SERIAL9_BASE 0x00A84000 |
Definition at line 48 of file addressmap.h.
| #define QUP_WRAP0_BASE 0x009C0000 |
Definition at line 43 of file addressmap.h.
| #define QUP_WRAP1_BASE 0x00AC0000 |
Definition at line 55 of file addressmap.h.
| #define SDC1_TLMM_CFG_ADDR 0x0F1B3000 |
Definition at line 28 of file addressmap.h.
| #define SDC2_TLMM_CFG_ADDR 0x0F1B4000 |
Definition at line 29 of file addressmap.h.
| #define SHRM_SPROC_BASE 0x09051000 |
Definition at line 13 of file addressmap.h.
| #define SILVER_PLL_BASE 0x18280000 |
Definition at line 14 of file addressmap.h.
| #define TLMM_TILE_BASE 0x0F100000 |
Definition at line 15 of file addressmap.h.
| #define USB_HOST_DWC3_BASE 0x0a60c100 |
Definition at line 69 of file addressmap.h.
1.9.1