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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
struct | tegra_dc_dp_link_config |
struct | tegra_dc_sor_data |
Enumerations | |
enum | { training_pattern_disabled = 0 , training_pattern_1 = 1 , training_pattern_2 = 2 , training_pattern_3 = 3 , training_pattern_none = 0xff } |
enum | tegra_dc_sor_protocol { SOR_DP , SOR_LVDS , SOR_DP , SOR_LVDS } |
#define CHECK_RET | ( | x | ) |
#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16) |
#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24) |
#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24) |
#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28) |
#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4) |
#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4) |
#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5) |
#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5) |
#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6) |
#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6) |
#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7) |
#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7) |
#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (0x3 << 4) |
#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4) |
#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4) |
#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (0x3 << 12) |
#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12) |
#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12) |
#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (0x3 << 20) |
#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20) |
#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20) |
#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28) |
#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28) |
#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24) |
#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24) |
anonymous enum |
void tegra_dc_detach | ( | struct tegra_dc_sor_data * | sor | ) |
Definition at line 1039 of file sor.c.
References tegra_dc::base, BIOS_ERR, display_controller::cmd, tegra_dc_sor_data::dc, DC_N_WINDOWS, dc_cmd_reg::disp_cmd, DISP_CTRL_MODE_STOP, dc_cmd_reg::int_mask, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP, NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE, NV_SOR_SUPER_STATE1_ATTACHED_NO, NV_SOR_SUPER_STATE1_ATTACHED_YES, NV_SOR_TEST, NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP, printk, READL(), tegra_dc_sor_disable_win_short_raster(), tegra_dc_sor_enable_sor(), tegra_dc_sor_general_act(), tegra_dc_sor_poll_register(), tegra_dc_sor_restore_win_and_raster(), tegra_dc_sor_super_update(), TEGRA_SOR_ATTACH_TIMEOUT_MS, tegra_sor_writel(), and WRITEL().
Referenced by tegra_dc_dp_check_sink().
void tegra_dc_sor_attach | ( | struct tegra_dc_sor_data * | sor | ) |
Definition at line 728 of file sor.c.
References tegra_dc::base, BIOS_ERR, BIOS_INFO, display_controller::cmd, tegra_dc_sor_data::dc, display_controller::disp, dc_cmd_reg::disp_cmd, DISP_CTRL_MODE_C_DISPLAY, dc_cmd_reg::disp_pow_ctrl, dc_disp_reg::disp_win_opt, FRAME_IN_MS, GENERAL_ACT_REQ, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE, NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL, NV_SOR_SUPER_STATE1_ATTACHED_NO, NV_SOR_SUPER_STATE1_ATTACHED_YES, NV_SOR_TEST, NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE, NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, NV_SOR_TEST_ATTACHED_TRUE, PM0_ENABLE, PM1_ENABLE, printk, PW0_ENABLE, PW1_ENABLE, PW2_ENABLE, PW3_ENABLE, PW4_ENABLE, READ_MUX_ACTIVE, SOR_ENABLE, dc_cmd_reg::state_access, dc_cmd_reg::state_ctrl, tegra_dc_sor_config_panel(), tegra_dc_sor_enable_dc(), tegra_dc_sor_poll_register(), tegra_dc_sor_super_update(), tegra_dc_sor_update(), TEGRA_SOR_ATTACH_TIMEOUT_MS, tegra_sor_readl(), tegra_sor_writel(), udelay(), WRITE_MUX_ACTIVE, and WRITEL().
void tegra_dc_sor_enable_dp | ( | struct tegra_dc_sor_data * | sor | ) |
Definition at line 672 of file sor.c.
References BIOS_ERR, tegra_dc_dp_link_config::lane_count, tegra_dc_sor_data::link_cfg, NV_SOR_CLK_CNTRL, NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK, NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK, NV_SOR_PLL0, NV_SOR_PLL0_ICHPMP_SHFIT, NV_SOR_PLL0_PLLREG_LEVEL_V45, NV_SOR_PLL0_PWR_ON, NV_SOR_PLL0_RESISTORSEL_EXT, NV_SOR_PLL0_VCOCAP_SHIFT, NV_SOR_PLL0_VCOPD_RESCIND, NV_SOR_PLL1, NV_SOR_PLL1_TERM_COMPOUT_HIGH, NV_SOR_PLL1_TMDS_TERM_ENABLE, NV_SOR_PLL2, NV_SOR_PLL2_AUX1_SEQ_MASK, NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE, NV_SOR_PLL2_AUX2_MASK, NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN, NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE, NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK, NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE, NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE, NV_SOR_PLL3, NV_SOR_PLL3_PLLVDD_MODE_MASK, NV_SOR_PLL3_PLLVDD_MODE_V3_3, printk, tegra_dc_sor_poll_register(), tegra_dc_sor_power_dplanes(), tegra_dc_sor_power_up(), tegra_dc_sor_set_dp_mode(), tegra_sor_enable_edp_clock(), TEGRA_SOR_TIMEOUT_MS, tegra_sor_write_field(), tegra_sor_writel(), and udelay().
void tegra_dc_sor_power_down_unused_lanes | ( | struct tegra_dc_sor_data * | sor | ) |
Definition at line 844 of file sor.c.
References BIOS_ERR, tegra_dc_dp_link_config::lane_count, tegra_dc_sor_data::link_cfg, NV_SOR_DP_PADCTL, NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, NV_SOR_DP_PADCTL_PD_TXD_0_NO, NV_SOR_DP_PADCTL_PD_TXD_1_NO, NV_SOR_DP_PADCTL_PD_TXD_1_YES, NV_SOR_DP_PADCTL_PD_TXD_2_NO, NV_SOR_DP_PADCTL_PD_TXD_2_YES, NV_SOR_DP_PADCTL_PD_TXD_3_NO, NV_SOR_DP_PADCTL_PD_TXD_3_YES, tegra_dc_sor_data::portnum, printk, tegra_dc_sor_enable_lane_sequencer(), and tegra_sor_writel().
void tegra_dc_sor_read_link_config | ( | struct tegra_dc_sor_data * | sor, |
u8 * | link_bw, | ||
u8 * | lane_count | ||
) |
Definition at line 382 of file sor.c.
References BIOS_ERR, NV_SOR_CLK_CNTRL, NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK, NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT, NV_SOR_DP_LINKCTL, NV_SOR_DP_LINKCTL_LANECOUNT_FOUR, NV_SOR_DP_LINKCTL_LANECOUNT_MASK, NV_SOR_DP_LINKCTL_LANECOUNT_ONE, NV_SOR_DP_LINKCTL_LANECOUNT_TWO, NV_SOR_DP_LINKCTL_LANECOUNT_ZERO, tegra_dc_sor_data::portnum, printk, and tegra_sor_readl().
void tegra_dc_sor_set_dp_linkctl | ( | struct tegra_dc_sor_data * | sor, |
int | ena, | ||
u8 | training_pattern, | ||
const struct tegra_dc_dp_link_config * | link_cfg | ||
) |
Definition at line 141 of file sor.c.
References tegra_dc_dp_link_config::enhanced_framing, tegra_dc_dp_link_config::link_bw, NV_SOR_DP_LINKCTL, NV_SOR_DP_LINKCTL_ENABLE_NO, NV_SOR_DP_LINKCTL_ENABLE_YES, NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE, NV_SOR_DP_LINKCTL_TUSIZE_MASK, NV_SOR_DP_LINKCTL_TUSIZE_SHIFT, NV_SOR_DP_TPG, tegra_dc_sor_data::portnum, SOR_LINK_SPEED_G5_4, tegra_sor_readl(), tegra_sor_writel(), training_pattern_1, training_pattern_2, training_pattern_3, and tegra_dc_dp_link_config::tu_size.
Referenced by tegra_dc_sor_set_dp_mode().
void tegra_dc_sor_set_internal_panel | ( | struct tegra_dc_sor_data * | sor, |
int | is_int | ||
) |
Definition at line 367 of file sor.c.
References NV_SOR_DP_SPARE, NV_SOR_DP_SPARE_PANEL_INTERNAL, NV_SOR_DP_SPARE_SEQ_ENABLE_YES, NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK, tegra_dc_sor_data::portnum, tegra_sor_readl(), and tegra_sor_writel().
void tegra_dc_sor_set_lane_count | ( | struct tegra_dc_sor_data * | sor, |
u8 | lane_count | ||
) |
Definition at line 418 of file sor.c.
References BIOS_ERR, NV_SOR_DP_LINKCTL, NV_SOR_DP_LINKCTL_LANECOUNT_FOUR, NV_SOR_DP_LINKCTL_LANECOUNT_MASK, NV_SOR_DP_LINKCTL_LANECOUNT_ONE, NV_SOR_DP_LINKCTL_LANECOUNT_TWO, tegra_dc_sor_data::portnum, printk, tegra_sor_readl(), and tegra_sor_writel().
Referenced by tegra_dc_sor_power_dplanes(), and tegra_dc_sor_set_lane_parm().
void tegra_dc_sor_set_lane_parm | ( | struct tegra_dc_sor_data * | sor, |
const struct tegra_dc_dp_link_config * | link_cfg | ||
) |
Definition at line 789 of file sor.c.
References tegra_dc_dp_link_config::drive_current, tegra_dc_dp_link_config::lane_count, tegra_dc_dp_link_config::link_bw, NV_SOR_DP_PADCTL, NV_SOR_DP_PADCTL_TX_PU_ENABLE, NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT, NV_SOR_LANE_DRIVE_CURRENT, NV_SOR_LVDS, NV_SOR_POSTCURSOR, NV_SOR_PR, tegra_dc_sor_data::portnum, tegra_dc_dp_link_config::postcursor, tegra_dc_dp_link_config::preemphasis, tegra_dc_sor_set_lane_count(), tegra_dc_sor_set_link_bandwidth(), tegra_sor_write_field(), tegra_sor_writel(), and udelay().
void tegra_dc_sor_set_link_bandwidth | ( | struct tegra_dc_sor_data * | sor, |
u8 | link_bw | ||
) |
Definition at line 411 of file sor.c.
References NV_SOR_CLK_CNTRL, NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK, NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT, and tegra_sor_write_field().
Referenced by tegra_dc_sor_power_up(), tegra_dc_sor_set_dp_mode(), and tegra_dc_sor_set_lane_parm().
void tegra_dc_sor_set_panel_power | ( | struct tegra_dc_sor_data * | sor, |
int | power_up | ||
) |
Definition at line 242 of file sor.c.
References NV_SOR_DP_PADCTL, NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, tegra_dc_sor_data::portnum, tegra_sor_readl(), and tegra_sor_writel().
int tegra_dc_sor_set_power_state | ( | struct tegra_dc_sor_data * | sor, |
int | pu_pd | ||
) |
Definition at line 113 of file sor.c.
References BIOS_ERR, EFAULT, NV_SOR_PWR, NV_SOR_PWR_NORMAL_STATE_PD, NV_SOR_PWR_NORMAL_STATE_PU, NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK, NV_SOR_PWR_SETTING_NEW_DONE, NV_SOR_PWR_SETTING_NEW_TRIGGER, printk, tegra_dc_sor_poll_register(), tegra_sor_readl(), TEGRA_SOR_TIMEOUT_MS, and tegra_sor_writel().
void tegra_dc_sor_set_voltage_swing | ( | struct tegra_dc_sor_data * | sor | ) |
Definition at line 818 of file sor.c.
References BIOS_WARNING, tegra_dc_dp_link_config::link_bw, tegra_dc_sor_data::link_cfg, NV_SOR_LANE_DRIVE_CURRENT, NV_SOR_PR, tegra_dc_sor_data::portnum, printk, SOR_LINK_SPEED_G1_62, SOR_LINK_SPEED_G2_7, SOR_LINK_SPEED_G5_4, and tegra_sor_writel().
void tegra_dp_disable_tx_pu | ( | struct tegra_dc_sor_data * | sor | ) |
Definition at line 66 of file sor.c.
References NV_SOR_DP_PADCTL, NV_SOR_DP_PADCTL_TX_PU_DISABLE, NV_SOR_DP_PADCTL_TX_PU_MASK, tegra_dc_sor_data::portnum, and tegra_sor_write_field().
void tegra_dp_set_pe_vs_pc | ( | struct tegra_dc_sor_data * | sor, |
u32 | mask, | ||
u32 | pe_reg, | ||
u32 | vs_reg, | ||
u32 | pc_reg, | ||
u8 | pc_supported | ||
) |
Definition at line 74 of file sor.c.
References mask, NV_SOR_DC, NV_SOR_POSTCURSOR, NV_SOR_PR, tegra_dc_sor_data::portnum, and tegra_sor_write_field().
void tegra_sor_precharge_lanes | ( | struct tegra_dc_sor_data * | sor | ) |
Definition at line 885 of file sor.c.
References BIOS_ERR, tegra_dc_dp_link_config::lane_count, tegra_dc_sor_data::link_cfg, NV_SOR_DP_PADCTL, NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT, NV_SOR_DP_PADCTL_PD_TXD_0_NO, NV_SOR_DP_PADCTL_PD_TXD_1_NO, NV_SOR_DP_PADCTL_PD_TXD_2_NO, NV_SOR_DP_PADCTL_PD_TXD_3_NO, tegra_dc_sor_data::portnum, printk, tegra_sor_write_field(), udelay(), and val.