4 #ifndef _IPQ40XX_SPI_H_
5 #define _IPQ40XX_SPI_H_
11 #define BLSP0_QUP_REG_BASE ((void *)0x78b5000u)
12 #define BLSP1_QUP_REG_BASE ((void *)0x78b6000u)
14 #define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300)
15 #define BLSP1_SPI_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000300)
17 #define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304)
18 #define BLSP1_SPI_IO_CONTROL_REG (BLSP1_QUP_REG_BASE + 0x00000304)
20 #define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308)
21 #define BLSP1_SPI_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x00000308)
23 #define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310)
24 #define BLSP1_SPI_DEASSERT_WAIT_REG (BLSP1_QUP_REG_BASE + 0x00000310)
25 #define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c)
26 #define BLSP1_SPI_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x0000030c)
28 #define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000)
29 #define BLSP1_QUP_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000000)
31 #define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c)
32 #define BLSP1_QUP_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x0000001c)
34 #define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020)
35 #define BLSP1_QUP_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x00000020)
37 #define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028)
38 #define BLSP1_QUP_OPERATIONAL_MASK (BLSP1_QUP_REG_BASE + 0x00000028)
40 #define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018)
41 #define BLSP1_QUP_OPERATIONAL_REG (BLSP1_QUP_REG_BASE + 0x00000018)
43 #define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008)
44 #define BLSP1_QUP_IO_MODES_REG (BLSP1_QUP_REG_BASE + 0x00000008)
46 #define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004)
47 #define BLSP1_QUP_STATE_REG (BLSP1_QUP_REG_BASE + 0x00000004)
49 #define BLSP0_QUP_INPUT_FIFOc_REG(c) \
50 (BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c))
51 #define BLSP1_QUP_INPUT_FIFOc_REG(c) \
52 (BLSP1_QUP_REG_BASE + 0x00000218 + 4 * (c))
54 #define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \
55 (BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c))
56 #define BLSP1_QUP_OUTPUT_FIFOc_REG(c) \
57 (BLSP1_QUP_REG_BASE + 0x00000110 + 4 * (c))
59 #define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200)
60 #define BLSP1_QUP_MX_INPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000200)
62 #define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100)
63 #define BLSP1_QUP_MX_OUTPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000100)
65 #define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c)
66 #define BLSP1_QUP_SW_RESET_REG (BLSP1_QUP_REG_BASE + 0x0000000c)
68 #define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8)
69 #define QUP_CONFIG_MINI_CORE_SPI (1 << 8)
70 #define QUP_CONF_INPUT_MSK (1 << 7)
71 #define QUP_CONF_INPUT_ENA (0 << 7)
72 #define QUP_CONF_NO_INPUT (1 << 7)
73 #define QUP_CONF_OUTPUT_MSK (1 << 6)
74 #define QUP_CONF_OUTPUT_ENA (0 << 6)
75 #define QUP_CONF_NO_OUTPUT (1 << 6)
76 #define QUP_CONF_N_MASK 0x1F
77 #define QUP_CONF_N_SPI_8_BIT_WORD 0x07
79 #define SPI_CONFIG_INPUT_FIRST (1 << 9)
80 #define SPI_CONFIG_INPUT_FIRST_BACK (0 << 9)
81 #define SPI_CONFIG_LOOP_BACK_MSK (1 << 8)
82 #define SPI_CONFIG_NO_LOOP_BACK (0 << 8)
83 #define SPI_CONFIG_NO_SLAVE_OPER_MSK (1 << 5)
84 #define SPI_CONFIG_NO_SLAVE_OPER (0 << 5)
86 #define SPI_IO_CTRL_CLK_ALWAYS_ON (0 << 9)
87 #define SPI_IO_CTRL_MX_CS_MODE (1 << 8)
88 #define SPI_IO_CTRL_NO_TRI_STATE (1 << 0)
89 #define SPI_IO_CTRL_FORCE_CS_MSK (1 << 11)
90 #define SPI_IO_CTRL_FORCE_CS_EN (1 << 11)
91 #define SPI_IO_CTRL_FORCE_CS_DIS (0 << 11)
92 #define SPI_IO_CTRL_CLOCK_IDLE_HIGH (1 << 10)
94 #define QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK (1 << 16)
95 #define QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN (1 << 16)
96 #define QUP_IO_MODES_INPUT_MODE_MSK (0x03 << 12)
97 #define QUP_IO_MODES_INPUT_BLOCK_MODE (0x01 << 12)
98 #define QUP_IO_MODES_OUTPUT_MODE_MSK (0x03 << 10)
99 #define QUP_IO_MODES_OUTPUT_BLOCK_MODE (0x01 << 10)
101 #define SPI_INPUT_BLOCK_SIZE 4
102 #define SPI_OUTPUT_BLOCK_SIZE 4
104 #define MAX_COUNT_SIZE 0xffff
106 #define SPI_CORE_RESET 0
107 #define SPI_CORE_RUNNING 1
139 #define DUMMY_DATA_VAL 0
140 #define TIMEOUT_CNT 100
142 #define ETIMEDOUT -10
148 #define MAX_PACKET_COUNT ((64 * KiB) - 1)
void * qup_mx_output_count
void * qup_error_flags_en
void * qup_mx_input_count
const struct blsp_spi * regs