coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
reset.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <
cf9_reset.h
>
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#include <
reset.h
>
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#include <soc/southbridge.h>
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#include <
amdblocks/acpimmio.h
>
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#include <
amdblocks/reset.h
>
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void
do_cold_reset
(
void
)
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{
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/* De-assert and then assert all PwrGood signals on CF9 reset. */
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pm_write16
(
PWR_RESET_CFG
,
pm_read16
(
PWR_RESET_CFG
) |
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TOGGLE_ALL_PWR_GOOD
);
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outb
(
RST_CPU
|
SYS_RST
,
RST_CNT
);
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}
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void
do_warm_reset
(
void
)
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{
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/* Warm resets are not supported and must be executed as cold */
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pm_write16
(
PWR_RESET_CFG
,
pm_read16
(
PWR_RESET_CFG
) |
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TOGGLE_ALL_PWR_GOOD
);
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outb
(
RST_CPU
|
SYS_RST
,
RST_CNT
);
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}
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void
do_board_reset
(
void
)
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{
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do_cold_reset
();
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}
acpimmio.h
pm_write16
static void pm_write16(uint8_t reg, uint16_t value)
Definition:
acpimmio.h:186
pm_read16
static uint16_t pm_read16(uint8_t reg)
Definition:
acpimmio.h:171
PWR_RESET_CFG
#define PWR_RESET_CFG
Definition:
southbridge.h:13
TOGGLE_ALL_PWR_GOOD
#define TOGGLE_ALL_PWR_GOOD
Definition:
southbridge.h:14
cf9_reset.h
RST_CNT
#define RST_CNT
Definition:
cf9_reset.h:7
SYS_RST
#define SYS_RST
Definition:
cf9_reset.h:10
RST_CPU
#define RST_CPU
Definition:
cf9_reset.h:9
outb
void outb(u8 val, u16 port)
do_board_reset
void do_board_reset(void)
Definition:
reset.c:8
do_warm_reset
void do_warm_reset(void)
Definition:
reset.c:18
do_cold_reset
void do_cold_reset(void)
Definition:
reset.c:10
reset.h
reset.h
src
soc
amd
cezanne
reset.c
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