coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
f81866d_uart.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pnp.h>
6 #include "fintek_internal.h"
7 #include "f81866d.h"
8 
9 #define LDN_REG 0x07
10 #define PORT_SELECT_REGISTER 0x27
11 #define MULTI_FUNC_SEL3_REG 0x29
12 #define IRQ_SHARE_REGISTER 0xF0
13 #define FIFO_SEL_MODE 0xF6
14 
15 /*
16  * f81866d_uart_init enables all necessary registers for UART 3/4
17  * Fintek needs to know if pins are used as GPIO or UART pins
18  * Share interrupt usage needs to be enabled
19  */
20 void f81866d_uart_init(struct device *dev)
21 {
22  struct resource *res = probe_resource(dev, PNP_IDX_IO0);
23  u8 tmp;
24 
25  if (!res) {
26  printk(BIOS_WARNING, "%s: No UART resource found.\n", __func__);
27  return;
28  }
29 
31 
32  // Set Port Select Register (Bit 0) = 0
33  // before accessing Multi Function Select 3 Register
35  pnp_write_config(dev, PORT_SELECT_REGISTER, tmp & 0xFE);
36 
37  // Set UART 3 function (Bit 4/5), otherwise pin 36-43 are GPIO
38  if (dev->path.pnp.device == F81866D_SP3) {
40  pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30);
41  }
42 
43  // Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO
44  if (dev->path.pnp.device == F81866D_SP4) {
46  pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0);
47  }
48 
49  // Select UART X in LDN register
50  pnp_write_config(dev, LDN_REG, dev->path.pnp.device & 0xff);
51  // Set IRQ trigger mode from active low to high (Bit 3)
52  tmp = pnp_read_config(dev, FIFO_SEL_MODE);
53  pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8);
54  // Enable share interrupt (Bit 0)
56 
57  pnp_exit_conf_mode(dev);
58 }
#define printk(level,...)
Definition: stdlib.h:16
struct resource * probe_resource(const struct device *dev, unsigned int index)
See if a resource structure already exists for a given index.
Definition: device_util.c:323
#define F81866D_SP4
Definition: f81866d.h:17
#define F81866D_SP3
Definition: f81866d.h:16
#define IRQ_SHARE_REGISTER
Definition: f81866d_uart.c:12
#define FIFO_SEL_MODE
Definition: f81866d_uart.c:13
void f81866d_uart_init(struct device *dev)
Definition: f81866d_uart.c:20
#define LDN_REG
Definition: f81866d_uart.c:9
#define MULTI_FUNC_SEL3_REG
Definition: f81866d_uart.c:11
#define PORT_SELECT_REGISTER
Definition: f81866d_uart.c:10
#define BIOS_WARNING
BIOS_WARNING - Bad configuration.
Definition: loglevel.h:86
#define PNP_IDX_IO0
Definition: pnp_def.h:5
void pnp_exit_conf_mode(struct device *dev)
Definition: pnp_device.c:17
u8 pnp_read_config(struct device *dev, u8 reg)
Definition: pnp_device.c:44
void pnp_enter_conf_mode(struct device *dev)
Definition: pnp_device.c:11
void pnp_write_config(struct device *dev, u8 reg, u8 value)
Definition: pnp_device.c:38
uint8_t u8
Definition: stdint.h:45
struct pnp_path pnp
Definition: path.h:117
Definition: device.h:107
struct device_path path
Definition: device.h:115
unsigned int device
Definition: path.h:59