pll.h File Reference

#include <device/mmio.h>
#include <types.h>
#include <soc/pll_common.h>

Include dependency graph for pll.h:

Go to the source code of this file.

Data Structures
struct	mtk_topckgen_regs
struct	mtk_apmixed_regs

Enumerations
enum	{ PLL_CKSQ_ON_DELAY = 100 , PLL_PWR_ON_DELAY = 30 , PLL_ISO_DELAY = 1 , PLL_EN_DELAY = 20 }
enum	{ PCW_INTEGER_BITS = 8 }
enum	{ MT8195_PLL_EN = 0x1 << 9 , MT8195_APLL5_EN = (0x1 << 9) | (0x1 << 20) , GLITCH_FREE_EN = 0x1 << 12 , PLL_DIV_EN = 0xff << 24 }
enum	{   MCU_DIV_MASK = 0x1f << 17 , MCU_DIV_1 = 0x8 << 17 , MCU_MUX_MASK = 0x3 << 9 , MCU_MUX_SRC_PLL = 0x1 << 9 ,   MCU_MUX_SRC_26M = 0x0 << 9 }
enum	{   ARMPLL_LL_HZ = 1036 * MHz , ARMPLL_BL_HZ = 1027 * MHz , CCIPLL_HZ = 835 * MHz , NNAPLL_HZ = 860 * MHz ,   RESPLL_HZ = 600 * MHz , ETHPLL_HZ = 500 * MHz , MSDCPLL_HZ = 384 * MHz , TVDPLL1_HZ = 594 * MHz ,   TVDPLL2_HZ = 594 * MHz , MMPLL_HZ = 2750UL * MHz , MAINPLL_HZ = 2184UL * MHz , VDECPLL_HZ = 220 * MHz ,   IMGPLL_HZ = 650 * MHz , UNIVPLL_HZ = 2496UL * MHz , HDMIPLL1_HZ = 884 * MHz , HDMIPLL2_HZ = 600 * MHz ,   HDMIRX_APLL_HZ = 294915 * KHz , USB1PLL_HZ = 192 * MHz , ADSPPLL_HZ = 720 * MHz , APLL1_HZ = 196608 * KHz ,   APLL2_HZ = 180633600 , APLL3_HZ = 196608 * KHz , APLL4_HZ = 196608 * KHz , APLL5_HZ = 196608 * KHz ,   MFGPLL_HZ = 700 * MHz , DGIPLL_HZ = 165 * MHz }
enum	{ CLK26M_HZ = 26 * MHz , UNIVPLL_D6_D2_HZ = UNIVPLL_HZ / 6 / 2 }
enum	{ SPI_HZ = UNIVPLL_D6_D2_HZ , UART_HZ = CLK26M_HZ }
enum	{   INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18) , INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18) , INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK , INFRACFG_AO_INFRA_BUS_DCM_REG0_ON ,   INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = (0xf << 0) , INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = (0x0 << 0) , INFRACFG_AO_PERI_BUS_DCM_REG0_MASK , INFRACFG_AO_PERI_BUS_DCM_REG0_ON ,   INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = (0x1 << 29) | (0x1 << 31) , INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = (0x1 << 29) | (0x1 << 31) }

Functions
	check_member (mtk_topckgen_regs, clk_cfg_0, 0x0020)
	check_member (mtk_topckgen_regs, clk_cfg_11_clr, 0x00ac)
	check_member (mtk_topckgen_regs, clk_extck_reg, 0x0204)
	check_member (mtk_topckgen_regs, clk26cali_0, 0x0218)
	check_member (mtk_topckgen_regs, clk_misc_cfg_0, 0x022c)
	check_member (mtk_topckgen_regs, clk_misc_cfg_1, 0x0238)
	check_member (mtk_topckgen_regs, clk_misc_cfg_2, 0x0244)
	check_member (mtk_topckgen_regs, clk_misc_cfg_3, 0x0250)
	check_member (mtk_topckgen_regs, clk_misc_cfg_6, 0x025c)
	check_member (mtk_topckgen_regs, clkmon_clk_sel, 0x029c)
	check_member (mtk_topckgen_regs, cksta_reg_0, 0x02bc)
	check_member (mtk_topckgen_regs, clk_auddiv_0, 0x0320)
	check_member (mtk_topckgen_regs, clk_auddiv_4, 0x0338)
	check_member (mtk_apmixed_regs, pllon_con0, 0x0050)
	check_member (mtk_apmixed_regs, armpll_bl_con0, 0x0070)
	check_member (mtk_apmixed_regs, ap_pllgp2_con0, 0x0090)
	check_member (mtk_apmixed_regs, tvdpll1_con0, 0x00a0)
	check_member (mtk_apmixed_regs, tvdpll2_con0, 0x00c0)
	check_member (mtk_apmixed_regs, mmpll_con0, 0x00e0)
	check_member (mtk_apmixed_regs, imgpll_con0, 0x0100)
	check_member (mtk_apmixed_regs, ap_pllgp3_con0, 0x0120)
	check_member (mtk_apmixed_regs, dgipll_con0, 0x0150)
	check_member (mtk_apmixed_regs, respll_con0, 0x0190)
	check_member (mtk_apmixed_regs, mainpll_con0, 0x01d0)
	check_member (mtk_apmixed_regs, univpll_con0, 0x01f0)
	check_member (mtk_apmixed_regs, ulposc1_con0, 0x02b0)
	check_member (mtk_apmixed_regs, ulposc2_con0, 0x02c0)
	check_member (mtk_apmixed_regs, respll_con4, 0x0320)
	check_member (mtk_apmixed_regs, ap_pllgp4_con0, 0x0330)
	check_member (mtk_apmixed_regs, mfgpll_con0, 0x0340)
	check_member (mtk_apmixed_regs, ethpll_con0, 0x0360)
	check_member (mtk_apmixed_regs, nnapll_con0, 0x0390)
	check_member (mtk_apmixed_regs, ap_auxadc_con0, 0x0440)
	check_member (mtk_apmixed_regs, apll1_tuner_con0, 0x0470)
	check_member (mtk_apmixed_regs, pll_pwr_con0, 0x04c0)
	check_member (mtk_apmixed_regs, pll_iso_con0, 0x04d0)
	check_member (mtk_apmixed_regs, pll_stb_con0, 0x04e0)
	check_member (mtk_apmixed_regs, div_stb_con0, 0x04f0)
	check_member (mtk_apmixed_regs, ap_abist_mon_con0, 0x0500)
	check_member (mtk_apmixed_regs, cksys_occ_sel0, 0x0540)
	check_member (mtk_apmixed_regs, clkdiv_con0, 0x0580)
	check_member (mtk_apmixed_regs, armpll_ll_con4, 0x0600)
	check_member (mtk_apmixed_regs, ccipll_con1, 0x0634)
	check_member (mtk_apmixed_regs, univpll_con4, 0x0700)
	check_member (mtk_apmixed_regs, msdcpll_con0, 0x0710)
	check_member (mtk_apmixed_regs, apll4_con0, 0x0740)
	check_member (mtk_apmixed_regs, apll3_con0, 0x0760)
	check_member (mtk_apmixed_regs, apll2_con0, 0x0780)
	check_member (mtk_apmixed_regs, apll5_con0, 0x07a0)
	check_member (mtk_apmixed_regs, apll1_con0, 0x07c0)
	check_member (mtk_apmixed_regs, adsppll_con0, 0x07e0)
	check_member (mtk_apmixed_regs, mpll_con0, 0x0800)
	check_member (mtk_apmixed_regs, hdmipll2_con0, 0x0870)
	check_member (mtk_apmixed_regs, vdecpll_con0, 0x0890)
	check_member (mtk_apmixed_regs, hdmipll1_con0, 0x08c0)
	check_member (mtk_apmixed_regs, hdmirx_apll_con0, 0x08e0)
	check_member (mtk_apmixed_regs, occscan_con4, 0x0d80)
	check_member (mtk_apmixed_regs, apll1_con5, 0x0dc0)
	check_member (mtk_apmixed_regs, hdmirx_apll_con5, 0x0dd4)

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
PLL_CKSQ_ON_DELAY
PLL_PWR_ON_DELAY
PLL_ISO_DELAY
PLL_EN_DELAY

Definition at line 506 of file pll.h.

anonymous enum

anonymous enum

Enumerator
PCW_INTEGER_BITS

Definition at line 513 of file pll.h.

anonymous enum

anonymous enum

Enumerator
MT8195_PLL_EN
MT8195_APLL5_EN
GLITCH_FREE_EN
PLL_DIV_EN

Definition at line 517 of file pll.h.

anonymous enum

anonymous enum

Enumerator
MCU_DIV_MASK
MCU_DIV_1
MCU_MUX_MASK
MCU_MUX_SRC_PLL
MCU_MUX_SRC_26M

Definition at line 524 of file pll.h.

anonymous enum

anonymous enum

Enumerator
ARMPLL_LL_HZ
ARMPLL_BL_HZ
CCIPLL_HZ
NNAPLL_HZ
RESPLL_HZ
ETHPLL_HZ
MSDCPLL_HZ
TVDPLL1_HZ
TVDPLL2_HZ
MMPLL_HZ
MAINPLL_HZ
VDECPLL_HZ
IMGPLL_HZ
UNIVPLL_HZ
HDMIPLL1_HZ
HDMIPLL2_HZ
HDMIRX_APLL_HZ
USB1PLL_HZ
ADSPPLL_HZ
APLL1_HZ
APLL2_HZ
APLL3_HZ
APLL4_HZ
APLL5_HZ
MFGPLL_HZ
DGIPLL_HZ

Definition at line 534 of file pll.h.

anonymous enum

anonymous enum

Enumerator
CLK26M_HZ
UNIVPLL_D6_D2_HZ

Definition at line 564 of file pll.h.

anonymous enum

anonymous enum

Enumerator
SPI_HZ
UART_HZ

Definition at line 570 of file pll.h.

anonymous enum

anonymous enum

Enumerator
INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK
INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON
INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK
INFRACFG_AO_INFRA_BUS_DCM_REG0_ON
INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK
INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON
INFRACFG_AO_PERI_BUS_DCM_REG0_MASK
INFRACFG_AO_PERI_BUS_DCM_REG0_ON
INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK
INFRACFG_AO_PERI_MODULE_DCM_REG0_ON

Definition at line 583 of file pll.h.

Function Documentation

check_member() [1/59]

check_member	(	mtk_apmixed_regs	,
		adsppll_con0	,
		0x07e0
	)

check_member() [2/59]

check_member	(	mtk_apmixed_regs	,
		ap_abist_mon_con0	,
		0x0500
	)

check_member() [3/59]

check_member	(	mtk_apmixed_regs	,
		ap_auxadc_con0	,
		0x0440
	)

check_member() [4/59]

check_member	(	mtk_apmixed_regs	,
		ap_pllgp2_con0	,
		0x0090
	)

check_member() [5/59]

check_member	(	mtk_apmixed_regs	,
		ap_pllgp3_con0	,
		0x0120
	)

check_member() [6/59]

check_member	(	mtk_apmixed_regs	,
		ap_pllgp4_con0	,
		0x0330
	)

check_member() [7/59]

check_member	(	mtk_apmixed_regs	,
		apll1_con0	,
		0x07c0
	)

check_member() [8/59]

check_member	(	mtk_apmixed_regs	,
		apll1_con5	,
		0x0dc0
	)

check_member() [9/59]

check_member	(	mtk_apmixed_regs	,
		apll1_tuner_con0	,
		0x0470
	)

check_member() [10/59]

check_member	(	mtk_apmixed_regs	,
		apll2_con0	,
		0x0780
	)

check_member() [11/59]

check_member	(	mtk_apmixed_regs	,
		apll3_con0	,
		0x0760
	)

check_member() [12/59]

check_member	(	mtk_apmixed_regs	,
		apll4_con0	,
		0x0740
	)

check_member() [13/59]

check_member	(	mtk_apmixed_regs	,
		apll5_con0	,
		0x07a0
	)

check_member() [14/59]

check_member	(	mtk_apmixed_regs	,
		armpll_bl_con0	,
		0x0070
	)

check_member() [15/59]

check_member	(	mtk_apmixed_regs	,
		armpll_ll_con4	,
		0x0600
	)

check_member() [16/59]

check_member	(	mtk_apmixed_regs	,
		ccipll_con1	,
		0x0634
	)

check_member() [17/59]

check_member	(	mtk_apmixed_regs	,
		cksys_occ_sel0	,
		0x0540
	)

check_member() [18/59]

check_member	(	mtk_apmixed_regs	,
		clkdiv_con0	,
		0x0580
	)

check_member() [19/59]

check_member	(	mtk_apmixed_regs	,
		dgipll_con0	,
		0x0150
	)

check_member() [20/59]

check_member	(	mtk_apmixed_regs	,
		div_stb_con0	,
		0x04f0
	)

check_member() [21/59]

check_member	(	mtk_apmixed_regs	,
		ethpll_con0	,
		0x0360
	)

check_member() [22/59]

check_member	(	mtk_apmixed_regs	,
		hdmipll1_con0	,
		0x08c0
	)

check_member() [23/59]

check_member	(	mtk_apmixed_regs	,
		hdmipll2_con0	,
		0x0870
	)

check_member() [24/59]

check_member	(	mtk_apmixed_regs	,
		hdmirx_apll_con0	,
		0x08e0
	)

check_member() [25/59]

check_member	(	mtk_apmixed_regs	,
		hdmirx_apll_con5	,
		0x0dd4
	)

check_member() [26/59]

check_member	(	mtk_apmixed_regs	,
		imgpll_con0	,
		0x0100
	)

check_member() [27/59]

check_member	(	mtk_apmixed_regs	,
		mainpll_con0	,
		0x01d0
	)

check_member() [28/59]

check_member	(	mtk_apmixed_regs	,
		mfgpll_con0	,
		0x0340
	)

check_member() [29/59]

check_member	(	mtk_apmixed_regs	,
		mmpll_con0	,
		0x00e0
	)

check_member() [30/59]

check_member	(	mtk_apmixed_regs	,
		mpll_con0	,
		0x0800
	)

check_member() [31/59]

check_member	(	mtk_apmixed_regs	,
		msdcpll_con0	,
		0x0710
	)

check_member() [32/59]

check_member	(	mtk_apmixed_regs	,
		nnapll_con0	,
		0x0390
	)

check_member() [33/59]

check_member	(	mtk_apmixed_regs	,
		occscan_con4	,
		0x0d80
	)

check_member() [34/59]

check_member	(	mtk_apmixed_regs	,
		pll_iso_con0	,
		0x04d0
	)

check_member() [35/59]

check_member	(	mtk_apmixed_regs	,
		pll_pwr_con0	,
		0x04c0
	)

check_member() [36/59]

check_member	(	mtk_apmixed_regs	,
		pll_stb_con0	,
		0x04e0
	)

check_member() [37/59]

check_member	(	mtk_apmixed_regs	,
		pllon_con0	,
		0x0050
	)

check_member() [38/59]

check_member	(	mtk_apmixed_regs	,
		respll_con0	,
		0x0190
	)

check_member() [39/59]

check_member	(	mtk_apmixed_regs	,
		respll_con4	,
		0x0320
	)

check_member() [40/59]

check_member	(	mtk_apmixed_regs	,
		tvdpll1_con0	,
		0x00a0
	)

check_member() [41/59]

check_member	(	mtk_apmixed_regs	,
		tvdpll2_con0	,
		0x00c0
	)

check_member() [42/59]

check_member	(	mtk_apmixed_regs	,
		ulposc1_con0	,
		0x02b0
	)

check_member() [43/59]

check_member	(	mtk_apmixed_regs	,
		ulposc2_con0	,
		0x02c0
	)

check_member() [44/59]

check_member	(	mtk_apmixed_regs	,
		univpll_con0	,
		0x01f0
	)

check_member() [45/59]

check_member	(	mtk_apmixed_regs	,
		univpll_con4	,
		0x0700
	)

check_member() [46/59]

check_member	(	mtk_apmixed_regs	,
		vdecpll_con0	,
		0x0890
	)

check_member() [47/59]

check_member	(	mtk_topckgen_regs	,
		cksta_reg_0	,
		0x02bc
	)

check_member() [48/59]

check_member	(	mtk_topckgen_regs	,
		clk26cali_0	,
		0x0218
	)

check_member() [49/59]

check_member	(	mtk_topckgen_regs	,
		clk_auddiv_0	,
		0x0320
	)

check_member() [50/59]

check_member	(	mtk_topckgen_regs	,
		clk_auddiv_4	,
		0x0338
	)

check_member() [51/59]

check_member	(	mtk_topckgen_regs	,
		clk_cfg_0	,
		0x0020
	)

check_member() [52/59]

check_member	(	mtk_topckgen_regs	,
		clk_cfg_11_clr	,
		0x00ac
	)

check_member() [53/59]

check_member	(	mtk_topckgen_regs	,
		clk_extck_reg	,
		0x0204
	)

check_member() [54/59]

check_member	(	mtk_topckgen_regs	,
		clk_misc_cfg_0	,
		0x022c
	)

check_member() [55/59]

check_member	(	mtk_topckgen_regs	,
		clk_misc_cfg_1	,
		0x0238
	)

check_member() [56/59]

check_member	(	mtk_topckgen_regs	,
		clk_misc_cfg_2	,
		0x0244
	)

check_member() [57/59]

check_member	(	mtk_topckgen_regs	,
		clk_misc_cfg_3	,
		0x0250
	)

check_member() [58/59]

check_member	(	mtk_topckgen_regs	,
		clk_misc_cfg_6	,
		0x025c
	)

check_member() [59/59]

check_member	(	mtk_topckgen_regs	,
		clkmon_clk_sel	,
		0x029c
	)