coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
sdram-lpddr3-K4E8E304EE-2GB.inc
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1 { /* 2GB (8Gb + 8Gb) for dual rank dram setting */
2  {
3  .impedance_drvp = 0x9,
4  .impedance_drvn = 0xa,
5  .datlat_ucfirst = 18,
6 
7  .ca_train = {
8  [CHANNEL_A] = { 6, 4, 3, 5, 4, 0, 0, 0, 0, 0},
9  [CHANNEL_B] = { 1, 1, 1, 1, 0, 6, 5, 5, 5, 7}
10  },
11 
12  .ca_train_center = {
13  [CHANNEL_A] = 3,
14  [CHANNEL_B] = 3
15  },
16 
17  .wr_level = {
18  [CHANNEL_A] = { 8, 10, 6, 8},
19  [CHANNEL_B] = { 9, 9, 7, 6}
20  },
21 
22  .gating_win = {
23  [CHANNEL_A] = {
24  { 27, 64},
25  { 27, 72}
26  },
27  [CHANNEL_B] = {
28  { 27, 72},
29  { 27, 72}
30  }
31  },
32 
33  .rx_dqs_dly = {
34  [CHANNEL_A] = 0x08080908,
35  [CHANNEL_B] = 0x0b0b060b
36  },
37 
38  .rx_dq_dly = {
39  [CHANNEL_A] = {
40  0x01010300,
41  0x06030002,
42  0x01010201,
43  0x03020002,
44  0x00010103,
45  0x02010201,
46  0x02040200,
47  0x02020201
48  },
49  [CHANNEL_B] = {
50  0x00020202,
51  0x02020202,
52  0x01020201,
53  0x01010100,
54  0x01010101,
55  0x01000002,
56  0x02000201,
57  0x00010101,
58  }
59  },
60  },
61  {
62  .actim = 0xaafd478c,
63  .actim1 = 0x91001f59,
64  .actim05t = 0x000025e1,
65  .conf1 = 0x00048403,
66  .conf2 = 0x030000a9,
67  .ddr2ctl = 0x000063b1,
68  .gddr3ctl1 = 0x11000000,
69  .misctl0 = 0x21000000,
70  .pd_ctrl = 0xd1976442,
71  .rkcfg = 0x002156c1,
72  .test2_3 = 0xbfc70401,
73  .test2_4 = 0x2801110d
74  },
75  {
76  .cona = 0x50535057,
77  .conb = 0x17283544,
78  .conc = 0x0a1a0b1a,
79  .cond = 0x00000000,
80  .cone = 0xffff0848,
81  .conf = 0x08420000,
82  .cong = 0x2b2b2a38,
83  .conh = 0x00000000,
84  .conm_1 = 0x40000500,
85  .conm_2 = 0x400005ff,
86  .mdct_1 = 0x80030303,
87  .mdct_2 = 0x34220c3f,
88  .test0 = 0xcccccccc,
89  .test1 = 0xcccccccc,
90  .testb = 0x00060124,
91  .testc = 0x38470000,
92  .testd = 0x00000000,
93  .arba = 0x7f077a49,
94  .arbc = 0xa0a070dd,
95  .arbd = 0x07007046,
96  .arbe = 0x40407046,
97  .arbf = 0xa0a070c6,
98  .arbg = 0xffff7047,
99  .arbi = 0x20406188,
100  .arbj = 0x9719595e,
101  .arbk = 0x64f3fc79,
102  .slct_1 = 0x00010800,
103  .slct_2 = 0xff03ff00,
104  .bmen = 0x00ff0001
105  },
106  {
107  .mrs_1 = 0x00830001,
108  .mrs_2 = 0x001c0002,
109  .mrs_3 = 0x00010003,
110  .mrs_10 = 0x00ff000a,
111  .mrs_11 = 0x0000000b,
112  .mrs_63 = 0x0000003f
113  },
114  .type = TYPE_LPDDR3,
115  .dram_freq = 896 * MHz,
116 },
#define MHz
Definition: helpers.h:80
@ CHANNEL_A
Definition: dramc_soc.h:7
@ CHANNEL_B
Definition: dramc_soc.h:8
@ TYPE_LPDDR3
Definition: emi.h:15