coreboot
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dramc_soc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _DRAMC_SOC_H_
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#define _DRAMC_SOC_H_
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enum
{
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CHANNEL_A
= 0,
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CHANNEL_B
,
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CHANNEL_NUM
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};
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enum
{
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GW_PARAM_COARSE
= 0,
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GW_PARAM_FINE
,
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GW_PARAM_NUM
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};
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enum
{
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DUAL_RANKS
= 2,
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CATRAINING_NUM
= 10
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};
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enum
{
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DQ_DATA_WIDTH
= 32,
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DQS_BIT_NUMBER
= 8,
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DQS_NUMBER
= (
DQ_DATA_WIDTH
/
DQS_BIT_NUMBER
)
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};
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#endif
/* _DRAMC_COMMON_H_ */
DQS_NUMBER
@ DQS_NUMBER
Definition:
dramc_soc.h:26
DQ_DATA_WIDTH
@ DQ_DATA_WIDTH
Definition:
dramc_soc.h:24
DQS_BIT_NUMBER
@ DQS_BIT_NUMBER
Definition:
dramc_soc.h:25
CHANNEL_A
@ CHANNEL_A
Definition:
dramc_soc.h:7
CHANNEL_NUM
@ CHANNEL_NUM
Definition:
dramc_soc.h:9
CHANNEL_B
@ CHANNEL_B
Definition:
dramc_soc.h:8
CATRAINING_NUM
@ CATRAINING_NUM
Definition:
dramc_soc.h:20
DUAL_RANKS
@ DUAL_RANKS
Definition:
dramc_soc.h:19
GW_PARAM_COARSE
@ GW_PARAM_COARSE
Definition:
dramc_soc.h:13
GW_PARAM_FINE
@ GW_PARAM_FINE
Definition:
dramc_soc.h:14
GW_PARAM_NUM
@ GW_PARAM_NUM
Definition:
dramc_soc.h:15
src
soc
mediatek
mt8173
include
soc
dramc_soc.h
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