13 #define WAK_STS (1 << 15)
14 #define PCIEXPWAK_STS (1 << 14)
15 #define PRBTNOR_STS (1 << 11)
16 #define RTC_STS (1 << 10)
17 #define PWRBTN_STS (1 << 8)
18 #define GBL_STS (1 << 5)
20 #define RTC_EN (1 << 10)
21 #define PWRBTN_EN (1 << 8)
22 #define GBL_EN (1 << 5)
23 #define TMROF_EN (1 << 0)
25 #define GBL_RLS (1 << 2)
26 #define SCI_EN (1 << 0)
29 #define ESPI_SMI_EN (1 << 28)
30 #define PERIODIC_EN (1 << 14)
31 #define TCO_SMI_EN (1 << 13)
32 #define APMC_EN (1 << 5)
33 #define SLP_SMI_EN (1 << 4)
34 #define BIOS_EN (1 << 2)
36 #define GBL_SMI_EN (1 << 0)
38 #define SMI_STS_BITS 32
39 #define XHCI_SMI_STS_BIT 31
40 #define ME_SMI_STS_BIT 30
41 #define SERIAL_IO_SMI_STS_BIT 29
42 #define ESPI_SMI_STS_BIT 28
43 #define GPIO_UNLOCK_SMI_STS_BIT 27
44 #define SPI_SMI_STS_BIT 26
45 #define SCC_SMI_STS_BIT 25
46 #define IE_SMI_STS_BIT 23
47 #define MONITOR_STS_BIT 21
48 #define PCI_EXP_SMI_STS_BIT 20
49 #define SMBUS_SMI_STS_BIT 16
50 #define SERIRQ_SMI_STS_BIT 15
51 #define PERIODIC_STS_BIT 14
52 #define TCO_STS_BIT 13
53 #define DEVMON_STS_BIT 12
54 #define MCSMI_STS_BIT 11
55 #define GPIO_STS_BIT 10
56 #define GPE0_STS_BIT 9
58 #define SWSMI_TMR_STS_BIT 6
60 #define SMI_ON_SLP_EN_STS_BIT 4
61 #define LEGACY_USB_STS_BIT 3
62 #define BIOS_STS_BIT 2
64 #define SWGPE_CTRL (1 << 1)
65 #define DEVACT_STS 0x44
67 #define GPE0_REG_MAX 4
68 #define GPE0_REG_SIZE 32
69 #define GPE0_STS(x) (0x80 + ((x) * 4))
70 #define GPE0_EN(x) (0x90 + ((x) * 4))
72 #define GPE_STS_RSVD GPE_STD
73 #define GPIO_T2_STS (1 << 15)
74 #define PME_B0_STS (1 << 13)
75 #define PME_STS (1 << 11)
76 #define PCI_EXP_STS (1 << 9)
77 #define SMB_WAK_STS (1 << 7)
78 #define TCOSCI_STS (1 << 6)
79 #define GPE0_EN(x) (0x90 + ((x) * 4))
80 #define GPIO_T2_EN (1 << 15)
81 #define ESPI_EN (1 << 14)
82 #define PME_B0_EN (1 << 13)
83 #define PME_EN (1 << 11)
84 #define PCI_EXP_EN (1 << 9)
85 #define TCOSCI_EN (1 << 6)
87 #define ENABLE_SMI_PARAMS \
88 (APMC_EN | GBL_SMI_EN | EOS)
91 #define PSS_MAX_ENTRIES 16
92 #define PSS_RATIO_STEP 1
93 #define PSS_LATENCY_TRANSITION 10
94 #define PSS_LATENCY_BUSMASTER 10
98 #define CF9_LOCK (1 << 31)
99 #define CF9_GLB_RST (1 << 20)
uint16_t get_pmbase(void)
struct chipset_power_state __packed
uint8_t * pmc_mmio_regs(void)
uint32_t prev_sleep_state