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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
| struct | chipset_power_state |
Macros | |
| #define | PM1_STS 0x00 |
| #define | WAK_STS (1 << 15) |
| #define | PCIEXPWAK_STS (1 << 14) |
| #define | PRBTNOR_STS (1 << 11) |
| #define | RTC_STS (1 << 10) |
| #define | PWRBTN_STS (1 << 8) |
| #define | GBL_STS (1 << 5) |
| #define | PM1_EN 0x02 |
| #define | RTC_EN (1 << 10) |
| #define | PWRBTN_EN (1 << 8) |
| #define | GBL_EN (1 << 5) |
| #define | TMROF_EN (1 << 0) |
| #define | PM1_CNT 0x04 |
| #define | GBL_RLS (1 << 2) |
| #define | SCI_EN (1 << 0) |
| #define | PM1_TMR 0x08 |
| #define | SMI_EN 0x30 |
| #define | ESPI_SMI_EN (1 << 28) |
| #define | PERIODIC_EN (1 << 14) |
| #define | TCO_SMI_EN (1 << 13) |
| #define | APMC_EN (1 << 5) |
| #define | SLP_SMI_EN (1 << 4) |
| #define | BIOS_EN (1 << 2) |
| #define | EOS (1 << 1) |
| #define | GBL_SMI_EN (1 << 0) |
| #define | SMI_STS 0x34 |
| #define | SMI_STS_BITS 32 |
| #define | XHCI_SMI_STS_BIT 31 |
| #define | ME_SMI_STS_BIT 30 |
| #define | SERIAL_IO_SMI_STS_BIT 29 |
| #define | ESPI_SMI_STS_BIT 28 |
| #define | GPIO_UNLOCK_SMI_STS_BIT 27 |
| #define | SPI_SMI_STS_BIT 26 |
| #define | SCC_SMI_STS_BIT 25 |
| #define | IE_SMI_STS_BIT 23 |
| #define | MONITOR_STS_BIT 21 |
| #define | PCI_EXP_SMI_STS_BIT 20 |
| #define | SMBUS_SMI_STS_BIT 16 |
| #define | SERIRQ_SMI_STS_BIT 15 |
| #define | PERIODIC_STS_BIT 14 |
| #define | TCO_STS_BIT 13 |
| #define | DEVMON_STS_BIT 12 |
| #define | MCSMI_STS_BIT 11 |
| #define | GPIO_STS_BIT 10 |
| #define | GPE0_STS_BIT 9 |
| #define | PM1_STS_BIT 8 |
| #define | SWSMI_TMR_STS_BIT 6 |
| #define | APM_STS_BIT 5 |
| #define | SMI_ON_SLP_EN_STS_BIT 4 |
| #define | LEGACY_USB_STS_BIT 3 |
| #define | BIOS_STS_BIT 2 |
| #define | GPE_CNTL 0x42 |
| #define | SWGPE_CTRL (1 << 1) |
| #define | DEVACT_STS 0x44 |
| #define | PM2_CNT 0x50 |
| #define | GPE0_REG_MAX 4 |
| #define | GPE0_REG_SIZE 32 |
| #define | GPE0_STS(x) (0x80 + ((x) * 4)) |
| #define | GPE0_EN(x) (0x90 + ((x) * 4)) |
| #define | GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ |
| #define | GPE_STS_RSVD GPE_STD |
| #define | GPIO_T2_STS (1 << 15) |
| #define | PME_B0_STS (1 << 13) |
| #define | PME_STS (1 << 11) |
| #define | PCI_EXP_STS (1 << 9) |
| #define | SMB_WAK_STS (1 << 7) |
| #define | TCOSCI_STS (1 << 6) |
| #define | GPE0_EN(x) (0x90 + ((x) * 4)) |
| #define | GPIO_T2_EN (1 << 15) |
| #define | ESPI_EN (1 << 14) |
| #define | PME_B0_EN (1 << 13) |
| #define | PME_EN (1 << 11) |
| #define | PCI_EXP_EN (1 << 9) |
| #define | TCOSCI_EN (1 << 6) |
| #define | ENABLE_SMI_PARAMS (APMC_EN | GBL_SMI_EN | EOS) |
| #define | PSS_MAX_ENTRIES 16 |
| #define | PSS_RATIO_STEP 1 |
| #define | PSS_LATENCY_TRANSITION 10 |
| #define | PSS_LATENCY_BUSMASTER 10 |
| #define | ETR 0xac |
| #define | CF9_LOCK (1 << 31) |
| #define | CF9_GLB_RST (1 << 20) |
| #define | PRSTS 0x10 |
Functions | |
| uint8_t * | pmc_mmio_regs (void) |
| uint16_t | get_pmbase (void) |
| void | pmc_lock_smi (void) |
Variables | |
| struct chipset_power_state | __packed |
| #define ENABLE_SMI_PARAMS (APMC_EN | GBL_SMI_EN | EOS) |
Definition at line 57 of file pmc.c.
References BIOS_DEBUG, GEN_PMCON_A, PCH_DEV_PMC, pci_or_config32(), printk, and SMI_LOCK.
Definition at line 142 of file pmutil.c.
References PCH_DEV_PMC, PCH_PWRM_BASE_ADDRESS, pci_read_config32(), PMC_PWRM_BASE, and PWRMBASE.
Referenced by clear_rtc_failed(), deep_s3_enabled(), pmc_set_disb(), pmc_soc_set_afterg3_en(), soc_fill_power_state(), soc_read_pmc_base(), and vbnv_cmos_failed().
| struct chipset_power_state __packed |
1.9.1