coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
superio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <device/device.h>
4 #include <device/pnp.h>
5 #include <superio/conf_mode.h>
6 #include <pc80/keyboard.h>
7 
8 #include "lpc47m10x.h"
9 
10 /**
11  * Initialize the specified Super I/O device.
12  *
13  * Devices other than COM ports and the keyboard controller are ignored.
14  * For COM ports, we configure the baud rate.
15  *
16  * @param dev Pointer to structure describing a Super I/O device.
17  */
18 static void lpc47m10x_init(struct device *dev)
19 {
20  if (!dev->enabled)
21  return;
22 
23  switch (dev->path.pnp.device) {
24  case LPC47M10X2_KBC:
26  break;
27  }
28 }
29 
30 static struct device_operations ops = {
32  .set_resources = pnp_set_resources,
33  .enable_resources = pnp_enable_resources,
34  .enable = pnp_alt_enable,
35  .init = lpc47m10x_init,
36  .ops_pnp_mode = &pnp_conf_mode_55_aa,
37 };
38 
39 static struct pnp_info pnp_dev_info[] = {
40  { NULL, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
41  { NULL, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
42  { NULL, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
43  { NULL, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
45  0x07ff, 0x07ff, },
46  { NULL, LPC47M10X2_PME, PNP_IO0, 0x0f80, },
47 };
48 
49 /**
50  * Create device structures and allocate resources to devices specified in the
51  * pnp_dev_info array (above).
52  *
53  * @param dev Pointer to structure describing a Super I/O device.
54  */
55 static void enable_dev(struct device *dev)
56 {
58 }
59 
61  CHIP_NAME("SMSC LPC47M10x Super I/O")
62  .enable_dev = enable_dev
63 };
#define ARRAY_SIZE(a)
Definition: helpers.h:12
const struct pnp_mode_ops pnp_conf_mode_55_aa
Definition: conf_mode.c:175
#define CHIP_NAME(X)
Definition: device.h:32
uint8_t pc_keyboard_init(uint8_t probe_aux)
Definition: keyboard.c:229
#define NO_AUX_DEVICE
Definition: keyboard.h:6
#define LPC47M10X2_PME
Definition: lpc47m10x.h:15
#define LPC47M10X2_SP1
Definition: lpc47m10x.h:11
#define LPC47M10X2_SP2
Definition: lpc47m10x.h:12
#define LPC47M10X2_PP
Definition: lpc47m10x.h:10
#define LPC47M10X2_KBC
Definition: lpc47m10x.h:13
#define LPC47M10X2_FDC
Definition: lpc47m10x.h:9
#define PNP_IRQ1
Definition: pnp.h:48
#define PNP_DRQ0
Definition: pnp.h:49
#define PNP_IO1
Definition: pnp.h:43
#define PNP_IO0
Definition: pnp.h:42
#define PNP_IRQ0
Definition: pnp.h:47
void pnp_read_resources(struct device *dev)
Definition: pnp_device.c:114
void pnp_enable_devices(struct device *base_dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info)
Definition: pnp_device.c:371
void pnp_set_resources(struct device *dev)
Definition: pnp_device.c:157
void pnp_alt_enable(struct device *dev)
Definition: pnp_device.c:191
void pnp_enable_resources(struct device *dev)
Definition: pnp_device.c:173
static void enable_dev(struct device *dev)
Create device structures and allocate resources to devices specified in the pnp_dev_info array (above...
Definition: superio.c:55
static void lpc47m10x_init(struct device *dev)
Initialize the specified Super I/O device.
Definition: superio.c:18
static struct device_operations ops
Definition: superio.c:30
static struct pnp_info pnp_dev_info[]
Definition: superio.c:39
struct chip_operations superio_smsc_lpc47m10x_ops
Definition: superio.c:60
#define NULL
Definition: stddef.h:19
void(* read_resources)(struct device *dev)
Definition: device.h:39
struct pnp_path pnp
Definition: path.h:117
Definition: device.h:107
struct device_path path
Definition: device.h:115
unsigned int enabled
Definition: device.h:122
Definition: pnp.h:37
unsigned int device
Definition: path.h:59