3 #ifndef SOC_INTEL_COMMON_BLOCK_PMC_IPC_H
4 #define SOC_INTEL_COMMON_BLOCK_PMC_IPC_H
8 #define PMC_IPC_BUF_COUNT 4
10 #define PMC_IPC_CMD_COMMAND_SHIFT 0
11 #define PMC_IPC_CMD_COMMAND_MASK 0xff
12 #define PMC_IPC_CMD_MSI_SHIFT 8
13 #define PMC_IPC_CMD_MSI_MASK 0x01
14 #define PMC_IPC_CMD_SUB_COMMAND_SHIFT 12
15 #define PMC_IPC_CMD_SUB_COMMAND_MASK 0x0f
16 #define PMC_IPC_CMD_SIZE_SHIFT 16
17 #define PMC_IPC_CMD_SIZE_MASK 0xff
20 #define PMC_IPC_CMD_COMMAND_FIVR 0xA3
22 #define PMC_IPC_CMD_CMD_ID_FIVR_READ 0x00
24 #define PMC_IPC_CMD_CMD_ID_FIVR_WRITE 0x01
26 #define PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC 0
28 #define PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC 1
30 #define PMC_IPC_SUBCMD_EMI_CTRL0_LOGIC 2
32 #define PMC_IPC_SUBCMD_FFFC_FAULT_STATUS 3
34 #define PMC_IPC_SUBCMD_FFFC_RFI_STATUS 4
36 #define PMC_IPC_CMD_FIELD(name, val) \
37 ((((val) & PMC_IPC_CMD_##name##_MASK) << PMC_IPC_CMD_##name##_SHIFT))
39 #define PMC_IPC_CMD_NO_MSI 0
42 #define PMC_IPC_CMD_RD_PMC_REG 0xA0
43 #define PMC_IPC_CMD_SUBCMD_RD_PMC_REG 0x02
46 #define PMC_IPC_CMD_ID_SET_PCIE_CLOCK 0xAC
49 #define PMC_IPC_SUCCESS 0
50 #define PMC_IPC_ERROR 1
51 #define PMC_IPC_TIMEOUT 2
cb_err
coreboot error codes
#define PMC_IPC_CMD_FIELD(name, val)
#define PMC_IPC_BUF_COUNT
void pmc_ipc_acpi_set_pci_clock(unsigned int pcie_rp, unsigned int clock_pin, bool enable)
enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, struct pmc_ipc_buffer *rbuf)
#define PMC_IPC_CMD_NO_MSI
void pmc_ipc_acpi_fill_ssdt(void)
static uint32_t pmc_make_ipc_cmd(uint32_t cmd, uint32_t subcmd, uint32_t size)
uint32_t buf[PMC_IPC_BUF_COUNT]