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Macros
#define	BIT0 0x00000001

#define	BIT1 0x00000002

#define	BIT2 0x00000004

#define	BIT3 0x00000008

#define	BIT4 0x00000010

#define	BIT5 0x00000020

#define	BIT6 0x00000040

#define	BIT7 0x00000080

#define	BIT8 0x00000100

#define	BIT9 0x00000200

#define	BIT10 0x00000400

#define	BIT11 0x00000800

#define	BIT12 0x00001000

#define	BIT13 0x00002000

#define	BIT14 0x00004000

#define	BIT15 0x00008000

#define	BIT16 0x00010000

#define	BIT17 0x00020000

#define	BIT18 0x00040000

#define	BIT19 0x00080000

#define	BIT20 0x00100000

#define	BIT21 0x00200000

#define	BIT22 0x00400000

#define	BIT23 0x00800000

#define	BIT24 0x01000000

#define	BIT25 0x02000000

#define	BIT26 0x04000000

#define	BIT27 0x08000000

#define	BIT28 0x10000000

#define	BIT29 0x20000000

#define	BIT30 0x40000000

#define	BIT31 0x80000000

#define	MC_BUS PCI_BUS_NUMBER_QNC

#define	MC_DEV 0x00

#define	MC_FUN 0x00

#define	QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID

#define	QUARK_MC_DEVICE_ID 0x0958

#define	QUARK2_MC_DEVICE_ID 0x12C0

#define	QNC_MC_REV_ID_A0 0x00

#define	QNC_ACCESS_PORT_MCR 0xD0

#define	QNC_MCR_MASK 0x000000ff

#define	QNC_MCR_BYTE_ENABLES 0x000000f0

#define	QNC_ACCESS_PORT_MDR 0xD4

#define	QNC_ACCESS_PORT_MEA 0xD8

#define	QNC_MEA_MASK 0xffffff00

#define	QNC_MCR_OP_OFFSET 24

#define	QNC_MCR_PORT_OFFSET 16

#define	QNC_MCR_REG_OFFSET 8

#define	LShift16(value) (value << 16)

#define	QUARK_OPCODE_READ 0x10

#define	QUARK_OPCODE_WRITE 0x11

#define	QUARK_ALT_OPCODE_READ 0x06

#define	QUARK_ALT_OPCODE_WRITE 0x07

#define	QUARK_OPCODE_IO_READ 0x02

#define	QUARK_OPCODE_IO_WRITE 0x03

#define	QUARK_DRAM_BASE_ADDR_READY 0x78

#define	QUARK_ECC_SCRUB_RESUME 0xC2

#define	QUARK_ECC_SCRUB_PAUSE 0xC3

#define	QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00

#define	QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01

#define	QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03

#define	QUARK_NC_RMU_SB_PORT_ID 0x04

#define	QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05

#define	QUARK_SC_USB_AFE_SB_PORT_ID 0x14

#define	QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16

#define	QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31

#define	QUARK_SCSS_FUSE_SB_PORT_ID 0x33

#define	QUARK_ICLK_SB_PORT_ID 0x32

#define	QUARK_SCSS_CRU_SB_PORT_ID 0x34

#define	QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21

#define	ASTATUS_PRI_CASUAL 0x0

#define	ASTATUS_PRI_IMPENDING 0x1

#define	ASTATUS_PRI_NORMAL 0x2

#define	ASTATUS_PRI_URGENT 0x3

#define	ASTATUS1_RASISED_BP (10)

#define	ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)

#define	ASTATUS0_RASISED_BP (8)

#define	ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)

#define	ASTATUS1_DEFAULT_BP (2)

#define	ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)

#define	ASTATUS0_DEFAULT_BP (0)

#define	ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)

#define	QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70

#define	B_DFUSESTAT_ECC_DIS (BIT0)

#define	QNC_MSG_TMPM_REG_PMBA 0x70

#define	QUARK_NC_RMU_REG_CONFIG 0x71

#define	TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6)

#define	TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5)

#define	QUARK_NC_RMU_REG_OPTIONS_1 0x72

#define	OPTIONS_1_DMA_DISABLE (BIT0)

#define	QUARK_NC_RMU_REG_WDT_CONTROL 0x74

#define	B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 \| BIT18)

#define	B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18

#define	V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE 0

#define	V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)

#define	V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)

#define	V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)

#define	QUARK_NC_RMU_REG_TS_MODE 0xB0

#define	TS_ENABLE (BIT15)

#define	QUARK_NC_RMU_REG_TS_TRIP 0xB2

#define	TS_HOT_TRIP_CLEAR_THOLD_BP 24

#define	TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP)

#define	TS_CAT_TRIP_CLEAR_THOLD_BP 16

#define	TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP)

#define	TS_HOT_TRIP_SET_THOLD_BP 8

#define	TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP)

#define	TS_CAT_TRIP_SET_THOLD_BP 0

#define	TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP)

#define	QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50

#define	SCRUB_CFG_INTERVAL_SHIFT 0x00

#define	SCRUB_CFG_INTERVAL_MASK 0xFF

#define	SCRUB_CFG_BLOCKSIZE_SHIFT 0x08

#define	SCRUB_CFG_BLOCKSIZE_MASK 0x1F

#define	SCRUB_CFG_ACTIVE (BIT13)

#define	SCRUB_CFG_INVALID 0x00000FFF

#define	QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76

#define	QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77

#define	QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C

#define	SCRUB_RESUME_MSG()

#define	SCRUB_PAUSE_MSG()

#define	QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82

#define	BLOCK_ENABLE_PG (1 << 28)

#define	BLOCK_DISABLE_PG (1 << 29)

#define	QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19

#define	EnableIMRInt BIT31

#define	QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C

#define	EnableSMMInt BIT31

#define	QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20

#define	DRAM_NON_HOST_RQ_LIMIT_BP 0

#define	DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP)

#define	QUARK_NC_TOTAL_IMR_SET 0x8

#define	QUARK_NC_MEMORY_MANAGER_IMR0 0x40

#define	QUARK_NC_MEMORY_MANAGER_IMR1 0x44

#define	QUARK_NC_MEMORY_MANAGER_IMR2 0x48

#define	QUARK_NC_MEMORY_MANAGER_IMR3 0x4C

#define	QUARK_NC_MEMORY_MANAGER_IMR4 0x50

#define	QUARK_NC_MEMORY_MANAGER_IMR5 0x54

#define	QUARK_NC_MEMORY_MANAGER_IMR6 0x58

#define	QUARK_NC_MEMORY_MANAGER_IMR7 0x5C

#define	QUARK_NC_MEMORY_MANAGER_IMRXL 0x00

#define	IMR_LOCK BIT31

#define	IMR_EN BIT30

#define	IMRL_MASK 0x00FFFFFC

#define	IMRL_RESET 0x00000000

#define	QUARK_NC_MEMORY_MANAGER_IMRXH 0x01

#define	IMRH_MASK 0x00FFFFFC

#define	IMRH_RESET 0x00000000

#define	QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02

#define	QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03

#define	IMRX_ALL_ACCESS 0xFFFFFFFF

#define	CPU_SNOOP BIT30

#define	RMU BIT29

#define	CPU0_NON_SMM BIT0

#define	QNC_MSG_FSBIC_REG_HMISC 0x03

#define	SMI_EN (BIT19)

#define	FSEG_RD_DRAM (BIT2)

#define	ESEG_RD_DRAM (BIT1)

#define	QNC_MSG_FSBIC_REG_HSMMC 0x04

#define	NON_HOST_SMM_WR_OPEN (BIT18)

#define	NON_HOST_SMM_RD_OPEN (BIT17)

#define	SMM_CODE_RD_OPEN (BIT16)

#define	SMM_CTL_EN (BIT3)

#define	SMM_WRITE_OPEN (BIT2)

#define	SMM_READ_OPEN (BIT1)

#define	SMM_LOCKED (BIT0)

#define	SMM_START_MASK 0x0000FFF0

#define	SMM_END_MASK 0xFFF00000

#define	QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08

#define	HMBOUND_MASK 0x0FFFFF000

#define	HMBOUND_LOCK BIT0

#define	QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A

#define	HLEGACY_SMI_PIN_VALUE BIT12

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54

#define	QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68

#define	QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69

#define	QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00

#define	B_STPDDRCFG_FORCE_RECOVERY BIT0

#define	QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25

#define	B_ROM_FUSE_IN_SECURE_SKU BIT6

#define	QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31

#define	B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 \| BIT4 \| BIT3)

#define	B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3

#define	B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK

#define	B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8

#define	B_TSCGF1_CONFIG_IBGEN BIT17

#define	B_TSCGF1_CONFIG_IBGEN_BP 17

#define	B_TSCGF1_CONFIG_IBGCHOPEN BIT18

#define	B_TSCGF1_CONFIG_IBGCHOPEN_BP 18

#define	B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14

#define	B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14

#define	QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32

#define	B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF

#define	B_TSCGF2_CONFIG_IDSCONTROL_BP 0

#define	B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000

#define	B_TSCGF2_CONFIG_IDSTIMING_BP 16

#define	QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33

#define	B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000

#define	B_TSCGF2_CONFIG2_ISPARECTRL_BP 24

#define	B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 \| BIT8)

#define	B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8

#define	B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF

#define	B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0

#define	QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34

#define	B_TSCGF3_CONFIG_ITSRST BIT0

#define	B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11

#define	B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP)

#define	QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36

#define	SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20

#define	SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19

#define	SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18

#define	SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17

#define	SOCCLKEN_CONFIG_BB_RST_B BIT16

#define	QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36

#define	QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51

#define	B_CFG_STICKY_RW_SMM_VIOLATION BIT0

#define	B_CFG_STICKY_RW_HMB_VIOLATION BIT1

#define	B_CFG_STICKY_RW_IMR_VIOLATION BIT2

#define	B_CFG_STICKY_RW_DECC_VIOLATION BIT3

#define	B_CFG_STICKY_RW_WARM_RST BIT4

#define	B_CFG_STICKY_RW_FORCE_RECOVERY BIT9

#define	B_CFG_STICKY_RW_VIOLATION

#define	B_CFG_STICKY_RW_ALL

#define	QUARK_ICLK_MUXTOP 0x0140

#define	B_MUXTOP_FLEX2_MASK (BIT25 \| BIT24 \| BIT23)

#define	B_MUXTOP_FLEX2_BP 23

#define	B_MUXTOP_FLEX1_MASK (BIT22 \| BIT21 \| BIT20)

#define	B_MUXTOP_FLEX1_BP 20

#define	QUARK_ICLK_SSC1 0x0314

#define	QUARK_ICLK_SSC2 0x0414

#define	QUARK_ICLK_SSC3 0x0514

#define	QUARK_ICLK_REF2_DBUFF0 0x2000

#define	QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080

#define	QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180

#define	OCFGPIMIXLOAD_1_0 BIT6

#define	OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F

#define	V_INTEL_VENDOR_ID 0x8086

#define	PCI_BUS_NUMBER_QNC 0x00

#define	PCI_DEVICE_NUMBER_QNC_LPC 31

#define	PCI_FUNCTION_NUMBER_QNC_LPC 0

#define	R_QNC_LPC_VENDOR_ID 0x00

#define	V_LPC_VENDOR_ID V_INTEL_VENDOR_ID

#define	R_QNC_LPC_DEVICE_ID 0x02

#define	QUARK_V_LPC_DEVICE_ID_0 0x095E

#define	R_QNC_LPC_REV_ID 0x08

#define	R_QNC_LPC_SMBUS_BASE 0x40

#define	B_QNC_LPC_SMBUS_BASE_EN (BIT31)

#define	B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0

#define	R_QNC_SMBUS_HCTL 0x00

#define	B_QNC_SMBUS_START (BIT4)

#define	V_QNC_SMBUS_HCTL_CMD_QUICK 0

#define	V_QNC_SMBUS_HCTL_CMD_BYTE 1

#define	V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2

#define	V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3

#define	V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4

#define	V_QNC_SMBUS_HCTL_CMD_BLOCK 5

#define	R_QNC_SMBUS_HSTS 0x01

#define	B_QNC_SMBUS_BERR (BIT2)

#define	B_QNC_SMBUS_DERR (BIT1)

#define	B_QNC_SMBUS_BYTE_DONE_STS (BIT0)

#define	B_QNC_SMBUS_HSTS_ALL 0x07

#define	R_QNC_SMBUS_HCLK 0x02

#define	V_QNC_SMBUS_HCLK_100KHZ 0x0054

#define	R_QNC_SMBUS_TSA 0x04

#define	V_QNC_SMBUS_RW_SEL_READ 1

#define	V_QNC_SMBUS_RW_SEL_WRITE 0

#define	R_QNC_SMBUS_HCMD 0x05

#define	R_QNC_SMBUS_HD0 0x06

#define	R_QNC_SMBUS_HD1 0x07

#define	R_QNC_SMBUS_HBD 0x20

#define	R_QNC_LPC_GBA_BASE 0x44

#define	B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0

#define	R_QNC_GPIO_CGEN_CORE_WELL 0x00

#define	R_QNC_GPIO_CGIO_CORE_WELL 0x04

#define	R_QNC_GPIO_CGLVL_CORE_WELL 0x08

#define	R_QNC_GPIO_CGTPE_CORE_WELL 0x0C

#define	R_QNC_GPIO_CGTNE_CORE_WELL 0x10

#define	R_QNC_GPIO_CGGPE_CORE_WELL 0x14

#define	R_QNC_GPIO_CGSMI_CORE_WELL 0x18

#define	R_QNC_GPIO_CGTS_CORE_WELL 0x1C

#define	R_QNC_GPIO_RGEN_RESUME_WELL 0x20

#define	R_QNC_GPIO_RGIO_RESUME_WELL 0x24

#define	R_QNC_GPIO_RGLVL_RESUME_WELL 0x28

#define	R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C

#define	R_QNC_GPIO_RGTNE_RESUME_WELL 0x30

#define	R_QNC_GPIO_RGGPE_RESUME_WELL 0x34

#define	R_QNC_GPIO_RGSMI_RESUME_WELL 0x38

#define	R_QNC_GPIO_RGTS_RESUME_WELL 0x3C

#define	R_QNC_GPIO_CNMIEN_CORE_WELL 0x40

#define	R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44

#define	R_QNC_LPC_PM1BLK 0x48

#define	B_QNC_LPC_PM1BLK_MASK 0x0000FFF0

#define	R_QNC_PM1BLK_PM1S 0x00

#define	S_QNC_PM1BLK_PM1S 2

#define	B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)

#define	B_QNC_PM1BLK_PM1S_WAKE (BIT15)

#define	B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14)

#define	B_QNC_PM1BLK_PM1S_RTC (BIT10)

#define	B_QNC_PM1BLK_PM1S_GLOB (BIT5)

#define	B_QNC_PM1BLK_PM1S_TO (BIT0)

#define	N_QNC_PM1BLK_PM1S_RTC 10

#define	R_QNC_PM1BLK_PM1E 0x02

#define	S_QNC_PM1BLK_PM1E 2

#define	B_QNC_PM1BLK_PM1E_PWAKED (BIT14)

#define	B_QNC_PM1BLK_PM1E_RTC (BIT10)

#define	B_QNC_PM1BLK_PM1E_GLOB (BIT5)

#define	N_QNC_PM1BLK_PM1E_RTC 10

#define	R_QNC_PM1BLK_PM1C 0x04

#define	B_QNC_PM1BLK_PM1C_SLPEN (BIT13)

#define	B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10)

#define	V_S0 0x00000000

#define	V_S3 0x00001400

#define	V_S4 0x00001800

#define	V_S5 0x00001C00

#define	B_QNC_PM1BLK_PM1C_SCIEN (BIT0)

#define	R_QNC_PM1BLK_PM1T 0x08

#define	R_QNC_LPC_GPE0BLK 0x4C

#define	B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0

#define	R_QNC_GPE0BLK_GPE0S 0x00

#define	S_QNC_GPE0BLK_GPE0S 4

#define	B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800

#define	B_QNC_GPE0BLK_GPE0S_PCIE (BIT17)

#define	B_QNC_GPE0BLK_GPE0S_GPIO (BIT14)

#define	B_QNC_GPE0BLK_GPE0S_EGPE (BIT13)

#define	N_QNC_GPE0BLK_GPE0S_THRM 12

#define	R_QNC_GPE0BLK_GPE0E 0x04

#define	S_QNC_GPE0BLK_GPE0E 4

#define	B_QNC_GPE0BLK_GPE0E_PCIE (BIT17)

#define	B_QNC_GPE0BLK_GPE0E_GPIO (BIT14)

#define	B_QNC_GPE0BLK_GPE0E_EGPE (BIT13)

#define	N_QNC_GPE0BLK_GPE0E_THRM 12

#define	R_QNC_GPE0BLK_SMIE 0x10

#define	S_QNC_GPE0BLK_SMIE 4

#define	B_QNC_GPE0BLK_SMIE_ALL 0x0003871F

#define	B_QNC_GPE0BLK_SMIE_APM (BIT4)

#define	B_QNC_GPE0BLK_SMIE_SLP (BIT2)

#define	B_QNC_GPE0BLK_SMIE_SWT (BIT1)

#define	N_QNC_GPE0BLK_SMIE_GPIO 9

#define	N_QNC_GPE0BLK_SMIE_ESMI 8

#define	N_QNC_GPE0BLK_SMIE_APM 4

#define	N_QNC_GPE0BLK_SMIE_SPI 3

#define	N_QNC_GPE0BLK_SMIE_SLP 2

#define	N_QNC_GPE0BLK_SMIE_SWT 1

#define	R_QNC_GPE0BLK_SMIS 0x14

#define	S_QNC_GPE0BLK_SMIS 4

#define	B_QNC_GPE0BLK_SMIS_ALL 0x0003871F

#define	B_QNC_GPE0BLK_SMIS_EOS (BIT31)

#define	B_QNC_GPE0BLK_SMIS_APM (BIT4)

#define	B_QNC_GPE0BLK_SMIS_SPI (BIT3)

#define	B_QNC_GPE0BLK_SMIS_SLP (BIT2)

#define	B_QNC_GPE0BLK_SMIS_SWT (BIT1)

#define	B_QNC_GPE0BLK_SMIS_BIOS (BIT0)

#define	N_QNC_GPE0BLK_SMIS_GPIO 9

#define	N_QNC_GPE0BLK_SMIS_APM 4

#define	N_QNC_GPE0BLK_SMIS_SPI 3

#define	N_QNC_GPE0BLK_SMIS_SLP 2

#define	N_QNC_GPE0BLK_SMIS_SWT 1

#define	R_QNC_GPE0BLK_PMCW 0x28

#define	B_QNC_GPE0BLK_PMCW_PSE (BIT31)

#define	R_QNC_GPE0BLK_PMSW 0x2C

#define	B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0)

#define	R_QNC_LPC_ACTL 0x58

#define	V_QNC_LPC_ACTL_SCIS_IRQ9 0x00

#define	QNC_NUMBER_PIRQS 8

#define	R_QNC_LPC_PIRQA_ROUT 0x60

#define	R_QNC_LPC_PIRQB_ROUT 0x61

#define	R_QNC_LPC_PIRQC_ROUT 0x62

#define	R_QNC_LPC_PIRQD_ROUT 0x63

#define	R_QNC_LPC_PIRQE_ROUT 0x64

#define	R_QNC_LPC_PIRQF_ROUT 0x65

#define	R_QNC_LPC_PIRQG_ROUT 0x66

#define	R_QNC_LPC_PIRQH_ROUT 0x67

#define	B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)

#define	R_QNC_LPC_WDTBA 0x84

#define	R_QNC_LPC_WDT_WDTCR 0x10

#define	R_QNC_LPC_WDT_WDTLR 0x18

#define	R_QNC_LPC_FWH_BIOS_DEC 0xD4

#define	B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31)

#define	B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30)

#define	B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29)

#define	B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28)

#define	B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27)

#define	B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26)

#define	B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25)

#define	B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24)

#define	R_QNC_LPC_BIOS_CNTL 0xD8

#define	S_QNC_LPC_BIOS_CNTL 4

#define	B_QNC_LPC_BIOS_CNTL_PFE (BIT8)

#define	B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5)

#define	B_QNC_LPC_BIOS_CNTL_BCD (BIT2)

#define	B_QNC_LPC_BIOS_CNTL_BLE (BIT1)

#define	B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0)

#define	N_QNC_LPC_BIOS_CNTL_BLE 1

#define	N_QNC_LPC_BIOS_CNTL_BIOSWE 0

#define	R_QNC_LPC_RCBA 0xF0

#define	B_QNC_LPC_RCBA_MASK 0xFFFFC000

#define	B_QNC_LPC_RCBA_EN (BIT0)

#define	R_APM_CNT 0xB2

#define	RST_CNT 0xCF9

#define	B_RST_CNT_COLD_RST (BIT3)

#define	B_RST_CNT_WARM_RST (BIT1)

#define	PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20

#define	PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21

#define	PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0

#define	PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23

#define	PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0

#define	PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1

#define	MAX_PCI_EXPRESS_ROOT_PORTS 2

#define	R_QNC_PCIE_BNUM 0x18

#define	R_QNC_PCIE_CAP_PTR 0x34

#define	PCIE_CAPID 0x10

#define	PCIE_CAP_EXT_HEARDER_OFFSET 0x100

#define	PCIE_DEV_CAP_OFFSET 0x04

#define	PCIE_LINK_CAP_OFFSET 0x0C

#define	PCIE_LINK_CNT_OFFSET 0x10

#define	PCIE_LINK_STS_OFFSET 0x12

#define	PCIE_SLOT_CAP_OFFSET 0x14

#define	R_QNC_PCIE_XCAP 0x42

#define	B_QNC_PCIE_XCAP_SI (BIT8)

#define	R_QNC_PCIE_DCAP 0x44

#define	B_QNC_PCIE_DCAP_E1AL (BIT11 \| BIT10 \| BIT9)

#define	B_QNC_PCIE_DCAP_E0AL (BIT8 \| BIT7 \| BIT6)

#define	R_QNC_PCIE_DCTL 0x48

#define	B_QNC_PCIE_DCTL_URE (BIT3)

#define	B_QNC_PCIE_DCTL_FEE (BIT2)

#define	B_QNC_PCIE_DCTL_NFE (BIT1)

#define	B_QNC_PCIE_DCTL_CEE (BIT0)

#define	R_QNC_PCIE_LCAP 0x4C

#define	B_QNC_PCIE_LCAP_CPM (BIT18)

#define	B_QNC_PCIE_LCAP_EL1_MASK (BIT17 \| BIT16 \| BIT15)

#define	B_QNC_PCIE_LCAP_EL0_MASK (BIT14 \| BIT13 \| BIT12)

#define	B_QNC_PCIE_LCAP_APMS_MASK (BIT11 \| BIT10)

#define	V_QNC_PCIE_LCAP_APMS_OFFSET 10

#define	R_QNC_PCIE_LCTL 0x50

#define	B_QNC_PCIE_LCTL_CCC (BIT6)

#define	B_QNC_PCIE_LCTL_RL (BIT5)

#define	R_QNC_PCIE_LSTS 0x52

#define	B_QNC_PCIE_LSTS_SCC (BIT12)

#define	B_QNC_PCIE_LSTS_LT (BIT11)

#define	R_QNC_PCIE_SLCAP 0x54

#define	B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F

#define	V_QNC_PCIE_SLCAP_SLV 0x0A

#define	V_QNC_PCIE_SLCAP_SLV_OFFSET 7

#define	V_QNC_PCIE_SLCAP_PSN_OFFSET 19

#define	R_QNC_PCIE_SLCTL 0x58

#define	B_QNC_PCIE_SLCTL_HPE (BIT5)

#define	B_QNC_PCIE_SLCTL_PDE (BIT3)

#define	B_QNC_PCIE_SLCTL_ABE (BIT0)

#define	R_QNC_PCIE_SLSTS 0x5A

#define	B_QNC_PCIE_SLSTS_PDS (BIT6)

#define	B_QNC_PCIE_SLSTS_PDC (BIT3)

#define	B_QNC_PCIE_SLSTS_ABP (BIT0)

#define	R_QNC_PCIE_RCTL 0x5C

#define	B_QNC_PCIE_RCTL_PIE (BIT3)

#define	B_QNC_PCIE_RCTL_SFE (BIT2)

#define	B_QNC_PCIE_RCTL_SNE (BIT1)

#define	B_QNC_PCIE_RCTL_SCE (BIT0)

#define	R_QNC_PCIE_SVID 0x94

#define	R_QNC_PCIE_CCFG 0xD0

#define	B_QNC_PCIE_CCFG_UPSD (BIT24)

#define	B_QNC_PCIE_CCFG_UNRS (BIT15)

#define	B_QNC_PCIE_CCFG_UPRS (BIT14)

#define	R_QNC_PCIE_MPC2 0xD4

#define	B_QNC_PCIE_MPC2_IPF (BIT11)

#define	R_QNC_PCIE_MPC 0xD8

#define	B_QNC_PCIE_MPC_PMCE (BIT31)

#define	B_QNC_PCIE_MPC_HPCE (BIT30)

#define	B_QNC_PCIE_MPC_HPME (BIT1)

#define	B_QNC_PCIE_MPC_PMME (BIT0)

#define	R_QNC_PCIE_IOSFSBCTL 0xF6

#define	B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 \| BIT0)

#define	B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 \| BIT0)

#define	V_PCIE_MAX_TRY_TIMES 200

#define	R_EFI_PCI_SVID 0x2C

#define	IOAPIC_BASE 0xFEC00000

#define	IOAPIC_SIZE 0x1000

#define	R_QNC_RCRB_SPIBASE 0x3020

#define	R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00)

#define	B_QNC_RCRB_SPIS_SCL (BIT15)

#define	B_QNC_RCRB_SPIS_BAS (BIT3)

#define	B_QNC_RCRB_SPIS_CDS (BIT2)

#define	B_QNC_RCRB_SPIS_SCIP (BIT0)

#define	R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02)

#define	B_QNC_RCRB_SPIC_DC (BIT14)

#define	B_QNC_RCRB_SPIC_DBC 0x3F00

#define	B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4)

#define	B_QNC_RCRB_SPIC_SPOP (BIT3)

#define	B_QNC_RCRB_SPIC_ACS (BIT2)

#define	B_QNC_RCRB_SPIC_SCGO (BIT1)

#define	R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04)

#define	B_QNC_RCRB_SPIA_MASK 0x00FFFFFF

#define	R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08)

#define	R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54)

#define	R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56)

#define	B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0

#define	B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0)

#define	B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1)

#define	B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1)

#define	R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58)

#define	R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60)

#define	R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64)

#define	R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68)

#define	B_QNC_RCRB_SPIPBRn_WPE (BIT31)

#define	R_QNC_RCRB_AGENT0IR 0x3140

#define	R_QNC_RCRB_AGENT1IR 0x3142

#define	R_QNC_RCRB_AGENT2IR 0x3144

#define	R_QNC_RCRB_AGENT3IR 0x3146

Macro Definition Documentation

◆ ASTATUS0_DEFAULT_BP

#define ASTATUS0_DEFAULT_BP (0)

Definition at line 158 of file QuarkNcSocId.h.

◆ ASTATUS0_DEFAULT_BP_MASK

#define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)

Definition at line 159 of file QuarkNcSocId.h.

◆ ASTATUS0_RASISED_BP

#define ASTATUS0_RASISED_BP (8)

Definition at line 154 of file QuarkNcSocId.h.

◆ ASTATUS0_RASISED_BP_MASK

#define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)

Definition at line 155 of file QuarkNcSocId.h.

◆ ASTATUS1_DEFAULT_BP

#define ASTATUS1_DEFAULT_BP (2)

Definition at line 156 of file QuarkNcSocId.h.

◆ ASTATUS1_DEFAULT_BP_MASK

#define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)

Definition at line 157 of file QuarkNcSocId.h.

◆ ASTATUS1_RASISED_BP

#define ASTATUS1_RASISED_BP (10)

Definition at line 152 of file QuarkNcSocId.h.

◆ ASTATUS1_RASISED_BP_MASK

#define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)

Definition at line 153 of file QuarkNcSocId.h.

◆ ASTATUS_PRI_CASUAL

#define ASTATUS_PRI_CASUAL 0x0

Definition at line 148 of file QuarkNcSocId.h.

◆ ASTATUS_PRI_IMPENDING

#define ASTATUS_PRI_IMPENDING 0x1

Definition at line 149 of file QuarkNcSocId.h.

◆ ASTATUS_PRI_NORMAL

#define ASTATUS_PRI_NORMAL 0x2

Definition at line 150 of file QuarkNcSocId.h.

◆ ASTATUS_PRI_URGENT

#define ASTATUS_PRI_URGENT 0x3

Definition at line 151 of file QuarkNcSocId.h.

◆ B_CFG_STICKY_RW_ALL

#define B_CFG_STICKY_RW_ALL

Value:

(B_CFG_STICKY_RW_VIOLATION \

| B_CFG_STICKY_RW_WARM_RST)

B_CFG_STICKY_RW_VIOLATION

#define B_CFG_STICKY_RW_VIOLATION

Definition: QuarkNcSocId.h:377

B_CFG_STICKY_RW_WARM_RST

#define B_CFG_STICKY_RW_WARM_RST

Definition: QuarkNcSocId.h:375

Definition at line 382 of file QuarkNcSocId.h.

◆ B_CFG_STICKY_RW_DECC_VIOLATION

#define B_CFG_STICKY_RW_DECC_VIOLATION BIT3

Definition at line 374 of file QuarkNcSocId.h.

◆ B_CFG_STICKY_RW_FORCE_RECOVERY

#define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9

Definition at line 376 of file QuarkNcSocId.h.

◆ B_CFG_STICKY_RW_HMB_VIOLATION

#define B_CFG_STICKY_RW_HMB_VIOLATION BIT1

Definition at line 372 of file QuarkNcSocId.h.

◆ B_CFG_STICKY_RW_IMR_VIOLATION

#define B_CFG_STICKY_RW_IMR_VIOLATION BIT2

Definition at line 373 of file QuarkNcSocId.h.

◆ B_CFG_STICKY_RW_SMM_VIOLATION

#define B_CFG_STICKY_RW_SMM_VIOLATION BIT0

Definition at line 371 of file QuarkNcSocId.h.

◆ B_CFG_STICKY_RW_VIOLATION

#define B_CFG_STICKY_RW_VIOLATION

Value:

                (B_CFG_STICKY_RW_SMM_VIOLATION \
                | B_CFG_STICKY_RW_HMB_VIOLATION \
                | B_CFG_STICKY_RW_IMR_VIOLATION \
                | B_CFG_STICKY_RW_DECC_VIOLATION)

Definition at line 377 of file QuarkNcSocId.h.

◆ B_CFG_STICKY_RW_WARM_RST

#define B_CFG_STICKY_RW_WARM_RST BIT4

Definition at line 375 of file QuarkNcSocId.h.

◆ B_DFUSESTAT_ECC_DIS

#define B_DFUSESTAT_ECC_DIS (BIT0)

Definition at line 165 of file QuarkNcSocId.h.

◆ B_MUXTOP_FLEX1_BP

#define B_MUXTOP_FLEX1_BP 20

Definition at line 392 of file QuarkNcSocId.h.

◆ B_MUXTOP_FLEX1_MASK

#define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20)

Definition at line 391 of file QuarkNcSocId.h.

◆ B_MUXTOP_FLEX2_BP

#define B_MUXTOP_FLEX2_BP 23

Definition at line 390 of file QuarkNcSocId.h.

◆ B_MUXTOP_FLEX2_MASK

#define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23)

Definition at line 389 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_GPE0E_EGPE

#define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13)

Definition at line 536 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_GPE0E_GPIO

#define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14)

Definition at line 535 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_GPE0E_PCIE

#define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17)

Definition at line 534 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_GPE0S_ALL

#define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800

Definition at line 526 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_GPE0S_EGPE

#define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13)

Definition at line 529 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_GPE0S_GPIO

#define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14)

Definition at line 528 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_GPE0S_PCIE

#define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17)

Definition at line 527 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_PMCW_PSE

#define B_QNC_GPE0BLK_PMCW_PSE (BIT31)

Definition at line 568 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_PMSW_DRAM_INIT

#define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0)

Definition at line 571 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIE_ALL

#define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F

Definition at line 541 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIE_APM

#define B_QNC_GPE0BLK_SMIE_APM (BIT4)

Definition at line 542 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIE_SLP

#define B_QNC_GPE0BLK_SMIE_SLP (BIT2)

Definition at line 543 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIE_SWT

#define B_QNC_GPE0BLK_SMIE_SWT (BIT1)

Definition at line 544 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIS_ALL

#define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F

Definition at line 554 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIS_APM

#define B_QNC_GPE0BLK_SMIS_APM (BIT4)

Definition at line 556 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIS_BIOS

#define B_QNC_GPE0BLK_SMIS_BIOS (BIT0)

Definition at line 560 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIS_EOS

#define B_QNC_GPE0BLK_SMIS_EOS (BIT31)

Definition at line 555 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIS_SLP

#define B_QNC_GPE0BLK_SMIS_SLP (BIT2)

Definition at line 558 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIS_SPI

#define B_QNC_GPE0BLK_SMIS_SPI (BIT3)

Definition at line 557 of file QuarkNcSocId.h.

◆ B_QNC_GPE0BLK_SMIS_SWT

#define B_QNC_GPE0BLK_SMIS_SWT (BIT1)

Definition at line 559 of file QuarkNcSocId.h.

◆ B_QNC_LPC_BIOS_CNTL_BCD

#define B_QNC_LPC_BIOS_CNTL_BCD (BIT2)

Definition at line 614 of file QuarkNcSocId.h.

◆ B_QNC_LPC_BIOS_CNTL_BIOSWE

#define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0)

Definition at line 616 of file QuarkNcSocId.h.

◆ B_QNC_LPC_BIOS_CNTL_BLE

#define B_QNC_LPC_BIOS_CNTL_BLE (BIT1)

Definition at line 615 of file QuarkNcSocId.h.

◆ B_QNC_LPC_BIOS_CNTL_PFE

#define B_QNC_LPC_BIOS_CNTL_PFE (BIT8)

Definition at line 612 of file QuarkNcSocId.h.

◆ B_QNC_LPC_BIOS_CNTL_SMM_BWP

#define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5)

Definition at line 613 of file QuarkNcSocId.h.

◆ B_QNC_LPC_FWH_BIOS_DEC_C0

#define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24)

Definition at line 608 of file QuarkNcSocId.h.

◆ B_QNC_LPC_FWH_BIOS_DEC_C8

#define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25)

Definition at line 607 of file QuarkNcSocId.h.

◆ B_QNC_LPC_FWH_BIOS_DEC_D0

#define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26)

Definition at line 606 of file QuarkNcSocId.h.

◆ B_QNC_LPC_FWH_BIOS_DEC_D8

#define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27)

Definition at line 605 of file QuarkNcSocId.h.

◆ B_QNC_LPC_FWH_BIOS_DEC_E0

#define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28)

Definition at line 604 of file QuarkNcSocId.h.

◆ B_QNC_LPC_FWH_BIOS_DEC_E8

#define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29)

Definition at line 603 of file QuarkNcSocId.h.

◆ B_QNC_LPC_FWH_BIOS_DEC_F0

#define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30)

Definition at line 602 of file QuarkNcSocId.h.

◆ B_QNC_LPC_FWH_BIOS_DEC_F8

#define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31)

Definition at line 601 of file QuarkNcSocId.h.

◆ B_QNC_LPC_GPA_BASE_MASK

#define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0

Definition at line 462 of file QuarkNcSocId.h.

◆ B_QNC_LPC_GPE0BLK_MASK

#define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0

Definition at line 521 of file QuarkNcSocId.h.

◆ B_QNC_LPC_PIRQX_ROUT

#define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)

Definition at line 592 of file QuarkNcSocId.h.

◆ B_QNC_LPC_PM1BLK_MASK

#define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0

Definition at line 487 of file QuarkNcSocId.h.

◆ B_QNC_LPC_RCBA_EN

#define B_QNC_LPC_RCBA_EN (BIT0)

Definition at line 622 of file QuarkNcSocId.h.

◆ B_QNC_LPC_RCBA_MASK

#define B_QNC_LPC_RCBA_MASK 0xFFFFC000

Definition at line 621 of file QuarkNcSocId.h.

◆ B_QNC_LPC_SMBUS_BASE_EN

#define B_QNC_LPC_SMBUS_BASE_EN (BIT31)

Definition at line 427 of file QuarkNcSocId.h.

◆ B_QNC_LPC_SMBUS_BASE_MASK

#define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0

Definition at line 428 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_CCFG_UNRS

#define B_QNC_PCIE_CCFG_UNRS (BIT15)

Definition at line 748 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_CCFG_UPRS

#define B_QNC_PCIE_CCFG_UPRS (BIT14)

Definition at line 749 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_CCFG_UPSD

#define B_QNC_PCIE_CCFG_UPSD (BIT24)

Definition at line 747 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_DCAP_E0AL

#define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6)

Definition at line 702 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_DCAP_E1AL

#define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9)

Definition at line 700 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_DCTL_CEE

#define B_QNC_PCIE_DCTL_CEE (BIT0)

Definition at line 708 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_DCTL_FEE

#define B_QNC_PCIE_DCTL_FEE (BIT2)

Definition at line 706 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_DCTL_NFE

#define B_QNC_PCIE_DCTL_NFE (BIT1)

Definition at line 707 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_DCTL_URE

#define B_QNC_PCIE_DCTL_URE (BIT3)

Definition at line 705 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER

#define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0)

Definition at line 762 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_IOSFSBCTL_SBIC_MASK

#define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0)

Definition at line 760 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_LCAP_APMS_MASK

#define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10)

Definition at line 715 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_LCAP_CPM

#define B_QNC_PCIE_LCAP_CPM (BIT18)

Definition at line 710 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_LCAP_EL0_MASK

#define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12)

Definition at line 713 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_LCAP_EL1_MASK

#define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15)

Definition at line 712 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_LCTL_CCC

#define B_QNC_PCIE_LCTL_CCC (BIT6)

Definition at line 718 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_LCTL_RL

#define B_QNC_PCIE_LCTL_RL (BIT5)

Definition at line 719 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_LSTS_LT

#define B_QNC_PCIE_LSTS_LT (BIT11)

Definition at line 722 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_LSTS_SCC

#define B_QNC_PCIE_LSTS_SCC (BIT12)

Definition at line 721 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_MPC2_IPF

#define B_QNC_PCIE_MPC2_IPF (BIT11)

Definition at line 751 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_MPC_HPCE

#define B_QNC_PCIE_MPC_HPCE (BIT30)

Definition at line 754 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_MPC_HPME

#define B_QNC_PCIE_MPC_HPME (BIT1)

Definition at line 756 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_MPC_PMCE

#define B_QNC_PCIE_MPC_PMCE (BIT31)

Definition at line 753 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_MPC_PMME

#define B_QNC_PCIE_MPC_PMME (BIT0)

Definition at line 757 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_RCTL_PIE

#define B_QNC_PCIE_RCTL_PIE (BIT3)

Definition at line 740 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_RCTL_SCE

#define B_QNC_PCIE_RCTL_SCE (BIT0)

Definition at line 743 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_RCTL_SFE

#define B_QNC_PCIE_RCTL_SFE (BIT2)

Definition at line 741 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_RCTL_SNE

#define B_QNC_PCIE_RCTL_SNE (BIT1)

Definition at line 742 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_SLCAP_MASK_RSV_VALUE

#define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F

Definition at line 724 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_SLCTL_ABE

#define B_QNC_PCIE_SLCTL_ABE (BIT0)

Definition at line 733 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_SLCTL_HPE

#define B_QNC_PCIE_SLCTL_HPE (BIT5)

Definition at line 731 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_SLCTL_PDE

#define B_QNC_PCIE_SLCTL_PDE (BIT3)

Definition at line 732 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_SLSTS_ABP

#define B_QNC_PCIE_SLSTS_ABP (BIT0)

Definition at line 737 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_SLSTS_PDC

#define B_QNC_PCIE_SLSTS_PDC (BIT3)

Definition at line 736 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_SLSTS_PDS

#define B_QNC_PCIE_SLSTS_PDS (BIT6)

Definition at line 735 of file QuarkNcSocId.h.

◆ B_QNC_PCIE_XCAP_SI

#define B_QNC_PCIE_XCAP_SI (BIT8)

Definition at line 697 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1C_SCIEN

#define B_QNC_PM1BLK_PM1C_SCIEN (BIT0)

Definition at line 516 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1C_SLPEN

#define B_QNC_PM1BLK_PM1C_SLPEN (BIT13)

Definition at line 510 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1C_SLPTP

#define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10)

Definition at line 511 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1E_GLOB

#define B_QNC_PM1BLK_PM1E_GLOB (BIT5)

Definition at line 506 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1E_PWAKED

#define B_QNC_PM1BLK_PM1E_PWAKED (BIT14)

Definition at line 504 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1E_RTC

#define B_QNC_PM1BLK_PM1E_RTC (BIT10)

Definition at line 505 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1S_ALL

#define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)

Definition at line 494 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1S_GLOB

#define B_QNC_PM1BLK_PM1S_GLOB (BIT5)

Definition at line 498 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1S_PCIEWSTS

#define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14)

Definition at line 496 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1S_RTC

#define B_QNC_PM1BLK_PM1S_RTC (BIT10)

Definition at line 497 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1S_TO

#define B_QNC_PM1BLK_PM1S_TO (BIT0)

Definition at line 499 of file QuarkNcSocId.h.

◆ B_QNC_PM1BLK_PM1S_WAKE

#define B_QNC_PM1BLK_PM1S_WAKE (BIT15)

Definition at line 495 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIA_MASK

#define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF

Definition at line 800 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIC_ACS

#define B_QNC_RCRB_SPIC_ACS (BIT2)

Definition at line 796 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIC_COP

#define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4)

Definition at line 794 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIC_DBC

#define B_QNC_RCRB_SPIC_DBC 0x3F00

Definition at line 792 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIC_DC

#define B_QNC_RCRB_SPIC_DC (BIT14)

Definition at line 791 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIC_SCGO

#define B_QNC_RCRB_SPIC_SCGO (BIT1)

Definition at line 797 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIC_SPOP

#define B_QNC_RCRB_SPIC_SPOP (BIT3)

Definition at line 795 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIOPTYPE_ADD_READ

#define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1)

Definition at line 809 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIOPTYPE_ADD_WRITE

#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1)

Definition at line 810 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIOPTYPE_NOADD_READ

#define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0

Definition at line 807 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE

#define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0)

Definition at line 808 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIPBRn_WPE

#define B_QNC_RCRB_SPIPBRn_WPE (BIT31)

Definition at line 819 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIS_BAS

#define B_QNC_RCRB_SPIS_BAS (BIT3)

Definition at line 786 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIS_CDS

#define B_QNC_RCRB_SPIS_CDS (BIT2)

Definition at line 787 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIS_SCIP

#define B_QNC_RCRB_SPIS_SCIP (BIT0)

Definition at line 788 of file QuarkNcSocId.h.

◆ B_QNC_RCRB_SPIS_SCL

#define B_QNC_RCRB_SPIS_SCL (BIT15)

Definition at line 785 of file QuarkNcSocId.h.

◆ B_QNC_SMBUS_BERR

#define B_QNC_SMBUS_BERR (BIT2)

Definition at line 443 of file QuarkNcSocId.h.

◆ B_QNC_SMBUS_BYTE_DONE_STS

#define B_QNC_SMBUS_BYTE_DONE_STS (BIT0)

Definition at line 445 of file QuarkNcSocId.h.

◆ B_QNC_SMBUS_DERR

#define B_QNC_SMBUS_DERR (BIT1)

Definition at line 444 of file QuarkNcSocId.h.

◆ B_QNC_SMBUS_HSTS_ALL

#define B_QNC_SMBUS_HSTS_ALL 0x07

Definition at line 446 of file QuarkNcSocId.h.

◆ B_QNC_SMBUS_START

#define B_QNC_SMBUS_START (BIT4)

Definition at line 434 of file QuarkNcSocId.h.

◆ B_ROM_FUSE_IN_SECURE_SKU

#define B_ROM_FUSE_IN_SECURE_SKU BIT6

Definition at line 326 of file QuarkNcSocId.h.

◆ B_RST_CNT_COLD_RST

#define B_RST_CNT_COLD_RST (BIT3)

Definition at line 665 of file QuarkNcSocId.h.

◆ B_RST_CNT_WARM_RST

#define B_RST_CNT_WARM_RST (BIT1)

Definition at line 666 of file QuarkNcSocId.h.

◆ B_STPDDRCFG_FORCE_RECOVERY

#define B_STPDDRCFG_FORCE_RECOVERY BIT0

Definition at line 324 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_IBGCHOPEN

#define B_TSCGF1_CONFIG_IBGCHOPEN BIT18

Definition at line 336 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_IBGCHOPEN_BP

#define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18

Definition at line 337 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_IBGEN

#define B_TSCGF1_CONFIG_IBGEN BIT17

Definition at line 334 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_IBGEN_BP

#define B_TSCGF1_CONFIG_IBGEN_BP 17

Definition at line 335 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_ISNSCHOPSEL_BP

#define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8

Definition at line 333 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK

#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK

Value:

(BIT12 | BIT11 | BIT10 | BIT9\

| BIT8)

BIT8

#define BIT8

Definition: QuarkNcSocId.h:27

BIT11

#define BIT11

Definition: QuarkNcSocId.h:30

BIT9

#define BIT9

Definition: QuarkNcSocId.h:28

BIT10

#define BIT10

Definition: QuarkNcSocId.h:29

BIT12

#define BIT12

Definition: QuarkNcSocId.h:31

Definition at line 331 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP

#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3

Definition at line 330 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK

#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3)

Definition at line 329 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_ISNSINTERNALVREFEN

#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14

Definition at line 338 of file QuarkNcSocId.h.

◆ B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP

#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14

Definition at line 339 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP

#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0

Definition at line 353 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK

#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF

Definition at line 352 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP

#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8

Definition at line 351 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK

#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8)

Definition at line 350 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG2_ISPARECTRL_BP

#define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24

Definition at line 349 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG2_ISPARECTRL_MASK

#define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000

Definition at line 348 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG_IDSCONTROL_BP

#define B_TSCGF2_CONFIG_IDSCONTROL_BP 0

Definition at line 343 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG_IDSCONTROL_MASK

#define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF

Definition at line 342 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG_IDSTIMING_BP

#define B_TSCGF2_CONFIG_IDSTIMING_BP 16

Definition at line 345 of file QuarkNcSocId.h.

◆ B_TSCGF2_CONFIG_IDSTIMING_MASK

#define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000

Definition at line 344 of file QuarkNcSocId.h.

◆ B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP

#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11

Definition at line 357 of file QuarkNcSocId.h.

◆ B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK

#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP)

Definition at line 358 of file QuarkNcSocId.h.

◆ B_TSCGF3_CONFIG_ITSRST

#define B_TSCGF3_CONFIG_ITSRST BIT0

Definition at line 356 of file QuarkNcSocId.h.

◆ B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP

#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18

Definition at line 181 of file QuarkNcSocId.h.

◆ B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK

#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18)

Definition at line 180 of file QuarkNcSocId.h.

◆ BIT0

#define BIT0 0x00000001

Definition at line 19 of file QuarkNcSocId.h.

◆ BIT1

#define BIT1 0x00000002

Definition at line 20 of file QuarkNcSocId.h.

◆ BIT10

#define BIT10 0x00000400

Definition at line 29 of file QuarkNcSocId.h.

◆ BIT11

#define BIT11 0x00000800

Definition at line 30 of file QuarkNcSocId.h.

◆ BIT12

#define BIT12 0x00001000

Definition at line 31 of file QuarkNcSocId.h.

◆ BIT13

#define BIT13 0x00002000

Definition at line 32 of file QuarkNcSocId.h.

◆ BIT14

#define BIT14 0x00004000

Definition at line 33 of file QuarkNcSocId.h.

◆ BIT15

#define BIT15 0x00008000

Definition at line 34 of file QuarkNcSocId.h.

◆ BIT16

#define BIT16 0x00010000

Definition at line 35 of file QuarkNcSocId.h.

◆ BIT17

#define BIT17 0x00020000

Definition at line 36 of file QuarkNcSocId.h.

◆ BIT18

#define BIT18 0x00040000

Definition at line 37 of file QuarkNcSocId.h.

◆ BIT19

#define BIT19 0x00080000

Definition at line 38 of file QuarkNcSocId.h.

◆ BIT2

#define BIT2 0x00000004

Definition at line 21 of file QuarkNcSocId.h.

◆ BIT20

#define BIT20 0x00100000

Definition at line 39 of file QuarkNcSocId.h.

◆ BIT21

#define BIT21 0x00200000

Definition at line 40 of file QuarkNcSocId.h.

◆ BIT22

#define BIT22 0x00400000

Definition at line 41 of file QuarkNcSocId.h.

◆ BIT23

#define BIT23 0x00800000

Definition at line 42 of file QuarkNcSocId.h.

◆ BIT24

#define BIT24 0x01000000

Definition at line 43 of file QuarkNcSocId.h.

◆ BIT25

#define BIT25 0x02000000

Definition at line 44 of file QuarkNcSocId.h.

◆ BIT26

#define BIT26 0x04000000

Definition at line 45 of file QuarkNcSocId.h.

◆ BIT27

#define BIT27 0x08000000

Definition at line 46 of file QuarkNcSocId.h.

◆ BIT28

#define BIT28 0x10000000

Definition at line 47 of file QuarkNcSocId.h.

◆ BIT29

#define BIT29 0x20000000

Definition at line 48 of file QuarkNcSocId.h.

◆ BIT3

#define BIT3 0x00000008

Definition at line 22 of file QuarkNcSocId.h.

◆ BIT30

#define BIT30 0x40000000

Definition at line 49 of file QuarkNcSocId.h.

◆ BIT31

#define BIT31 0x80000000

Definition at line 50 of file QuarkNcSocId.h.

◆ BIT4

#define BIT4 0x00000010

Definition at line 23 of file QuarkNcSocId.h.

◆ BIT5

#define BIT5 0x00000020

Definition at line 24 of file QuarkNcSocId.h.

◆ BIT6

#define BIT6 0x00000040

Definition at line 25 of file QuarkNcSocId.h.

◆ BIT7

#define BIT7 0x00000080

Definition at line 26 of file QuarkNcSocId.h.

◆ BIT8

#define BIT8 0x00000100

Definition at line 27 of file QuarkNcSocId.h.

◆ BIT9

#define BIT9 0x00000200

Definition at line 28 of file QuarkNcSocId.h.

◆ BLOCK_DISABLE_PG

#define BLOCK_DISABLE_PG (1 << 29)

Definition at line 230 of file QuarkNcSocId.h.

◆ BLOCK_ENABLE_PG

#define BLOCK_ENABLE_PG (1 << 28)

Definition at line 229 of file QuarkNcSocId.h.

◆ CPU0_NON_SMM

#define CPU0_NON_SMM BIT0

Definition at line 261 of file QuarkNcSocId.h.

◆ CPU_SNOOP

#define CPU_SNOOP BIT30

Definition at line 259 of file QuarkNcSocId.h.

◆ DRAM_NON_HOST_RQ_LIMIT_BP

#define DRAM_NON_HOST_RQ_LIMIT_BP 0

Definition at line 236 of file QuarkNcSocId.h.

◆ DRAM_NON_HOST_RQ_LIMIT_MASK

#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP)

Definition at line 237 of file QuarkNcSocId.h.

◆ EnableIMRInt

#define EnableIMRInt BIT31

Definition at line 232 of file QuarkNcSocId.h.

◆ EnableSMMInt

#define EnableSMMInt BIT31

Definition at line 234 of file QuarkNcSocId.h.

◆ ESEG_RD_DRAM

#define ESEG_RD_DRAM (BIT1)

Definition at line 271 of file QuarkNcSocId.h.

◆ FSEG_RD_DRAM

#define FSEG_RD_DRAM (BIT2)

Definition at line 269 of file QuarkNcSocId.h.

◆ HLEGACY_SMI_PIN_VALUE

#define HLEGACY_SMI_PIN_VALUE BIT12

Definition at line 287 of file QuarkNcSocId.h.

◆ HMBOUND_LOCK

#define HMBOUND_LOCK BIT0

Definition at line 285 of file QuarkNcSocId.h.

◆ HMBOUND_MASK

#define HMBOUND_MASK 0x0FFFFF000

Definition at line 284 of file QuarkNcSocId.h.

◆ IMR_EN

#define IMR_EN BIT30

Definition at line 250 of file QuarkNcSocId.h.

◆ IMR_LOCK

#define IMR_LOCK BIT31

Definition at line 249 of file QuarkNcSocId.h.

◆ IMRH_MASK

#define IMRH_MASK 0x00FFFFFC

Definition at line 254 of file QuarkNcSocId.h.

◆ IMRH_RESET

#define IMRH_RESET 0x00000000

Definition at line 255 of file QuarkNcSocId.h.

◆ IMRL_MASK

#define IMRL_MASK 0x00FFFFFC

Definition at line 251 of file QuarkNcSocId.h.

◆ IMRL_RESET

#define IMRL_RESET 0x00000000

Definition at line 252 of file QuarkNcSocId.h.

◆ IMRX_ALL_ACCESS

#define IMRX_ALL_ACCESS 0xFFFFFFFF

Definition at line 258 of file QuarkNcSocId.h.

◆ IOAPIC_BASE

#define IOAPIC_BASE 0xFEC00000

Definition at line 774 of file QuarkNcSocId.h.

◆ IOAPIC_SIZE

#define IOAPIC_SIZE 0x1000

Definition at line 775 of file QuarkNcSocId.h.

◆ LShift16

#define LShift16 ( value ) (value << 16)

Definition at line 101 of file QuarkNcSocId.h.

◆ MAX_PCI_EXPRESS_ROOT_PORTS

#define MAX_PCI_EXPRESS_ROOT_PORTS 2

Definition at line 683 of file QuarkNcSocId.h.

◆ MC_BUS

#define MC_BUS PCI_BUS_NUMBER_QNC

Definition at line 60 of file QuarkNcSocId.h.

◆ MC_DEV

#define MC_DEV 0x00

Definition at line 61 of file QuarkNcSocId.h.

◆ MC_FUN

#define MC_FUN 0x00

Definition at line 62 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_GPE0E_THRM

#define N_QNC_GPE0BLK_GPE0E_THRM 12

Definition at line 537 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_GPE0S_THRM

#define N_QNC_GPE0BLK_GPE0S_THRM 12

Definition at line 530 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIE_APM

#define N_QNC_GPE0BLK_SMIE_APM 4

Definition at line 547 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIE_ESMI

#define N_QNC_GPE0BLK_SMIE_ESMI 8

Definition at line 546 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIE_GPIO

#define N_QNC_GPE0BLK_SMIE_GPIO 9

Definition at line 545 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIE_SLP

#define N_QNC_GPE0BLK_SMIE_SLP 2

Definition at line 549 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIE_SPI

#define N_QNC_GPE0BLK_SMIE_SPI 3

Definition at line 548 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIE_SWT

#define N_QNC_GPE0BLK_SMIE_SWT 1

Definition at line 550 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIS_APM

#define N_QNC_GPE0BLK_SMIS_APM 4

Definition at line 562 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIS_GPIO

#define N_QNC_GPE0BLK_SMIS_GPIO 9

Definition at line 561 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIS_SLP

#define N_QNC_GPE0BLK_SMIS_SLP 2

Definition at line 564 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIS_SPI

#define N_QNC_GPE0BLK_SMIS_SPI 3

Definition at line 563 of file QuarkNcSocId.h.

◆ N_QNC_GPE0BLK_SMIS_SWT

#define N_QNC_GPE0BLK_SMIS_SWT 1

Definition at line 565 of file QuarkNcSocId.h.

◆ N_QNC_LPC_BIOS_CNTL_BIOSWE

#define N_QNC_LPC_BIOS_CNTL_BIOSWE 0

Definition at line 618 of file QuarkNcSocId.h.

◆ N_QNC_LPC_BIOS_CNTL_BLE

#define N_QNC_LPC_BIOS_CNTL_BLE 1

Definition at line 617 of file QuarkNcSocId.h.

◆ N_QNC_PM1BLK_PM1E_RTC

#define N_QNC_PM1BLK_PM1E_RTC 10

Definition at line 507 of file QuarkNcSocId.h.

◆ N_QNC_PM1BLK_PM1S_RTC

#define N_QNC_PM1BLK_PM1S_RTC 10

Definition at line 500 of file QuarkNcSocId.h.

◆ NON_HOST_SMM_RD_OPEN

#define NON_HOST_SMM_RD_OPEN (BIT17)

Definition at line 275 of file QuarkNcSocId.h.

◆ NON_HOST_SMM_WR_OPEN

#define NON_HOST_SMM_WR_OPEN (BIT18)

Definition at line 274 of file QuarkNcSocId.h.

◆ OCFGPIMIXLOAD_1_0

#define OCFGPIMIXLOAD_1_0 BIT6

Definition at line 404 of file QuarkNcSocId.h.

◆ OCFGPIMIXLOAD_1_0_MASK

#define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F

Definition at line 405 of file QuarkNcSocId.h.

◆ OPTIONS_1_DMA_DISABLE

#define OPTIONS_1_DMA_DISABLE (BIT0)

Definition at line 177 of file QuarkNcSocId.h.

◆ PCI_BUS_NUMBER_QNC

#define PCI_BUS_NUMBER_QNC 0x00

Definition at line 412 of file QuarkNcSocId.h.

◆ PCI_DEVICE_NUMBER_PCIE_ROOTPORT

#define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23

Definition at line 679 of file QuarkNcSocId.h.

◆ PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0

#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20

Definition at line 672 of file QuarkNcSocId.h.

◆ PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1

#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21

Definition at line 673 of file QuarkNcSocId.h.

◆ PCI_DEVICE_NUMBER_QNC_LPC

#define PCI_DEVICE_NUMBER_QNC_LPC 31

Definition at line 417 of file QuarkNcSocId.h.

◆ PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0

#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0

Definition at line 680 of file QuarkNcSocId.h.

◆ PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1

#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1

Definition at line 681 of file QuarkNcSocId.h.

◆ PCI_FUNCTION_NUMBER_QNC_IOSF2AHB

#define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0

Definition at line 674 of file QuarkNcSocId.h.

◆ PCI_FUNCTION_NUMBER_QNC_LPC

#define PCI_FUNCTION_NUMBER_QNC_LPC 0

Definition at line 418 of file QuarkNcSocId.h.

◆ PCIE_CAP_EXT_HEARDER_OFFSET

#define PCIE_CAP_EXT_HEARDER_OFFSET 0x100

Definition at line 689 of file QuarkNcSocId.h.

◆ PCIE_CAPID

#define PCIE_CAPID 0x10

Definition at line 688 of file QuarkNcSocId.h.

◆ PCIE_DEV_CAP_OFFSET

#define PCIE_DEV_CAP_OFFSET 0x04

Definition at line 690 of file QuarkNcSocId.h.

◆ PCIE_LINK_CAP_OFFSET

#define PCIE_LINK_CAP_OFFSET 0x0C

Definition at line 691 of file QuarkNcSocId.h.

◆ PCIE_LINK_CNT_OFFSET

#define PCIE_LINK_CNT_OFFSET 0x10

Definition at line 692 of file QuarkNcSocId.h.

◆ PCIE_LINK_STS_OFFSET

#define PCIE_LINK_STS_OFFSET 0x12

Definition at line 693 of file QuarkNcSocId.h.

◆ PCIE_SLOT_CAP_OFFSET

#define PCIE_SLOT_CAP_OFFSET 0x14

Definition at line 694 of file QuarkNcSocId.h.

◆ QNC_ACCESS_PORT_MCR

#define QNC_ACCESS_PORT_MCR 0xD0

Definition at line 77 of file QuarkNcSocId.h.

◆ QNC_ACCESS_PORT_MDR

#define QNC_ACCESS_PORT_MDR 0xD4

Definition at line 85 of file QuarkNcSocId.h.

◆ QNC_ACCESS_PORT_MEA

#define QNC_ACCESS_PORT_MEA 0xD8

Definition at line 90 of file QuarkNcSocId.h.

◆ QNC_MC_REV_ID_A0

#define QNC_MC_REV_ID_A0 0x00

Definition at line 67 of file QuarkNcSocId.h.

◆ QNC_MCR_BYTE_ENABLES

#define QNC_MCR_BYTE_ENABLES 0x000000f0

Definition at line 80 of file QuarkNcSocId.h.

◆ QNC_MCR_MASK

#define QNC_MCR_MASK 0x000000ff

Definition at line 79 of file QuarkNcSocId.h.

◆ QNC_MCR_OP_OFFSET

#define QNC_MCR_OP_OFFSET 24

Definition at line 93 of file QuarkNcSocId.h.

◆ QNC_MCR_PORT_OFFSET

#define QNC_MCR_PORT_OFFSET 16

Definition at line 94 of file QuarkNcSocId.h.

◆ QNC_MCR_REG_OFFSET

#define QNC_MCR_REG_OFFSET 8

Definition at line 95 of file QuarkNcSocId.h.

◆ QNC_MEA_MASK

#define QNC_MEA_MASK 0xffffff00

Definition at line 91 of file QuarkNcSocId.h.

◆ QNC_MSG_FSBIC_REG_HMISC

#define QNC_MSG_FSBIC_REG_HMISC 0x03

Definition at line 266 of file QuarkNcSocId.h.

◆ QNC_MSG_FSBIC_REG_HSMMC

#define QNC_MSG_FSBIC_REG_HSMMC 0x04

Definition at line 273 of file QuarkNcSocId.h.

◆ QNC_MSG_TMPM_REG_PMBA

#define QNC_MSG_TMPM_REG_PMBA 0x70

Definition at line 170 of file QuarkNcSocId.h.

◆ QNC_NUMBER_PIRQS

#define QNC_NUMBER_PIRQS 8

Definition at line 579 of file QuarkNcSocId.h.

◆ QUARK2_MC_DEVICE_ID

#define QUARK2_MC_DEVICE_ID 0x12C0

Definition at line 66 of file QuarkNcSocId.h.

◆ QUARK_ALT_OPCODE_READ

#define QUARK_ALT_OPCODE_READ 0x06

Definition at line 112 of file QuarkNcSocId.h.

◆ QUARK_ALT_OPCODE_WRITE

#define QUARK_ALT_OPCODE_WRITE 0x07

Definition at line 113 of file QuarkNcSocId.h.

◆ QUARK_DRAM_BASE_ADDR_READY

#define QUARK_DRAM_BASE_ADDR_READY 0x78

Definition at line 121 of file QuarkNcSocId.h.

◆ QUARK_ECC_SCRUB_PAUSE

#define QUARK_ECC_SCRUB_PAUSE 0xC3

Definition at line 125 of file QuarkNcSocId.h.

◆ QUARK_ECC_SCRUB_RESUME

#define QUARK_ECC_SCRUB_RESUME 0xC2

Definition at line 124 of file QuarkNcSocId.h.

◆ QUARK_ICLK_MUXTOP

#define QUARK_ICLK_MUXTOP 0x0140

Definition at line 388 of file QuarkNcSocId.h.

◆ QUARK_ICLK_REF2_DBUFF0

#define QUARK_ICLK_REF2_DBUFF0 0x2000

Definition at line 397 of file QuarkNcSocId.h.

◆ QUARK_ICLK_SB_PORT_ID

#define QUARK_ICLK_SB_PORT_ID 0x32

Definition at line 140 of file QuarkNcSocId.h.

◆ QUARK_ICLK_SSC1

#define QUARK_ICLK_SSC1 0x0314

Definition at line 394 of file QuarkNcSocId.h.

◆ QUARK_ICLK_SSC2

#define QUARK_ICLK_SSC2 0x0414

Definition at line 395 of file QuarkNcSocId.h.

◆ QUARK_ICLK_SSC3

#define QUARK_ICLK_SSC3 0x0514

Definition at line 396 of file QuarkNcSocId.h.

◆ QUARK_MC_DEVICE_ID

#define QUARK_MC_DEVICE_ID 0x0958

Definition at line 65 of file QuarkNcSocId.h.

◆ QUARK_MC_VENDOR_ID

#define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID

Definition at line 64 of file QuarkNcSocId.h.

◆ QUARK_NC_ECC_SCRUB_CONFIG_REG

#define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50

Definition at line 203 of file QuarkNcSocId.h.

◆ QUARK_NC_ECC_SCRUB_END_MEM_REG

#define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77

Definition at line 212 of file QuarkNcSocId.h.

◆ QUARK_NC_ECC_SCRUB_NEXT_READ_REG

#define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C

Definition at line 213 of file QuarkNcSocId.h.

◆ QUARK_NC_ECC_SCRUB_START_MEM_REG

#define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76

Definition at line 211 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_HLEGACY_REG

#define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A

Definition at line 286 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_HMBOUND_REG

#define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08

Definition at line 283 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40

Definition at line 288 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41

Definition at line 289 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A

Definition at line 303 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C

Definition at line 305 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E

Definition at line 307 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60

Definition at line 309 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62

Definition at line 311 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64

Definition at line 313 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66

Definition at line 315 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68

Definition at line 317 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B

Definition at line 304 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D

Definition at line 306 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F

Definition at line 308 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61

Definition at line 310 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63

Definition at line 312 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65

Definition at line 314 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67

Definition at line 316 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69

Definition at line 318 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58

Definition at line 301 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK

#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59

Definition at line 302 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44

Definition at line 291 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46

Definition at line 292 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48

Definition at line 293 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A

Definition at line 294 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C

Definition at line 295 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E

Definition at line 296 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50

Definition at line 297 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52

Definition at line 298 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54

Definition at line 299 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56

Definition at line 300 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000

#define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42

Definition at line 290 of file QuarkNcSocId.h.

◆ QUARK_NC_HOST_BRIDGE_SB_PORT_ID

#define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03

Definition at line 133 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_ARBITER_REG_ASTATUS

#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21

Definition at line 146 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_ARBITER_SB_PORT_ID

#define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00

Definition at line 131 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT

#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70

Definition at line 164 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID

#define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01

Definition at line 132 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_BIMRVCTL

#define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19

Definition at line 231 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_BSMMVCTL

#define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C

Definition at line 233 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_BTHCTRL

#define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20

Definition at line 235 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK

#define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82

Definition at line 228 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMR0

#define QUARK_NC_MEMORY_MANAGER_IMR0 0x40

Definition at line 240 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMR1

#define QUARK_NC_MEMORY_MANAGER_IMR1 0x44

Definition at line 241 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMR2

#define QUARK_NC_MEMORY_MANAGER_IMR2 0x48

Definition at line 242 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMR3

#define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C

Definition at line 243 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMR4

#define QUARK_NC_MEMORY_MANAGER_IMR4 0x50

Definition at line 244 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMR5

#define QUARK_NC_MEMORY_MANAGER_IMR5 0x54

Definition at line 245 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMR6

#define QUARK_NC_MEMORY_MANAGER_IMR6 0x58

Definition at line 246 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMR7

#define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C

Definition at line 247 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMRXH

#define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01

Definition at line 253 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMRXL

#define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00

Definition at line 248 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMRXRM

#define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02

Definition at line 256 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_IMRXWM

#define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03

Definition at line 257 of file QuarkNcSocId.h.

◆ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID

#define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05

Definition at line 135 of file QuarkNcSocId.h.

◆ QUARK_NC_RMU_REG_CONFIG

#define QUARK_NC_RMU_REG_CONFIG 0x71

Definition at line 172 of file QuarkNcSocId.h.

◆ QUARK_NC_RMU_REG_OPTIONS_1

#define QUARK_NC_RMU_REG_OPTIONS_1 0x72

Definition at line 176 of file QuarkNcSocId.h.

◆ QUARK_NC_RMU_REG_TS_MODE

#define QUARK_NC_RMU_REG_TS_MODE 0xB0

Definition at line 190 of file QuarkNcSocId.h.

◆ QUARK_NC_RMU_REG_TS_TRIP

#define QUARK_NC_RMU_REG_TS_TRIP 0xB2

Definition at line 192 of file QuarkNcSocId.h.

◆ QUARK_NC_RMU_REG_WDT_CONTROL

#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74

Definition at line 179 of file QuarkNcSocId.h.

◆ QUARK_NC_RMU_SB_PORT_ID

#define QUARK_NC_RMU_SB_PORT_ID 0x04

Definition at line 134 of file QuarkNcSocId.h.

◆ QUARK_NC_TOTAL_IMR_SET

#define QUARK_NC_TOTAL_IMR_SET 0x8

Definition at line 239 of file QuarkNcSocId.h.

◆ QUARK_OPCODE_IO_READ

#define QUARK_OPCODE_IO_READ 0x02

Definition at line 118 of file QuarkNcSocId.h.

◆ QUARK_OPCODE_IO_WRITE

#define QUARK_OPCODE_IO_WRITE 0x03

Definition at line 119 of file QuarkNcSocId.h.

◆ QUARK_OPCODE_READ

#define QUARK_OPCODE_READ 0x10

Definition at line 106 of file QuarkNcSocId.h.

◆ QUARK_OPCODE_WRITE

#define QUARK_OPCODE_WRITE 0x11

Definition at line 107 of file QuarkNcSocId.h.

◆ QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0

#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080

Definition at line 402 of file QuarkNcSocId.h.

◆ QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1

#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180

Definition at line 403 of file QuarkNcSocId.h.

◆ QUARK_SC_PCIE_AFE_SB_PORT_ID

#define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16

Definition at line 137 of file QuarkNcSocId.h.

◆ QUARK_SC_USB_AFE_SB_PORT_ID

#define QUARK_SC_USB_AFE_SB_PORT_ID 0x14

Definition at line 136 of file QuarkNcSocId.h.

◆ QUARK_SCSS_CRU_SB_PORT_ID

#define QUARK_SCSS_CRU_SB_PORT_ID 0x34

Definition at line 141 of file QuarkNcSocId.h.

◆ QUARK_SCSS_FUSE_SB_PORT_ID

#define QUARK_SCSS_FUSE_SB_PORT_ID 0x33

Definition at line 139 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW

#define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51

Definition at line 370 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_SB_PORT_ID

#define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31

Definition at line 138 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG [1/2]

#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36

Definition at line 368 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG [2/2]

#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36

Definition at line 368 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE

#define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25

Definition at line 325 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_STPDDRCFG

#define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00

Definition at line 323 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG

#define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31

Definition at line 328 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG

#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32

Definition at line 341 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2

#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33

Definition at line 347 of file QuarkNcSocId.h.

◆ QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG

#define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34

Definition at line 355 of file QuarkNcSocId.h.

◆ QUARK_V_LPC_DEVICE_ID_0

#define QUARK_V_LPC_DEVICE_ID_0 0x095E

Definition at line 423 of file QuarkNcSocId.h.

◆ R_APM_CNT

#define R_APM_CNT 0xB2

Definition at line 659 of file QuarkNcSocId.h.

◆ R_EFI_PCI_SVID

#define R_EFI_PCI_SVID 0x2C

Definition at line 769 of file QuarkNcSocId.h.

◆ R_QNC_GPE0BLK_GPE0E

#define R_QNC_GPE0BLK_GPE0E 0x04

Definition at line 532 of file QuarkNcSocId.h.

◆ R_QNC_GPE0BLK_GPE0S

#define R_QNC_GPE0BLK_GPE0S 0x00

Definition at line 524 of file QuarkNcSocId.h.

◆ R_QNC_GPE0BLK_PMCW

#define R_QNC_GPE0BLK_PMCW 0x28

Definition at line 567 of file QuarkNcSocId.h.

◆ R_QNC_GPE0BLK_PMSW

#define R_QNC_GPE0BLK_PMSW 0x2C

Definition at line 570 of file QuarkNcSocId.h.

◆ R_QNC_GPE0BLK_SMIE

#define R_QNC_GPE0BLK_SMIE 0x10

Definition at line 539 of file QuarkNcSocId.h.

◆ R_QNC_GPE0BLK_SMIS

#define R_QNC_GPE0BLK_SMIS 0x14

Definition at line 552 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_CGEN_CORE_WELL

#define R_QNC_GPIO_CGEN_CORE_WELL 0x00

Definition at line 467 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_CGGPE_CORE_WELL

#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14

Definition at line 472 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_CGIO_CORE_WELL

#define R_QNC_GPIO_CGIO_CORE_WELL 0x04

Definition at line 468 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_CGLVL_CORE_WELL

#define R_QNC_GPIO_CGLVL_CORE_WELL 0x08

Definition at line 469 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_CGSMI_CORE_WELL

#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18

Definition at line 473 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_CGTNE_CORE_WELL

#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10

Definition at line 471 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_CGTPE_CORE_WELL

#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C

Definition at line 470 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_CGTS_CORE_WELL

#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C

Definition at line 474 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_CNMIEN_CORE_WELL

#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40

Definition at line 483 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_RGEN_RESUME_WELL

#define R_QNC_GPIO_RGEN_RESUME_WELL 0x20

Definition at line 475 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_RGGPE_RESUME_WELL

#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34

Definition at line 480 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_RGIO_RESUME_WELL

#define R_QNC_GPIO_RGIO_RESUME_WELL 0x24

Definition at line 476 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_RGLVL_RESUME_WELL

#define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28

Definition at line 477 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_RGSMI_RESUME_WELL

#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38

Definition at line 481 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_RGTNE_RESUME_WELL

#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30

Definition at line 479 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_RGTPE_RESUME_WELL

#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C

Definition at line 478 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_RGTS_RESUME_WELL

#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C

Definition at line 482 of file QuarkNcSocId.h.

◆ R_QNC_GPIO_RNMIEN_RESUME_WELL

#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44

Definition at line 484 of file QuarkNcSocId.h.

◆ R_QNC_LPC_ACTL

#define R_QNC_LPC_ACTL 0x58

Definition at line 573 of file QuarkNcSocId.h.

◆ R_QNC_LPC_BIOS_CNTL

#define R_QNC_LPC_BIOS_CNTL 0xD8

Definition at line 610 of file QuarkNcSocId.h.

◆ R_QNC_LPC_DEVICE_ID

#define R_QNC_LPC_DEVICE_ID 0x02

Definition at line 422 of file QuarkNcSocId.h.

◆ R_QNC_LPC_FWH_BIOS_DEC

#define R_QNC_LPC_FWH_BIOS_DEC 0xD4

Definition at line 600 of file QuarkNcSocId.h.

◆ R_QNC_LPC_GBA_BASE

#define R_QNC_LPC_GBA_BASE 0x44

Definition at line 461 of file QuarkNcSocId.h.

◆ R_QNC_LPC_GPE0BLK

#define R_QNC_LPC_GPE0BLK 0x4C

Definition at line 520 of file QuarkNcSocId.h.

◆ R_QNC_LPC_PIRQA_ROUT

#define R_QNC_LPC_PIRQA_ROUT 0x60

Definition at line 580 of file QuarkNcSocId.h.

◆ R_QNC_LPC_PIRQB_ROUT

#define R_QNC_LPC_PIRQB_ROUT 0x61

Definition at line 581 of file QuarkNcSocId.h.

◆ R_QNC_LPC_PIRQC_ROUT

#define R_QNC_LPC_PIRQC_ROUT 0x62

Definition at line 582 of file QuarkNcSocId.h.

◆ R_QNC_LPC_PIRQD_ROUT

#define R_QNC_LPC_PIRQD_ROUT 0x63

Definition at line 583 of file QuarkNcSocId.h.

◆ R_QNC_LPC_PIRQE_ROUT

#define R_QNC_LPC_PIRQE_ROUT 0x64

Definition at line 584 of file QuarkNcSocId.h.

◆ R_QNC_LPC_PIRQF_ROUT

#define R_QNC_LPC_PIRQF_ROUT 0x65

Definition at line 585 of file QuarkNcSocId.h.

◆ R_QNC_LPC_PIRQG_ROUT

#define R_QNC_LPC_PIRQG_ROUT 0x66

Definition at line 586 of file QuarkNcSocId.h.

◆ R_QNC_LPC_PIRQH_ROUT

#define R_QNC_LPC_PIRQH_ROUT 0x67

Definition at line 587 of file QuarkNcSocId.h.

◆ R_QNC_LPC_PM1BLK

#define R_QNC_LPC_PM1BLK 0x48

Definition at line 486 of file QuarkNcSocId.h.

◆ R_QNC_LPC_RCBA

#define R_QNC_LPC_RCBA 0xF0

Definition at line 620 of file QuarkNcSocId.h.

◆ R_QNC_LPC_REV_ID

#define R_QNC_LPC_REV_ID 0x08

Definition at line 424 of file QuarkNcSocId.h.

◆ R_QNC_LPC_SMBUS_BASE

#define R_QNC_LPC_SMBUS_BASE 0x40

Definition at line 426 of file QuarkNcSocId.h.

◆ R_QNC_LPC_VENDOR_ID

#define R_QNC_LPC_VENDOR_ID 0x00

Definition at line 420 of file QuarkNcSocId.h.

◆ R_QNC_LPC_WDT_WDTCR

#define R_QNC_LPC_WDT_WDTCR 0x10

Definition at line 596 of file QuarkNcSocId.h.

◆ R_QNC_LPC_WDT_WDTLR

#define R_QNC_LPC_WDT_WDTLR 0x18

Definition at line 597 of file QuarkNcSocId.h.

◆ R_QNC_LPC_WDTBA

#define R_QNC_LPC_WDTBA 0x84

Definition at line 594 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_BNUM

#define R_QNC_PCIE_BNUM 0x18

Definition at line 685 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_CAP_PTR

#define R_QNC_PCIE_CAP_PTR 0x34

Definition at line 686 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_CCFG

#define R_QNC_PCIE_CCFG 0xD0

Definition at line 745 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_DCAP

#define R_QNC_PCIE_DCAP 0x44

Definition at line 698 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_DCTL

#define R_QNC_PCIE_DCTL 0x48

Definition at line 703 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_IOSFSBCTL

#define R_QNC_PCIE_IOSFSBCTL 0xF6

Definition at line 758 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_LCAP

#define R_QNC_PCIE_LCAP 0x4C

Definition at line 709 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_LCTL

#define R_QNC_PCIE_LCTL 0x50

Definition at line 717 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_LSTS

#define R_QNC_PCIE_LSTS 0x52

Definition at line 720 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_MPC

#define R_QNC_PCIE_MPC 0xD8

Definition at line 752 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_MPC2

#define R_QNC_PCIE_MPC2 0xD4

Definition at line 750 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_RCTL

#define R_QNC_PCIE_RCTL 0x5C

Definition at line 738 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_SLCAP

#define R_QNC_PCIE_SLCAP 0x54

Definition at line 723 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_SLCTL

#define R_QNC_PCIE_SLCTL 0x58

Definition at line 730 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_SLSTS

#define R_QNC_PCIE_SLSTS 0x5A

Definition at line 734 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_SVID

#define R_QNC_PCIE_SVID 0x94

Definition at line 744 of file QuarkNcSocId.h.

◆ R_QNC_PCIE_XCAP

#define R_QNC_PCIE_XCAP 0x42

Definition at line 696 of file QuarkNcSocId.h.

◆ R_QNC_PM1BLK_PM1C

#define R_QNC_PM1BLK_PM1C 0x04

Definition at line 509 of file QuarkNcSocId.h.

◆ R_QNC_PM1BLK_PM1E

#define R_QNC_PM1BLK_PM1E 0x02

Definition at line 502 of file QuarkNcSocId.h.

◆ R_QNC_PM1BLK_PM1S

#define R_QNC_PM1BLK_PM1S 0x00

Definition at line 492 of file QuarkNcSocId.h.

◆ R_QNC_PM1BLK_PM1T

#define R_QNC_PM1BLK_PM1T 0x08

Definition at line 518 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_AGENT0IR

#define R_QNC_RCRB_AGENT0IR 0x3140

Definition at line 821 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_AGENT1IR

#define R_QNC_RCRB_AGENT1IR 0x3142

Definition at line 822 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_AGENT2IR

#define R_QNC_RCRB_AGENT2IR 0x3144

Definition at line 823 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_AGENT3IR

#define R_QNC_RCRB_AGENT3IR 0x3146

Definition at line 824 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIA

#define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04)

Definition at line 799 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIBASE

#define R_QNC_RCRB_SPIBASE 0x3020

Definition at line 783 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIC

#define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02)

Definition at line 790 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPID0

#define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08)

Definition at line 801 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIOPMENU

#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58)

Definition at line 812 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIOPTYPE

#define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56)

Definition at line 805 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIPBR0

#define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60)

Definition at line 815 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIPBR1

#define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64)

Definition at line 816 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIPBR2

#define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68)

Definition at line 817 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIPREOP

#define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54)

Definition at line 803 of file QuarkNcSocId.h.

◆ R_QNC_RCRB_SPIS

#define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00)

Definition at line 784 of file QuarkNcSocId.h.

◆ R_QNC_SMBUS_HBD

#define R_QNC_SMBUS_HBD 0x20

Definition at line 458 of file QuarkNcSocId.h.

◆ R_QNC_SMBUS_HCLK

#define R_QNC_SMBUS_HCLK 0x02

Definition at line 448 of file QuarkNcSocId.h.

◆ R_QNC_SMBUS_HCMD

#define R_QNC_SMBUS_HCMD 0x05

Definition at line 455 of file QuarkNcSocId.h.

◆ R_QNC_SMBUS_HCTL

#define R_QNC_SMBUS_HCTL 0x00

Definition at line 433 of file QuarkNcSocId.h.

◆ R_QNC_SMBUS_HD0

#define R_QNC_SMBUS_HD0 0x06

Definition at line 456 of file QuarkNcSocId.h.

◆ R_QNC_SMBUS_HD1

#define R_QNC_SMBUS_HD1 0x07

Definition at line 457 of file QuarkNcSocId.h.

◆ R_QNC_SMBUS_HSTS

#define R_QNC_SMBUS_HSTS 0x01

Definition at line 442 of file QuarkNcSocId.h.

◆ R_QNC_SMBUS_TSA

#define R_QNC_SMBUS_TSA 0x04

Definition at line 451 of file QuarkNcSocId.h.

◆ RMU

#define RMU BIT29

Definition at line 260 of file QuarkNcSocId.h.

◆ RST_CNT

#define RST_CNT 0xCF9

Definition at line 664 of file QuarkNcSocId.h.

◆ S_QNC_GPE0BLK_GPE0E

#define S_QNC_GPE0BLK_GPE0E 4

Definition at line 533 of file QuarkNcSocId.h.

◆ S_QNC_GPE0BLK_GPE0S

#define S_QNC_GPE0BLK_GPE0S 4

Definition at line 525 of file QuarkNcSocId.h.

◆ S_QNC_GPE0BLK_SMIE

#define S_QNC_GPE0BLK_SMIE 4

Definition at line 540 of file QuarkNcSocId.h.

◆ S_QNC_GPE0BLK_SMIS

#define S_QNC_GPE0BLK_SMIS 4

Definition at line 553 of file QuarkNcSocId.h.

◆ S_QNC_LPC_BIOS_CNTL

#define S_QNC_LPC_BIOS_CNTL 4

Definition at line 611 of file QuarkNcSocId.h.

◆ S_QNC_PM1BLK_PM1E

#define S_QNC_PM1BLK_PM1E 2

Definition at line 503 of file QuarkNcSocId.h.

◆ S_QNC_PM1BLK_PM1S

#define S_QNC_PM1BLK_PM1S 2

Definition at line 493 of file QuarkNcSocId.h.

◆ SCRUB_CFG_ACTIVE

#define SCRUB_CFG_ACTIVE (BIT13)

Definition at line 208 of file QuarkNcSocId.h.

◆ SCRUB_CFG_BLOCKSIZE_MASK

#define SCRUB_CFG_BLOCKSIZE_MASK 0x1F

Definition at line 207 of file QuarkNcSocId.h.

◆ SCRUB_CFG_BLOCKSIZE_SHIFT

#define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08

Definition at line 206 of file QuarkNcSocId.h.

◆ SCRUB_CFG_INTERVAL_MASK

#define SCRUB_CFG_INTERVAL_MASK 0xFF

Definition at line 205 of file QuarkNcSocId.h.

◆ SCRUB_CFG_INTERVAL_SHIFT

#define SCRUB_CFG_INTERVAL_SHIFT 0x00

Definition at line 204 of file QuarkNcSocId.h.

◆ SCRUB_CFG_INVALID

#define SCRUB_CFG_INVALID 0x00000FFF

Definition at line 209 of file QuarkNcSocId.h.

◆ SCRUB_PAUSE_MSG

#define SCRUB_PAUSE_MSG ( )

Value:

        ((UINT32)( \
        (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \
        (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
        0xF0))

Definition at line 220 of file QuarkNcSocId.h.

◆ SCRUB_RESUME_MSG

#define SCRUB_RESUME_MSG ( )

Value:

        ((UINT32)( \
        (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \
        (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
        0xF0))

Definition at line 215 of file QuarkNcSocId.h.

◆ SMI_EN

#define SMI_EN (BIT19)

Definition at line 267 of file QuarkNcSocId.h.

◆ SMM_CODE_RD_OPEN

#define SMM_CODE_RD_OPEN (BIT16)

Definition at line 276 of file QuarkNcSocId.h.

◆ SMM_CTL_EN

#define SMM_CTL_EN (BIT3)

Definition at line 277 of file QuarkNcSocId.h.

◆ SMM_END_MASK

#define SMM_END_MASK 0xFFF00000

Definition at line 282 of file QuarkNcSocId.h.

◆ SMM_LOCKED

#define SMM_LOCKED (BIT0)

Definition at line 280 of file QuarkNcSocId.h.

◆ SMM_READ_OPEN

#define SMM_READ_OPEN (BIT1)

Definition at line 279 of file QuarkNcSocId.h.

◆ SMM_START_MASK

#define SMM_START_MASK 0x0000FFF0

Definition at line 281 of file QuarkNcSocId.h.

◆ SMM_WRITE_OPEN

#define SMM_WRITE_OPEN (BIT2)

Definition at line 278 of file QuarkNcSocId.h.

◆ SOCCLKEN_CONFIG_BB_RST_B

#define SOCCLKEN_CONFIG_BB_RST_B BIT16

Definition at line 366 of file QuarkNcSocId.h.

◆ SOCCLKEN_CONFIG_PHY_I_CMNRESET_L

#define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19

Definition at line 363 of file QuarkNcSocId.h.

◆ SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L

#define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20

Definition at line 362 of file QuarkNcSocId.h.

◆ SOCCLKEN_CONFIG_SBI_BB_RST_B

#define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18

Definition at line 364 of file QuarkNcSocId.h.

◆ SOCCLKEN_CONFIG_SBI_RST_100_CORE_B

#define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17

Definition at line 365 of file QuarkNcSocId.h.

◆ TS_CAT_TRIP_CLEAR_THOLD_BP

#define TS_CAT_TRIP_CLEAR_THOLD_BP 16

Definition at line 196 of file QuarkNcSocId.h.

◆ TS_CAT_TRIP_CLEAR_THOLD_MASK

#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP)

Definition at line 197 of file QuarkNcSocId.h.

◆ TS_CAT_TRIP_SET_THOLD_BP

#define TS_CAT_TRIP_SET_THOLD_BP 0

Definition at line 200 of file QuarkNcSocId.h.

◆ TS_CAT_TRIP_SET_THOLD_MASK

#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP)

Definition at line 201 of file QuarkNcSocId.h.

◆ TS_ENABLE

#define TS_ENABLE (BIT15)

Definition at line 191 of file QuarkNcSocId.h.

◆ TS_HOT_TRIP_CLEAR_THOLD_BP

#define TS_HOT_TRIP_CLEAR_THOLD_BP 24

Definition at line 194 of file QuarkNcSocId.h.

◆ TS_HOT_TRIP_CLEAR_THOLD_MASK

#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP)

Definition at line 195 of file QuarkNcSocId.h.

◆ TS_HOT_TRIP_SET_THOLD_BP

#define TS_HOT_TRIP_SET_THOLD_BP 8

Definition at line 198 of file QuarkNcSocId.h.

◆ TS_HOT_TRIP_SET_THOLD_MASK

#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP)

Definition at line 199 of file QuarkNcSocId.h.

◆ TS_LOCK_AUX_TRIP_PT_REGS_ENABLE

#define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6)

Definition at line 173 of file QuarkNcSocId.h.

◆ TS_LOCK_THRM_CTRL_REGS_ENABLE

#define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5)

Definition at line 174 of file QuarkNcSocId.h.

◆ V_INTEL_VENDOR_ID

#define V_INTEL_VENDOR_ID 0x8086

Definition at line 410 of file QuarkNcSocId.h.

◆ V_LPC_VENDOR_ID

#define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID

Definition at line 421 of file QuarkNcSocId.h.

◆ V_PCIE_MAX_TRY_TIMES

#define V_PCIE_MAX_TRY_TIMES 200

Definition at line 764 of file QuarkNcSocId.h.

◆ V_QNC_LPC_ACTL_SCIS_IRQ9

#define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00

Definition at line 574 of file QuarkNcSocId.h.

◆ V_QNC_PCIE_LCAP_APMS_OFFSET

#define V_QNC_PCIE_LCAP_APMS_OFFSET 10

Definition at line 716 of file QuarkNcSocId.h.

◆ V_QNC_PCIE_SLCAP_PSN_OFFSET

#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19

Definition at line 729 of file QuarkNcSocId.h.

◆ V_QNC_PCIE_SLCAP_SLV

#define V_QNC_PCIE_SLCAP_SLV 0x0A

Definition at line 726 of file QuarkNcSocId.h.

◆ V_QNC_PCIE_SLCAP_SLV_OFFSET

#define V_QNC_PCIE_SLCAP_SLV_OFFSET 7

Definition at line 727 of file QuarkNcSocId.h.

◆ V_QNC_SMBUS_HCLK_100KHZ

#define V_QNC_SMBUS_HCLK_100KHZ 0x0054

Definition at line 449 of file QuarkNcSocId.h.

◆ V_QNC_SMBUS_HCTL_CMD_BLOCK

#define V_QNC_SMBUS_HCTL_CMD_BLOCK 5

Definition at line 440 of file QuarkNcSocId.h.

◆ V_QNC_SMBUS_HCTL_CMD_BYTE

#define V_QNC_SMBUS_HCTL_CMD_BYTE 1

Definition at line 436 of file QuarkNcSocId.h.

◆ V_QNC_SMBUS_HCTL_CMD_BYTE_DATA

#define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2

Definition at line 437 of file QuarkNcSocId.h.

◆ V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL

#define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4

Definition at line 439 of file QuarkNcSocId.h.

◆ V_QNC_SMBUS_HCTL_CMD_QUICK

#define V_QNC_SMBUS_HCTL_CMD_QUICK 0

Definition at line 435 of file QuarkNcSocId.h.

◆ V_QNC_SMBUS_HCTL_CMD_WORD_DATA

#define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3

Definition at line 438 of file QuarkNcSocId.h.

◆ V_QNC_SMBUS_RW_SEL_READ

#define V_QNC_SMBUS_RW_SEL_READ 1

Definition at line 452 of file QuarkNcSocId.h.

◆ V_QNC_SMBUS_RW_SEL_WRITE

#define V_QNC_SMBUS_RW_SEL_WRITE 0

Definition at line 453 of file QuarkNcSocId.h.

◆ V_S0

#define V_S0 0x00000000

Definition at line 512 of file QuarkNcSocId.h.

◆ V_S3

#define V_S3 0x00001400

Definition at line 513 of file QuarkNcSocId.h.

◆ V_S4

#define V_S4 0x00001800

Definition at line 514 of file QuarkNcSocId.h.

◆ V_S5

#define V_S5 0x00001C00

Definition at line 515 of file QuarkNcSocId.h.

◆ V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT

#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)

Definition at line 183 of file QuarkNcSocId.h.

◆ V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE

#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE 0

Definition at line 182 of file QuarkNcSocId.h.

◆ V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR

#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)

Definition at line 187 of file QuarkNcSocId.h.

◆ V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM

#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)

Definition at line 185 of file QuarkNcSocId.h.

Macros

Macro Definition Documentation

◆ ASTATUS0_DEFAULT_BP

◆ ASTATUS0_DEFAULT_BP_MASK

◆ ASTATUS0_RASISED_BP

◆ ASTATUS0_RASISED_BP_MASK

◆ ASTATUS1_DEFAULT_BP

◆ ASTATUS1_DEFAULT_BP_MASK

◆ ASTATUS1_RASISED_BP

◆ ASTATUS1_RASISED_BP_MASK

◆ ASTATUS_PRI_CASUAL

◆ ASTATUS_PRI_IMPENDING

◆ ASTATUS_PRI_NORMAL

◆ ASTATUS_PRI_URGENT

◆ B_CFG_STICKY_RW_ALL

◆ B_CFG_STICKY_RW_DECC_VIOLATION

◆ B_CFG_STICKY_RW_FORCE_RECOVERY

◆ B_CFG_STICKY_RW_HMB_VIOLATION

◆ B_CFG_STICKY_RW_IMR_VIOLATION

◆ B_CFG_STICKY_RW_SMM_VIOLATION

◆ B_CFG_STICKY_RW_VIOLATION

◆ B_CFG_STICKY_RW_WARM_RST

◆ B_DFUSESTAT_ECC_DIS

◆ B_MUXTOP_FLEX1_BP

◆ B_MUXTOP_FLEX1_MASK

◆ B_MUXTOP_FLEX2_BP

◆ B_MUXTOP_FLEX2_MASK

◆ B_QNC_GPE0BLK_GPE0E_EGPE

◆ B_QNC_GPE0BLK_GPE0E_GPIO

◆ B_QNC_GPE0BLK_GPE0E_PCIE

◆ B_QNC_GPE0BLK_GPE0S_ALL

◆ B_QNC_GPE0BLK_GPE0S_EGPE

◆ B_QNC_GPE0BLK_GPE0S_GPIO

◆ B_QNC_GPE0BLK_GPE0S_PCIE

◆ B_QNC_GPE0BLK_PMCW_PSE

◆ B_QNC_GPE0BLK_PMSW_DRAM_INIT

◆ B_QNC_GPE0BLK_SMIE_ALL

◆ B_QNC_GPE0BLK_SMIE_APM

◆ B_QNC_GPE0BLK_SMIE_SLP

◆ B_QNC_GPE0BLK_SMIE_SWT

◆ B_QNC_GPE0BLK_SMIS_ALL

◆ B_QNC_GPE0BLK_SMIS_APM

◆ B_QNC_GPE0BLK_SMIS_BIOS

◆ B_QNC_GPE0BLK_SMIS_EOS

◆ B_QNC_GPE0BLK_SMIS_SLP

◆ B_QNC_GPE0BLK_SMIS_SPI

◆ B_QNC_GPE0BLK_SMIS_SWT

◆ B_QNC_LPC_BIOS_CNTL_BCD

◆ B_QNC_LPC_BIOS_CNTL_BIOSWE

◆ B_QNC_LPC_BIOS_CNTL_BLE

◆ B_QNC_LPC_BIOS_CNTL_PFE

◆ B_QNC_LPC_BIOS_CNTL_SMM_BWP

◆ B_QNC_LPC_FWH_BIOS_DEC_C0

◆ B_QNC_LPC_FWH_BIOS_DEC_C8

◆ B_QNC_LPC_FWH_BIOS_DEC_D0

◆ B_QNC_LPC_FWH_BIOS_DEC_D8

◆ B_QNC_LPC_FWH_BIOS_DEC_E0

◆ B_QNC_LPC_FWH_BIOS_DEC_E8

◆ B_QNC_LPC_FWH_BIOS_DEC_F0

◆ B_QNC_LPC_FWH_BIOS_DEC_F8

◆ B_QNC_LPC_GPA_BASE_MASK

◆ B_QNC_LPC_GPE0BLK_MASK

◆ B_QNC_LPC_PIRQX_ROUT

◆ B_QNC_LPC_PM1BLK_MASK

◆ B_QNC_LPC_RCBA_EN

◆ B_QNC_LPC_RCBA_MASK

◆ B_QNC_LPC_SMBUS_BASE_EN

◆ B_QNC_LPC_SMBUS_BASE_MASK

◆ B_QNC_PCIE_CCFG_UNRS

◆ B_QNC_PCIE_CCFG_UPRS

◆ B_QNC_PCIE_CCFG_UPSD

◆ B_QNC_PCIE_DCAP_E0AL

◆ B_QNC_PCIE_DCAP_E1AL

◆ B_QNC_PCIE_DCTL_CEE

◆ B_QNC_PCIE_DCTL_FEE

◆ B_QNC_PCIE_DCTL_NFE

◆ B_QNC_PCIE_DCTL_URE

◆ B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER

◆ B_QNC_PCIE_IOSFSBCTL_SBIC_MASK

◆ B_QNC_PCIE_LCAP_APMS_MASK