Go to the source code of this file.
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#define | MIDR_CORTEX_A9_R0P1 0x410FC091 |
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#define | MIDR_CORTEX_A9_R1P2 0x411FC092 |
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#define | MIDR_CORTEX_A9_R1P3 0x411FC093 |
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#define | MIDR_CORTEX_A9_R2P10 0x412FC09A |
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#define | MIDR_CORTEX_A15_R0P0 0x410FC0F0 |
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#define | CCSIDR_LINE_SIZE_OFFSET 0 |
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#define | CCSIDR_LINE_SIZE_MASK 0x7 |
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#define | CCSIDR_ASSOCIATIVITY_OFFSET 3 |
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#define | CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) |
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#define | CCSIDR_NUM_SETS_OFFSET 13 |
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#define | CCSIDR_NUM_SETS_MASK (0x7FFF << 13) |
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#define | ARMV7_CSSELR_IND_DATA_UNIFIED 0 |
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#define | ARMV7_CSSELR_IND_INSTRUCTION 1 |
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#define | ARMV7_CLIDR_CTYPE_NO_CACHE 0 |
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#define | ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 |
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#define | ARMV7_CLIDR_CTYPE_DATA_ONLY 2 |
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#define | ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 |
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#define | ARMV7_CLIDR_CTYPE_UNIFIED 4 |
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#define | CP15ISB (asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))) |
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#define | CP15DSB (asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))) |
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#define | CP15DMB (asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))) |
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◆ ARMV7_CLIDR_CTYPE_DATA_ONLY
#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 |
◆ ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA
#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 |
◆ ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY
#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 |
◆ ARMV7_CLIDR_CTYPE_NO_CACHE
#define ARMV7_CLIDR_CTYPE_NO_CACHE 0 |
◆ ARMV7_CLIDR_CTYPE_UNIFIED
#define ARMV7_CLIDR_CTYPE_UNIFIED 4 |
◆ ARMV7_CSSELR_IND_DATA_UNIFIED
#define ARMV7_CSSELR_IND_DATA_UNIFIED 0 |
◆ ARMV7_CSSELR_IND_INSTRUCTION
#define ARMV7_CSSELR_IND_INSTRUCTION 1 |
◆ CCSIDR_ASSOCIATIVITY_MASK
#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) |
◆ CCSIDR_ASSOCIATIVITY_OFFSET
#define CCSIDR_ASSOCIATIVITY_OFFSET 3 |
◆ CCSIDR_LINE_SIZE_MASK
#define CCSIDR_LINE_SIZE_MASK 0x7 |
◆ CCSIDR_LINE_SIZE_OFFSET
#define CCSIDR_LINE_SIZE_OFFSET 0 |
◆ CCSIDR_NUM_SETS_MASK
#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) |
◆ CCSIDR_NUM_SETS_OFFSET
#define CCSIDR_NUM_SETS_OFFSET 13 |
◆ CP15DMB
#define CP15DMB (asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))) |
◆ CP15DSB
#define CP15DSB (asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))) |
◆ CP15ISB
#define CP15ISB (asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))) |
◆ MIDR_CORTEX_A15_R0P0
#define MIDR_CORTEX_A15_R0P0 0x410FC0F0 |
◆ MIDR_CORTEX_A9_R0P1
#define MIDR_CORTEX_A9_R0P1 0x410FC091 |
◆ MIDR_CORTEX_A9_R1P2
#define MIDR_CORTEX_A9_R1P2 0x411FC092 |
◆ MIDR_CORTEX_A9_R1P3
#define MIDR_CORTEX_A9_R1P3 0x411FC093 |
◆ MIDR_CORTEX_A9_R2P10
#define MIDR_CORTEX_A9_R2P10 0x412FC09A |