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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <edid.h>
Go to the source code of this file.
Enumerations | |
enum | dp_pll_clk_src { SN65_SEL_12MHZ = 0x0 , SN65_SEL_19MHZ = 0x1 , SN65_SEL_26MHZ = 0x2 , SN65_SEL_27MHZ = 0x3 , SN65_SEL_38MHZ = 0x4 } |
Functions | |
void | sn65dsi86_bridge_init (uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk) |
void | sn65dsi86_bridge_configure (uint8_t bus, uint8_t chip, struct edid *edid, uint32_t num_of_lines, uint32_t dsi_bpp) |
enum cb_err | sn65dsi86_bridge_read_edid (uint8_t bus, uint8_t chip, struct edid *out) |
void | sn65dsi86_backlight_enable (uint8_t bus, uint8_t chip) |
enum dp_pll_clk_src |
Enumerator | |
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SN65_SEL_12MHZ | |
SN65_SEL_19MHZ | |
SN65_SEL_26MHZ | |
SN65_SEL_27MHZ | |
SN65_SEL_38MHZ |
Definition at line 8 of file sn65dsi86bridge.h.
Definition at line 439 of file sn65dsi86bridge.c.
References chip, DP_BACKLIGHT_BRIGHTNESS_MSB, DP_BACKLIGHT_CONTROL_MODE_DPCD, DP_BACKLIGHT_ENABLE, DP_BACKLIGHT_MODE_SET, DP_DISPLAY_CONTROL_REGISTER, DPCD_WRITE, sn65dsi86_bridge_aux_request(), and val.
void sn65dsi86_bridge_configure | ( | uint8_t | bus, |
uint8_t | chip, | ||
struct edid * | edid, | ||
uint32_t | num_of_lines, | ||
uint32_t | dsi_bpp | ||
) |
Definition at line 481 of file sn65dsi86bridge.c.
References chip, i2c_write_field(), i2c_writeb(), sn65dsi86_bridge_assr_config(), sn65dsi86_bridge_dp_lane_config(), sn65dsi86_bridge_link_training(), sn65dsi86_bridge_set_bridge_active_timing(), sn65dsi86_bridge_set_dp_clock_range(), sn65dsi86_bridge_set_dsi_clock_range(), SN_COLOR_BAR_REG, SN_DATA_FORMAT_REG, and SN_DSI_LANES_REG.
void sn65dsi86_bridge_init | ( | uint8_t | bus, |
uint8_t | chip, | ||
enum dp_pll_clk_src | ref_clk | ||
) |
Definition at line 472 of file sn65dsi86bridge.c.
References chip, HPD_DISABLE, i2c_write_field(), SN_DPPLL_SRC_REG, and SN_HPD_DISABLE_REG.
Referenced by display_startup().
Definition at line 154 of file sn65dsi86bridge.c.
Referenced by display_startup().