coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
elog.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <amdblocks/acpi.h>
4 #include <elog.h>
5 #include <soc/southbridge.h>
6 
7 static void elog_pm1_status(const struct acpi_pm_gpe_state *state)
8 {
9  uint16_t pm1_sts = state->pm1_sts;
10 
11  if (pm1_sts & WAK_STS)
12  elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, state->previous_sx_state);
13 
14  if (pm1_sts & PWRBTN_STS)
16 
17  if (pm1_sts & RTC_STS)
19 
20  if (pm1_sts & PCIEXPWAK_STS)
22 }
23 
24 static void elog_gpe_events(const struct acpi_pm_gpe_state *state)
25 {
26  int i;
27  uint32_t valid_gpe = state->gpe0_sts & state->gpe0_en;
28 
29  for (i = 0; i <= 31; i++) {
30  if (valid_gpe & (1U << i))
32  }
33 }
34 
35 void acpi_log_events(const struct chipset_power_state *ps)
36 {
39 }
#define PWRBTN_STS
Definition: southbridge.h:30
#define PCIEXPWAK_STS
Definition: southbridge.h:28
#define WAK_STS
Definition: southbridge.h:27
#define RTC_STS
Definition: southbridge.h:29
#define ELOG_WAKE_SOURCE_RTC
Definition: elog.h:154
#define ELOG_WAKE_SOURCE_PCIE
Definition: elog.h:151
#define ELOG_TYPE_ACPI_WAKE
Definition: elog.h:149
#define ELOG_WAKE_SOURCE_GPE
Definition: elog.h:155
#define ELOG_WAKE_SOURCE_PWRBTN
Definition: elog.h:157
int elog_add_event_byte(u8 event_type, u8 data)
Definition: elog.c:868
int elog_add_event_wake(u8 source, u32 instance)
Definition: elog.c:883
state
Definition: raminit.c:1787
static void elog_gpe_events(const struct acpi_pm_gpe_state *state)
Definition: elog.c:24
void acpi_log_events(const struct chipset_power_state *ps)
Definition: elog.c:35
static void elog_pm1_status(const struct acpi_pm_gpe_state *state)
Definition: elog.c:7
unsigned short uint16_t
Definition: stdint.h:11
unsigned int uint32_t
Definition: stdint.h:14
struct acpi_pm_gpe_state gpe_state
Definition: acpi.h:49