coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Data Structures | Macros | Functions | Variables
spm.h File Reference
#include <device/mmio.h>
#include <soc/addressmap.h>
#include <soc/mtcmos.h>
#include <types.h>
Include dependency graph for spm.h:

Go to the source code of this file.

Data Structures

struct  mtk_spm_regs
 
struct  pwr_ctrl
 
struct  pcm_desc
 
struct  dyna_load_pcm
 

Macros

#define SPM_INIT_DONE_US   20
 
#define CLK_SCP_CFG_0   (IO_PHYS + 0x200)
 
#define CLK_SCP_CFG_1   (IO_PHYS + 0x210)
 
#define INFRA_AO_RES_CTRL_MASK   (INFRACFG_AO_BASE + 0xB8)
 
#define AP_PLL_CON3   (APMIXED_BASE + 0xC)
 
#define AP_PLL_CON4   (APMIXED_BASE + 0x10)
 
#define MD32PCM_BASE   (SPM_BASE + 0x0A00)
 
#define MD32PCM_CFGREG_SW_RSTN   (MD32PCM_BASE + 0x0000)
 
#define MD32PCM_DMA0_SRC   (MD32PCM_BASE + 0x0200)
 
#define MD32PCM_DMA0_DST   (MD32PCM_BASE + 0x0204)
 
#define MD32PCM_DMA0_WPPT   (MD32PCM_BASE + 0x0208)
 
#define MD32PCM_DMA0_WPTO   (MD32PCM_BASE + 0x020C)
 
#define MD32PCM_DMA0_COUNT   (MD32PCM_BASE + 0x0210)
 
#define MD32PCM_DMA0_CON   (MD32PCM_BASE + 0x0214)
 
#define MD32PCM_DMA0_START   (MD32PCM_BASE + 0x0218)
 
#define MD32PCM_DMA0_RLCT   (MD32PCM_BASE + 0x0224)
 
#define MD32PCM_INTC_IRQ_RAW_STA   (MD32PCM_BASE + 0x033C)
 
#define MD32PCM_CFGREG_SW_RSTN_RUN   1
 
#define MD32PCM_DMA0_CON_VAL   0x0003820E
 
#define MD32PCM_DMA0_START_VAL   0x00008000
 
#define BCLK_CG_EN_LSB   BIT(0)
 
#define PCM_CK_EN_LSB   BIT(2)
 
#define PCM_SW_RESET_LSB   BIT(15)
 
#define RG_AHBMIF_APBEN_LSB   BIT(3)
 
#define REG_MD32_APB_INTERNAL_EN_LSB   BIT(14)
 
#define PCM_RF_SYNC_R7   BIT(23)
 
#define REG_DDREN_DBC_EN_LSB   BIT(16)
 
#define SPM_PROJECT_CODE   0xB16
 
#define SPM_REGWR_CFG_KEY   (SPM_PROJECT_CODE << 16)
 
#define POWER_ON_VAL1_DEF   0x80015860
 
#define SPM_WAKEUP_EVENT_MASK_DEF   0xEFFFFFFF
 
#define DDREN_DBC_EN_VAL   0x154
 
#define ARMPLL_CLK_SEL_DEF   0x3FF
 
#define SPM_RESOURCE_ACK_CON0_DEF   0x00000000
 
#define SPM_RESOURCE_ACK_CON1_DEF   0x00000000
 
#define SPM_RESOURCE_ACK_CON2_DEF   0xCCCC4E4E
 
#define SPM_RESOURCE_ACK_CON3_DEF   0x00000000
 
#define APMIX_CON3_DEF   0xFFFF7770
 
#define APMIX_CON4_DEF   0xFFFAA007
 
#define SCP_CFG0_DEF   0x3FF
 
#define SCP_CFG1_DEF   0x3
 
#define SPM_DVFS_LEVEL_DEF   0x00000001
 
#define SPM_DVS_DFS_LEVEL_DEF   0x00010001
 
#define SPM_ACK_CHK_3_SEL_HW_S1   0x0035009F
 
#define SPM_ACK_CHK_3_HW_S1_CNT   1
 
#define SPM_SYSCLK_SETTLE   0x60FE /* 1685us */
 
#define SPM_WAKEUP_EVENT_MASK_BIT0   1
 
#define RG_PCM_TIMER_EN_LSB   BIT(5)
 
#define RG_PCM_WDT_WAKE_LSB   BIT(9)
 
#define PCM_RF_SYNC_R0   BIT(16)
 
#define REG_SPM_EVENT_COUNTER_CLR_LSB   BIT(6)
 
#define R12_CSYSPWREQ_B   BIT(24)
 
#define SPM_BUS_PROTECT_MASK_B_DEF   0xFFFFFFFF
 
#define SPM_BUS_PROTECT2_MASK_B_DEF   0xFFFFFFFF
 
#define SPM_FLAG_DISABLE_VCORE_DVS   BIT(3)
 
#define SPM_FLAG_DISABLE_VCORE_DFS   BIT(4)
 
#define SPM_FLAG_RUN_COMMON_SCENARIO   BIT(10)
 
#define PCM_WDT_TIMEOUT   (30 * 32768) /* 30s */
 
#define PCM_TIMER_MAX   (0xffffffff - PCM_WDT_TIMEOUT)
 
#define ISRM_TWAM   BIT(2)
 
#define ISRM_PCM_RETURN   BIT(3)
 
#define ISRM_RET_IRQ0   BIT(8)
 
#define ISRM_RET_IRQ1   BIT(9)
 
#define ISRM_RET_IRQ2   BIT(10)
 
#define ISRM_RET_IRQ3   BIT(11)
 
#define ISRM_RET_IRQ4   BIT(12)
 
#define ISRM_RET_IRQ5   BIT(13)
 
#define ISRM_RET_IRQ6   BIT(14)
 
#define ISRM_RET_IRQ7   BIT(15)
 
#define ISRM_RET_IRQ8   BIT(16)
 
#define ISRM_RET_IRQ9   BIT(17)
 
#define ISRM_RET_IRQ_AUX
 
#define ISRM_ALL_EXC_TWAM   ISRM_RET_IRQ_AUX
 
#define ISRM_ALL   (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
 
#define ISRS_TWAM   BIT(2)
 
#define ISRS_PCM_RETURN   BIT(3)
 
#define ISRC_TWAM   ISRS_TWAM
 
#define ISRC_ALL_EXC_TWAM   ISRS_PCM_RETURN
 
#define ISRC_ALL   (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
 
#define PCM_SW_INT0   BIT(0)
 
#define PCM_SW_INT1   BIT(1)
 
#define PCM_SW_INT2   BIT(2)
 
#define PCM_SW_INT3   BIT(3)
 
#define PCM_SW_INT4   BIT(4)
 
#define PCM_SW_INT5   BIT(5)
 
#define PCM_SW_INT6   BIT(6)
 
#define PCM_SW_INT7   BIT(7)
 
#define PCM_SW_INT8   BIT(8)
 
#define PCM_SW_INT9   BIT(9)
 
#define PCM_SW_INT_ALL
 

Functions

 check_member (mtk_spm_regs, poweron_config_set, 0x0)
 
 check_member (mtk_spm_regs, dis_pwr_con, 0x354)
 
 check_member (mtk_spm_regs, nna_pwr_con, 0x3E0)
 
 check_member (mtk_spm_regs, ap_mdsrc_req, 0x430)
 
 check_member (mtk_spm_regs, ssusb_top_pwr_con, 0x9F0)
 
 check_member (mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4)
 
 check_member (mtk_spm_regs, adsp_infra_pwr_con, 0x9F8)
 
 check_member (mtk_spm_regs, adsp_ao_pwr_con, 0x9FC)
 
int spm_init (void)
 

Variables

static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE
 
static const struct power_domain_data disp []
 
static const struct power_domain_data audio []
 

Macro Definition Documentation

◆ AP_PLL_CON3

#define AP_PLL_CON3   (APMIXED_BASE + 0xC)

Definition at line 22 of file spm.h.

◆ AP_PLL_CON4

#define AP_PLL_CON4   (APMIXED_BASE + 0x10)

Definition at line 23 of file spm.h.

◆ APMIX_CON3_DEF

#define APMIX_CON3_DEF   0xFFFF7770

Definition at line 74 of file spm.h.

◆ APMIX_CON4_DEF

#define APMIX_CON4_DEF   0xFFFAA007

Definition at line 75 of file spm.h.

◆ ARMPLL_CLK_SEL_DEF

#define ARMPLL_CLK_SEL_DEF   0x3FF

Definition at line 69 of file spm.h.

◆ BCLK_CG_EN_LSB

#define BCLK_CG_EN_LSB   BIT(0)

Definition at line 43 of file spm.h.

◆ CLK_SCP_CFG_0

#define CLK_SCP_CFG_0   (IO_PHYS + 0x200)

Definition at line 18 of file spm.h.

◆ CLK_SCP_CFG_1

#define CLK_SCP_CFG_1   (IO_PHYS + 0x210)

Definition at line 19 of file spm.h.

◆ DDREN_DBC_EN_VAL

#define DDREN_DBC_EN_VAL   0x154

Definition at line 68 of file spm.h.

◆ INFRA_AO_RES_CTRL_MASK

#define INFRA_AO_RES_CTRL_MASK   (INFRACFG_AO_BASE + 0xB8)

Definition at line 20 of file spm.h.

◆ ISRC_ALL

#define ISRC_ALL   (ISRC_ALL_EXC_TWAM | ISRC_TWAM)

Definition at line 125 of file spm.h.

◆ ISRC_ALL_EXC_TWAM

#define ISRC_ALL_EXC_TWAM   ISRS_PCM_RETURN

Definition at line 124 of file spm.h.

◆ ISRC_TWAM

#define ISRC_TWAM   ISRS_TWAM

Definition at line 123 of file spm.h.

◆ ISRM_ALL

#define ISRM_ALL   (ISRM_ALL_EXC_TWAM | ISRM_TWAM)

Definition at line 118 of file spm.h.

◆ ISRM_ALL_EXC_TWAM

#define ISRM_ALL_EXC_TWAM   ISRM_RET_IRQ_AUX

Definition at line 117 of file spm.h.

◆ ISRM_PCM_RETURN

#define ISRM_PCM_RETURN   BIT(3)

Definition at line 103 of file spm.h.

◆ ISRM_RET_IRQ0

#define ISRM_RET_IRQ0   BIT(8)

Definition at line 104 of file spm.h.

◆ ISRM_RET_IRQ1

#define ISRM_RET_IRQ1   BIT(9)

Definition at line 105 of file spm.h.

◆ ISRM_RET_IRQ2

#define ISRM_RET_IRQ2   BIT(10)

Definition at line 106 of file spm.h.

◆ ISRM_RET_IRQ3

#define ISRM_RET_IRQ3   BIT(11)

Definition at line 107 of file spm.h.

◆ ISRM_RET_IRQ4

#define ISRM_RET_IRQ4   BIT(12)

Definition at line 108 of file spm.h.

◆ ISRM_RET_IRQ5

#define ISRM_RET_IRQ5   BIT(13)

Definition at line 109 of file spm.h.

◆ ISRM_RET_IRQ6

#define ISRM_RET_IRQ6   BIT(14)

Definition at line 110 of file spm.h.

◆ ISRM_RET_IRQ7

#define ISRM_RET_IRQ7   BIT(15)

Definition at line 111 of file spm.h.

◆ ISRM_RET_IRQ8

#define ISRM_RET_IRQ8   BIT(16)

Definition at line 112 of file spm.h.

◆ ISRM_RET_IRQ9

#define ISRM_RET_IRQ9   BIT(17)

Definition at line 113 of file spm.h.

◆ ISRM_RET_IRQ_AUX

#define ISRM_RET_IRQ_AUX
Value:
(ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | ISRM_RET_IRQ7 | \
ISRM_RET_IRQ6 | ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \
ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | ISRM_RET_IRQ1)
ISRM_RET_IRQ9
#define ISRM_RET_IRQ9
Definition: spm.h:113
ISRM_RET_IRQ7
#define ISRM_RET_IRQ7
Definition: spm.h:111
ISRM_RET_IRQ2
#define ISRM_RET_IRQ2
Definition: spm.h:106
ISRM_RET_IRQ8
#define ISRM_RET_IRQ8
Definition: spm.h:112
ISRM_RET_IRQ4
#define ISRM_RET_IRQ4
Definition: spm.h:108
ISRM_RET_IRQ1
#define ISRM_RET_IRQ1
Definition: spm.h:105
ISRM_RET_IRQ5
#define ISRM_RET_IRQ5
Definition: spm.h:109

Definition at line 114 of file spm.h.

◆ ISRM_TWAM

#define ISRM_TWAM   BIT(2)

Definition at line 102 of file spm.h.

◆ ISRS_PCM_RETURN

#define ISRS_PCM_RETURN   BIT(3)

Definition at line 122 of file spm.h.

◆ ISRS_TWAM

#define ISRS_TWAM   BIT(2)

Definition at line 121 of file spm.h.

◆ MD32PCM_BASE

#define MD32PCM_BASE   (SPM_BASE + 0x0A00)

Definition at line 26 of file spm.h.

◆ MD32PCM_CFGREG_SW_RSTN

#define MD32PCM_CFGREG_SW_RSTN   (MD32PCM_BASE + 0x0000)

Definition at line 27 of file spm.h.

◆ MD32PCM_CFGREG_SW_RSTN_RUN

#define MD32PCM_CFGREG_SW_RSTN_RUN   1

Definition at line 38 of file spm.h.

◆ MD32PCM_DMA0_CON

#define MD32PCM_DMA0_CON   (MD32PCM_BASE + 0x0214)

Definition at line 33 of file spm.h.

◆ MD32PCM_DMA0_CON_VAL

#define MD32PCM_DMA0_CON_VAL   0x0003820E

Definition at line 39 of file spm.h.

◆ MD32PCM_DMA0_COUNT

#define MD32PCM_DMA0_COUNT   (MD32PCM_BASE + 0x0210)

Definition at line 32 of file spm.h.

◆ MD32PCM_DMA0_DST

#define MD32PCM_DMA0_DST   (MD32PCM_BASE + 0x0204)

Definition at line 29 of file spm.h.

◆ MD32PCM_DMA0_RLCT

#define MD32PCM_DMA0_RLCT   (MD32PCM_BASE + 0x0224)

Definition at line 35 of file spm.h.

◆ MD32PCM_DMA0_SRC

#define MD32PCM_DMA0_SRC   (MD32PCM_BASE + 0x0200)

Definition at line 28 of file spm.h.

◆ MD32PCM_DMA0_START

#define MD32PCM_DMA0_START   (MD32PCM_BASE + 0x0218)

Definition at line 34 of file spm.h.

◆ MD32PCM_DMA0_START_VAL

#define MD32PCM_DMA0_START_VAL   0x00008000

Definition at line 40 of file spm.h.

◆ MD32PCM_DMA0_WPPT

#define MD32PCM_DMA0_WPPT   (MD32PCM_BASE + 0x0208)

Definition at line 30 of file spm.h.

◆ MD32PCM_DMA0_WPTO

#define MD32PCM_DMA0_WPTO   (MD32PCM_BASE + 0x020C)

Definition at line 31 of file spm.h.

◆ MD32PCM_INTC_IRQ_RAW_STA

#define MD32PCM_INTC_IRQ_RAW_STA   (MD32PCM_BASE + 0x033C)

Definition at line 36 of file spm.h.

◆ PCM_CK_EN_LSB

#define PCM_CK_EN_LSB   BIT(2)

Definition at line 44 of file spm.h.

◆ PCM_RF_SYNC_R0

#define PCM_RF_SYNC_R0   BIT(16)

Definition at line 86 of file spm.h.

◆ PCM_RF_SYNC_R7

#define PCM_RF_SYNC_R7   BIT(23)

Definition at line 48 of file spm.h.

◆ PCM_SW_INT0

#define PCM_SW_INT0   BIT(0)

Definition at line 128 of file spm.h.

◆ PCM_SW_INT1

#define PCM_SW_INT1   BIT(1)

Definition at line 129 of file spm.h.

◆ PCM_SW_INT2

#define PCM_SW_INT2   BIT(2)

Definition at line 130 of file spm.h.

◆ PCM_SW_INT3

#define PCM_SW_INT3   BIT(3)

Definition at line 131 of file spm.h.

◆ PCM_SW_INT4

#define PCM_SW_INT4   BIT(4)

Definition at line 132 of file spm.h.

◆ PCM_SW_INT5

#define PCM_SW_INT5   BIT(5)

Definition at line 133 of file spm.h.

◆ PCM_SW_INT6

#define PCM_SW_INT6   BIT(6)

Definition at line 134 of file spm.h.

◆ PCM_SW_INT7

#define PCM_SW_INT7   BIT(7)

Definition at line 135 of file spm.h.

◆ PCM_SW_INT8

#define PCM_SW_INT8   BIT(8)

Definition at line 136 of file spm.h.

◆ PCM_SW_INT9

#define PCM_SW_INT9   BIT(9)

Definition at line 137 of file spm.h.

◆ PCM_SW_INT_ALL

#define PCM_SW_INT_ALL
Value:
(PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
PCM_SW_INT0)
PCM_SW_INT4
#define PCM_SW_INT4
Definition: spm.h:132
PCM_SW_INT7
#define PCM_SW_INT7
Definition: spm.h:135
PCM_SW_INT2
#define PCM_SW_INT2
Definition: spm.h:130
PCM_SW_INT1
#define PCM_SW_INT1
Definition: spm.h:129
PCM_SW_INT9
#define PCM_SW_INT9
Definition: spm.h:137
PCM_SW_INT8
#define PCM_SW_INT8
Definition: spm.h:136
PCM_SW_INT5
#define PCM_SW_INT5
Definition: spm.h:133

Definition at line 138 of file spm.h.

◆ PCM_SW_RESET_LSB

#define PCM_SW_RESET_LSB   BIT(15)

Definition at line 45 of file spm.h.

◆ PCM_TIMER_MAX

#define PCM_TIMER_MAX   (0xffffffff - PCM_WDT_TIMEOUT)

Definition at line 99 of file spm.h.

◆ PCM_WDT_TIMEOUT

#define PCM_WDT_TIMEOUT   (30 * 32768) /* 30s */

Definition at line 97 of file spm.h.

◆ POWER_ON_VAL1_DEF

#define POWER_ON_VAL1_DEF   0x80015860

Definition at line 66 of file spm.h.

◆ R12_CSYSPWREQ_B

#define R12_CSYSPWREQ_B   BIT(24)

Definition at line 88 of file spm.h.

◆ REG_DDREN_DBC_EN_LSB

#define REG_DDREN_DBC_EN_LSB   BIT(16)

Definition at line 49 of file spm.h.

◆ REG_MD32_APB_INTERNAL_EN_LSB

#define REG_MD32_APB_INTERNAL_EN_LSB   BIT(14)

Definition at line 47 of file spm.h.

◆ REG_SPM_EVENT_COUNTER_CLR_LSB

#define REG_SPM_EVENT_COUNTER_CLR_LSB   BIT(6)

Definition at line 87 of file spm.h.

◆ RG_AHBMIF_APBEN_LSB

#define RG_AHBMIF_APBEN_LSB   BIT(3)

Definition at line 46 of file spm.h.

◆ RG_PCM_TIMER_EN_LSB

#define RG_PCM_TIMER_EN_LSB   BIT(5)

Definition at line 84 of file spm.h.

◆ RG_PCM_WDT_WAKE_LSB

#define RG_PCM_WDT_WAKE_LSB   BIT(9)

Definition at line 85 of file spm.h.

◆ SCP_CFG0_DEF

#define SCP_CFG0_DEF   0x3FF

Definition at line 76 of file spm.h.

◆ SCP_CFG1_DEF

#define SCP_CFG1_DEF   0x3

Definition at line 77 of file spm.h.

◆ SPM_ACK_CHK_3_HW_S1_CNT

#define SPM_ACK_CHK_3_HW_S1_CNT   1

Definition at line 81 of file spm.h.

◆ SPM_ACK_CHK_3_SEL_HW_S1

#define SPM_ACK_CHK_3_SEL_HW_S1   0x0035009F

Definition at line 80 of file spm.h.

◆ SPM_BUS_PROTECT2_MASK_B_DEF

#define SPM_BUS_PROTECT2_MASK_B_DEF   0xFFFFFFFF

Definition at line 90 of file spm.h.

◆ SPM_BUS_PROTECT_MASK_B_DEF

#define SPM_BUS_PROTECT_MASK_B_DEF   0xFFFFFFFF

Definition at line 89 of file spm.h.

◆ SPM_DVFS_LEVEL_DEF

#define SPM_DVFS_LEVEL_DEF   0x00000001

Definition at line 78 of file spm.h.

◆ SPM_DVS_DFS_LEVEL_DEF

#define SPM_DVS_DFS_LEVEL_DEF   0x00010001

Definition at line 79 of file spm.h.

◆ SPM_FLAG_DISABLE_VCORE_DFS

#define SPM_FLAG_DISABLE_VCORE_DFS   BIT(4)

Definition at line 93 of file spm.h.

◆ SPM_FLAG_DISABLE_VCORE_DVS

#define SPM_FLAG_DISABLE_VCORE_DVS   BIT(3)

Definition at line 92 of file spm.h.

◆ SPM_FLAG_RUN_COMMON_SCENARIO

#define SPM_FLAG_RUN_COMMON_SCENARIO   BIT(10)

Definition at line 94 of file spm.h.

◆ SPM_INIT_DONE_US

#define SPM_INIT_DONE_US   20

Definition at line 16 of file spm.h.

◆ SPM_PROJECT_CODE

#define SPM_PROJECT_CODE   0xB16

Definition at line 64 of file spm.h.

◆ SPM_REGWR_CFG_KEY

#define SPM_REGWR_CFG_KEY   (SPM_PROJECT_CODE << 16)

Definition at line 65 of file spm.h.

◆ SPM_RESOURCE_ACK_CON0_DEF

#define SPM_RESOURCE_ACK_CON0_DEF   0x00000000

Definition at line 70 of file spm.h.

◆ SPM_RESOURCE_ACK_CON1_DEF

#define SPM_RESOURCE_ACK_CON1_DEF   0x00000000

Definition at line 71 of file spm.h.

◆ SPM_RESOURCE_ACK_CON2_DEF

#define SPM_RESOURCE_ACK_CON2_DEF   0xCCCC4E4E

Definition at line 72 of file spm.h.

◆ SPM_RESOURCE_ACK_CON3_DEF

#define SPM_RESOURCE_ACK_CON3_DEF   0x00000000

Definition at line 73 of file spm.h.

◆ SPM_SYSCLK_SETTLE

#define SPM_SYSCLK_SETTLE   0x60FE /* 1685us */

Definition at line 82 of file spm.h.

◆ SPM_WAKEUP_EVENT_MASK_BIT0

#define SPM_WAKEUP_EVENT_MASK_BIT0   1

Definition at line 83 of file spm.h.

◆ SPM_WAKEUP_EVENT_MASK_DEF

#define SPM_WAKEUP_EVENT_MASK_DEF   0xEFFFFFFF

Definition at line 67 of file spm.h.

Function Documentation

◆ check_member() [1/8]

check_member ( mtk_spm_regs  ,
adsp_ao_pwr_con  ,
0x9FC   
)

◆ check_member() [2/8]

check_member ( mtk_spm_regs  ,
adsp_infra_pwr_con  ,
0x9F8   
)

◆ check_member() [3/8]

check_member ( mtk_spm_regs  ,
ap_mdsrc_req  ,
0x430   
)

◆ check_member() [4/8]

check_member ( mtk_spm_regs  ,
dis_pwr_con  ,
0x354   
)

◆ check_member() [5/8]

check_member ( mtk_spm_regs  ,
nna_pwr_con  ,
0x3E0   
)

◆ check_member() [6/8]

check_member ( mtk_spm_regs  ,
poweron_config_set  ,
0x0   
)

◆ check_member() [7/8]

check_member ( mtk_spm_regs  ,
ssusb_top_p1_pwr_con  ,
0x9F4   
)

◆ check_member() [8/8]

check_member ( mtk_spm_regs  ,
ssusb_top_pwr_con  ,
0x9F0   
)

◆ spm_init()

int spm_init ( void  )

Definition at line 298 of file spm.c.

Variable Documentation

◆ audio

const struct power_domain_data audio[]
static
Initial value:
= {
}

Definition at line 858 of file spm.h.

◆ disp

const struct power_domain_data disp[]
static
Initial value:
= {
{
.pwr_con = &mtk_spm->dis_pwr_con,
.pwr_sta_mask = 0x1 << 21,
.sram_pdn_mask = 0x1 << 8,
.sram_ack_mask = 0x1 << 12,
},
}
mtk_spm
static struct mtk_spm_regs *const mtk_spm
Definition: spm.h:858
mtk_spm_regs::dis_pwr_con
u32 dis_pwr_con
Definition: spm.h:44

Definition at line 858 of file spm.h.

◆ mtk_spm

struct mtk_spm_regs* const mtk_spm = (void *)SPM_BASE
static

Definition at line 858 of file spm.h.