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coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Public Types | Data Fields
soc_intel_icelake_config Struct Reference

#include <chip.h>

Collaboration diagram for soc_intel_icelake_config:
Collaboration graph

Public Types

enum  {
  SaGv_Disabled , SaGv_FixedLow , SaGv_FixedMid , SaGv_FixedHigh ,
  SaGv_Enabled
}
 

Data Fields

struct soc_intel_common_config common_soc_config
 
uint8_t gpe0_dw0
 
uint8_t gpe0_dw1
 
uint8_t gpe0_dw2
 
uint32_t gen1_dec
 
uint32_t gen2_dec
 
uint32_t gen3_dec
 
uint32_t gen4_dec
 
int s0ix_enable
 
int dptf_enable
 
int deep_s3_enable_ac
 
int deep_s3_enable_dc
 
int deep_s5_enable_ac
 
int deep_s5_enable_dc
 
uint32_t deep_sx_config
 
uint32_t tcc_offset
 
enum soc_intel_icelake_config:: { ... }  SaGv
 
uint8_t RMT
 
struct usb2_port_config usb2_ports [16]
 
struct usb3_port_config usb3_ports [10]
 
uint16_t usb2_wake_enable_bitmap
 
uint16_t usb3_wake_enable_bitmap
 
uint8_t SataEnable
 
uint8_t SataMode
 
uint8_t SataSalpSupport
 
uint8_t SataPortsEnable [8]
 
uint8_t SataPortsDevSlp [8]
 
uint8_t PchHdaEnable
 
uint8_t PchHdaDspEnable
 
uint8_t PchHdaAudioLinkHda
 
uint8_t PchHdaAudioLinkDmic0
 
uint8_t PchHdaAudioLinkDmic1
 
uint8_t PchHdaAudioLinkSsp0
 
uint8_t PchHdaAudioLinkSsp1
 
uint8_t PchHdaAudioLinkSsp2
 
uint8_t PchHdaAudioLinkSndw1
 
uint8_t PchHdaAudioLinkSndw2
 
uint8_t PchHdaAudioLinkSndw3
 
uint8_t PchHdaAudioLinkSndw4
 
uint8_t PcieRpEnable [CONFIG_MAX_ROOT_PORTS]
 
uint8_t PcieClkSrcUsage [CONFIG_MAX_ROOT_PORTS]
 
uint8_t PcieClkSrcClkReq [CONFIG_MAX_ROOT_PORTS]
 
uint8_t SmbusEnable
 
uint8_t ScsEmmcHs400Enabled
 
uint8_t EmmcUseCustomDlls
 
uint32_t EmmcTxCmdDelayRegValue
 
uint32_t EmmcTxDataDelay1RegValue
 
uint32_t EmmcTxDataDelay2RegValue
 
uint32_t EmmcRxCmdDataDelay1RegValue
 
uint32_t EmmcRxCmdDataDelay2RegValue
 
uint32_t EmmcRxStrobeDelayRegValue
 
uint8_t SdCardPowerEnableActiveHigh
 
uint8_t Heci3Enabled
 
uint8_t SkipExtGfxScan
 
uint8_t Device4Enable
 
uint8_t eist_enable
 
uint8_t enable_c6dram
 
uint8_t SerialIoI2cMode [CONFIG_SOC_INTEL_I2C_DEV_MAX]
 
uint8_t SerialIoGSpiMode [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
 
uint8_t SerialIoUartMode [CONFIG_SOC_INTEL_UART_DEV_MAX]
 
uint8_t SerialIoGSpiCsMode [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
 
uint8_t SerialIoGSpiCsState [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
 
unsigned int sdcard_cd_gpio
 
uint8_t pch_isclk
 
bool CnviBtAudioOffload
 
uint8_t gpio_override_pm
 
uint8_t gpio_pm [TOTAL_GPIO_COMM]
 

Detailed Description

Definition at line 20 of file chip.h.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum
Enumerator
SaGv_Disabled 
SaGv_FixedLow 
SaGv_FixedMid 
SaGv_FixedHigh 
SaGv_Enabled 

Definition at line 60 of file chip.h.

Field Documentation

◆ CnviBtAudioOffload

bool soc_intel_icelake_config::CnviBtAudioOffload

Definition at line 174 of file chip.h.

◆ common_soc_config

struct soc_intel_common_config soc_intel_icelake_config::common_soc_config

Definition at line 1 of file chip.h.

◆ deep_s3_enable_ac

int soc_intel_icelake_config::deep_s3_enable_ac

Definition at line 43 of file chip.h.

◆ deep_s3_enable_dc

int soc_intel_icelake_config::deep_s3_enable_dc

Definition at line 44 of file chip.h.

◆ deep_s5_enable_ac

int soc_intel_icelake_config::deep_s5_enable_ac

Definition at line 45 of file chip.h.

◆ deep_s5_enable_dc

int soc_intel_icelake_config::deep_s5_enable_dc

Definition at line 46 of file chip.h.

◆ deep_sx_config

uint32_t soc_intel_icelake_config::deep_sx_config

Definition at line 52 of file chip.h.

◆ Device4Enable

uint8_t soc_intel_icelake_config::Device4Enable

Definition at line 135 of file chip.h.

◆ dptf_enable

int soc_intel_icelake_config::dptf_enable

Definition at line 40 of file chip.h.

◆ eist_enable

uint8_t soc_intel_icelake_config::eist_enable

Definition at line 138 of file chip.h.

◆ EmmcRxCmdDataDelay1RegValue

uint32_t soc_intel_icelake_config::EmmcRxCmdDataDelay1RegValue

Definition at line 122 of file chip.h.

◆ EmmcRxCmdDataDelay2RegValue

uint32_t soc_intel_icelake_config::EmmcRxCmdDataDelay2RegValue

Definition at line 123 of file chip.h.

◆ EmmcRxStrobeDelayRegValue

uint32_t soc_intel_icelake_config::EmmcRxStrobeDelayRegValue

Definition at line 124 of file chip.h.

◆ EmmcTxCmdDelayRegValue

uint32_t soc_intel_icelake_config::EmmcTxCmdDelayRegValue

Definition at line 119 of file chip.h.

◆ EmmcTxDataDelay1RegValue

uint32_t soc_intel_icelake_config::EmmcTxDataDelay1RegValue

Definition at line 120 of file chip.h.

◆ EmmcTxDataDelay2RegValue

uint32_t soc_intel_icelake_config::EmmcTxDataDelay2RegValue

Definition at line 121 of file chip.h.

◆ EmmcUseCustomDlls

uint8_t soc_intel_icelake_config::EmmcUseCustomDlls

Definition at line 118 of file chip.h.

◆ enable_c6dram

uint8_t soc_intel_icelake_config::enable_c6dram

Definition at line 141 of file chip.h.

◆ gen1_dec

uint32_t soc_intel_icelake_config::gen1_dec

Definition at line 32 of file chip.h.

◆ gen2_dec

uint32_t soc_intel_icelake_config::gen2_dec

Definition at line 33 of file chip.h.

◆ gen3_dec

uint32_t soc_intel_icelake_config::gen3_dec

Definition at line 34 of file chip.h.

◆ gen4_dec

uint32_t soc_intel_icelake_config::gen4_dec

Definition at line 35 of file chip.h.

◆ gpe0_dw0

uint8_t soc_intel_icelake_config::gpe0_dw0

Definition at line 27 of file chip.h.

◆ gpe0_dw1

uint8_t soc_intel_icelake_config::gpe0_dw1

Definition at line 28 of file chip.h.

◆ gpe0_dw2

uint8_t soc_intel_icelake_config::gpe0_dw2

Definition at line 29 of file chip.h.

◆ gpio_override_pm

uint8_t soc_intel_icelake_config::gpio_override_pm

Definition at line 181 of file chip.h.

◆ gpio_pm

uint8_t soc_intel_icelake_config::gpio_pm[TOTAL_GPIO_COMM]

Definition at line 193 of file chip.h.

◆ Heci3Enabled

uint8_t soc_intel_icelake_config::Heci3Enabled

Definition at line 130 of file chip.h.

◆ pch_isclk

uint8_t soc_intel_icelake_config::pch_isclk

Definition at line 171 of file chip.h.

◆ PchHdaAudioLinkDmic0

uint8_t soc_intel_icelake_config::PchHdaAudioLinkDmic0

Definition at line 92 of file chip.h.

◆ PchHdaAudioLinkDmic1

uint8_t soc_intel_icelake_config::PchHdaAudioLinkDmic1

Definition at line 93 of file chip.h.

◆ PchHdaAudioLinkHda

uint8_t soc_intel_icelake_config::PchHdaAudioLinkHda

Definition at line 91 of file chip.h.

◆ PchHdaAudioLinkSndw1

uint8_t soc_intel_icelake_config::PchHdaAudioLinkSndw1

Definition at line 97 of file chip.h.

◆ PchHdaAudioLinkSndw2

uint8_t soc_intel_icelake_config::PchHdaAudioLinkSndw2

Definition at line 98 of file chip.h.

◆ PchHdaAudioLinkSndw3

uint8_t soc_intel_icelake_config::PchHdaAudioLinkSndw3

Definition at line 99 of file chip.h.

◆ PchHdaAudioLinkSndw4

uint8_t soc_intel_icelake_config::PchHdaAudioLinkSndw4

Definition at line 100 of file chip.h.

◆ PchHdaAudioLinkSsp0

uint8_t soc_intel_icelake_config::PchHdaAudioLinkSsp0

Definition at line 94 of file chip.h.

◆ PchHdaAudioLinkSsp1

uint8_t soc_intel_icelake_config::PchHdaAudioLinkSsp1

Definition at line 95 of file chip.h.

◆ PchHdaAudioLinkSsp2

uint8_t soc_intel_icelake_config::PchHdaAudioLinkSsp2

Definition at line 96 of file chip.h.

◆ PchHdaDspEnable

uint8_t soc_intel_icelake_config::PchHdaDspEnable

Definition at line 88 of file chip.h.

◆ PchHdaEnable

uint8_t soc_intel_icelake_config::PchHdaEnable

Definition at line 87 of file chip.h.

◆ PcieClkSrcClkReq

uint8_t soc_intel_icelake_config::PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]

Definition at line 110 of file chip.h.

◆ PcieClkSrcUsage

uint8_t soc_intel_icelake_config::PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]

Definition at line 107 of file chip.h.

◆ PcieRpEnable

uint8_t soc_intel_icelake_config::PcieRpEnable[CONFIG_MAX_ROOT_PORTS]

Definition at line 103 of file chip.h.

◆ RMT

uint8_t soc_intel_icelake_config::RMT

Definition at line 69 of file chip.h.

◆ s0ix_enable

int soc_intel_icelake_config::s0ix_enable

Definition at line 38 of file chip.h.

◆ 

enum { ... } soc_intel_icelake_config::SaGv

◆ SataEnable

uint8_t soc_intel_icelake_config::SataEnable

Definition at line 80 of file chip.h.

◆ SataMode

uint8_t soc_intel_icelake_config::SataMode

Definition at line 81 of file chip.h.

◆ SataPortsDevSlp

uint8_t soc_intel_icelake_config::SataPortsDevSlp[8]

Definition at line 84 of file chip.h.

◆ SataPortsEnable

uint8_t soc_intel_icelake_config::SataPortsEnable[8]

Definition at line 83 of file chip.h.

◆ SataSalpSupport

uint8_t soc_intel_icelake_config::SataSalpSupport

Definition at line 82 of file chip.h.

◆ ScsEmmcHs400Enabled

uint8_t soc_intel_icelake_config::ScsEmmcHs400Enabled

Definition at line 116 of file chip.h.

◆ sdcard_cd_gpio

unsigned int soc_intel_icelake_config::sdcard_cd_gpio

Definition at line 168 of file chip.h.

◆ SdCardPowerEnableActiveHigh

uint8_t soc_intel_icelake_config::SdCardPowerEnableActiveHigh

Definition at line 127 of file chip.h.

◆ SerialIoGSpiCsMode

uint8_t soc_intel_icelake_config::SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]

Definition at line 159 of file chip.h.

◆ SerialIoGSpiCsState

uint8_t soc_intel_icelake_config::SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]

Definition at line 165 of file chip.h.

◆ SerialIoGSpiMode

uint8_t soc_intel_icelake_config::SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]

Definition at line 152 of file chip.h.

◆ SerialIoI2cMode

uint8_t soc_intel_icelake_config::SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]

Definition at line 151 of file chip.h.

◆ SerialIoUartMode

uint8_t soc_intel_icelake_config::SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]

Definition at line 153 of file chip.h.

◆ SkipExtGfxScan

uint8_t soc_intel_icelake_config::SkipExtGfxScan

Definition at line 133 of file chip.h.

◆ SmbusEnable

uint8_t soc_intel_icelake_config::SmbusEnable

Definition at line 113 of file chip.h.

◆ tcc_offset

uint32_t soc_intel_icelake_config::tcc_offset

Definition at line 55 of file chip.h.

◆ usb2_ports

struct usb2_port_config soc_intel_icelake_config::usb2_ports[16]

Definition at line 69 of file chip.h.

◆ usb2_wake_enable_bitmap

uint16_t soc_intel_icelake_config::usb2_wake_enable_bitmap

Definition at line 75 of file chip.h.

◆ usb3_ports

struct usb3_port_config soc_intel_icelake_config::usb3_ports[10]

Definition at line 69 of file chip.h.

◆ usb3_wake_enable_bitmap

uint16_t soc_intel_icelake_config::usb3_wake_enable_bitmap

Definition at line 77 of file chip.h.

The documentation for this struct was generated from the following file: