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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | MAX_DRAM_ADDRESS 0xF8000000 |
#define | PMUGRF_BASE 0xff320000 |
#define | PMUSGRF_BASE 0xff330000 |
#define | PMUCRU_BASE 0xff750000 |
#define | CRU_BASE 0xff760000 |
#define | GRF_BASE 0xff770000 |
#define | TIMER0_BASE 0xff850000 |
#define | EMMC_BASE 0xfe330000 |
#define | SDMMC_BASE 0xfe320000 |
#define | GPIO0_BASE 0xff720000 |
#define | GPIO1_BASE 0xff730000 |
#define | GPIO2_BASE 0xff780000 |
#define | GPIO3_BASE 0xff788000 |
#define | GPIO4_BASE 0xff790000 |
#define | I2C0_BASE 0xff3c0000 |
#define | I2C1_BASE 0xff110000 |
#define | I2C2_BASE 0xff120000 |
#define | I2C3_BASE 0xff130000 |
#define | I2C4_BASE 0xff3d0000 |
#define | I2C5_BASE 0xff140000 |
#define | I2C6_BASE 0xff150000 |
#define | I2C7_BASE 0xff160000 |
#define | I2C8_BASE 0xff3e0000 |
#define | UART0_BASE 0xff180000 |
#define | UART1_BASE 0xff190000 |
#define | UART2_BASE 0xff1a0000 |
#define | UART3_BASE 0xff1b0000 |
#define | UART4_BASE 0xff370000 |
#define | SPI0_BASE 0xff1c0000 |
#define | SPI1_BASE 0xff1d0000 |
#define | SPI2_BASE 0xff1e0000 |
#define | SPI3_BASE 0xff350000 |
#define | SPI4_BASE 0xff1f0000 |
#define | SPI5_BASE 0xff200000 |
#define | TSADC_BASE 0xff260000 |
#define | SARADC_BASE 0xff100000 |
#define | RK_PWM_BASE 0xff420000 |
#define | EDP_BASE 0xff970000 |
#define | MIPI0_BASE 0xff960000 |
#define | MIPI1_BASE 0xff968000 |
#define | VOP_BIG_BASE 0xff900000 /* corresponds to vop_id 0 */ |
#define | VOP_LIT_BASE 0xff8f0000 /* corresponds to vop_id 1 */ |
#define | DDRC0_BASE_ADDR 0xffa80000 |
#define | SERVER_MSCH0_BASE_ADDR 0xffa84000 |
#define | DDRC1_BASE_ADDR 0xffa88000 |
#define | SERVER_MSCH1_BASE_ADDR 0xffa8c000 |
#define | CIC_BASE_ADDR 0xff620000 |
#define | USB_OTG0_DWC3_BASE 0xfe80c100 |
#define | USB_OTG1_DWC3_BASE 0xfe90c100 |
#define | USB_OTG0_TCPHY_BASE 0xff7c0000 |
#define | USB_OTG1_TCPHY_BASE 0xff800000 |
#define | IC_BASES |
#define CIC_BASE_ADDR 0xff620000 |
Definition at line 59 of file addressmap.h.
#define CRU_BASE 0xff760000 |
Definition at line 10 of file addressmap.h.
#define DDRC0_BASE_ADDR 0xffa80000 |
Definition at line 55 of file addressmap.h.
#define DDRC1_BASE_ADDR 0xffa88000 |
Definition at line 57 of file addressmap.h.
#define EDP_BASE 0xff970000 |
Definition at line 48 of file addressmap.h.
#define EMMC_BASE 0xfe330000 |
Definition at line 13 of file addressmap.h.
#define GPIO0_BASE 0xff720000 |
Definition at line 16 of file addressmap.h.
#define GPIO1_BASE 0xff730000 |
Definition at line 17 of file addressmap.h.
#define GPIO2_BASE 0xff780000 |
Definition at line 18 of file addressmap.h.
#define GPIO3_BASE 0xff788000 |
Definition at line 19 of file addressmap.h.
#define GPIO4_BASE 0xff790000 |
Definition at line 20 of file addressmap.h.
#define GRF_BASE 0xff770000 |
Definition at line 11 of file addressmap.h.
#define I2C0_BASE 0xff3c0000 |
Definition at line 22 of file addressmap.h.
#define I2C1_BASE 0xff110000 |
Definition at line 23 of file addressmap.h.
#define I2C2_BASE 0xff120000 |
Definition at line 24 of file addressmap.h.
#define I2C3_BASE 0xff130000 |
Definition at line 25 of file addressmap.h.
#define I2C4_BASE 0xff3d0000 |
Definition at line 26 of file addressmap.h.
#define I2C5_BASE 0xff140000 |
Definition at line 27 of file addressmap.h.
#define I2C6_BASE 0xff150000 |
Definition at line 28 of file addressmap.h.
#define I2C7_BASE 0xff160000 |
Definition at line 29 of file addressmap.h.
#define I2C8_BASE 0xff3e0000 |
Definition at line 30 of file addressmap.h.
#define IC_BASES |
Definition at line 66 of file addressmap.h.
#define MAX_DRAM_ADDRESS 0xF8000000 |
Definition at line 6 of file addressmap.h.
#define MIPI0_BASE 0xff960000 |
Definition at line 49 of file addressmap.h.
#define MIPI1_BASE 0xff968000 |
Definition at line 50 of file addressmap.h.
#define PMUCRU_BASE 0xff750000 |
Definition at line 9 of file addressmap.h.
#define PMUGRF_BASE 0xff320000 |
Definition at line 7 of file addressmap.h.
#define PMUSGRF_BASE 0xff330000 |
Definition at line 8 of file addressmap.h.
#define RK_PWM_BASE 0xff420000 |
Definition at line 47 of file addressmap.h.
#define SARADC_BASE 0xff100000 |
Definition at line 46 of file addressmap.h.
#define SDMMC_BASE 0xfe320000 |
Definition at line 14 of file addressmap.h.
#define SERVER_MSCH0_BASE_ADDR 0xffa84000 |
Definition at line 56 of file addressmap.h.
#define SERVER_MSCH1_BASE_ADDR 0xffa8c000 |
Definition at line 58 of file addressmap.h.
#define SPI0_BASE 0xff1c0000 |
Definition at line 38 of file addressmap.h.
#define SPI1_BASE 0xff1d0000 |
Definition at line 39 of file addressmap.h.
#define SPI2_BASE 0xff1e0000 |
Definition at line 40 of file addressmap.h.
#define SPI3_BASE 0xff350000 |
Definition at line 41 of file addressmap.h.
#define SPI4_BASE 0xff1f0000 |
Definition at line 42 of file addressmap.h.
#define SPI5_BASE 0xff200000 |
Definition at line 43 of file addressmap.h.
#define TIMER0_BASE 0xff850000 |
Definition at line 12 of file addressmap.h.
#define TSADC_BASE 0xff260000 |
Definition at line 45 of file addressmap.h.
#define UART0_BASE 0xff180000 |
Definition at line 32 of file addressmap.h.
#define UART1_BASE 0xff190000 |
Definition at line 33 of file addressmap.h.
#define UART2_BASE 0xff1a0000 |
Definition at line 34 of file addressmap.h.
#define UART3_BASE 0xff1b0000 |
Definition at line 35 of file addressmap.h.
#define UART4_BASE 0xff370000 |
Definition at line 36 of file addressmap.h.
#define USB_OTG0_DWC3_BASE 0xfe80c100 |
Definition at line 61 of file addressmap.h.
#define USB_OTG0_TCPHY_BASE 0xff7c0000 |
Definition at line 63 of file addressmap.h.
#define USB_OTG1_DWC3_BASE 0xfe90c100 |
Definition at line 62 of file addressmap.h.
#define USB_OTG1_TCPHY_BASE 0xff800000 |
Definition at line 64 of file addressmap.h.
#define VOP_BIG_BASE 0xff900000 /* corresponds to vop_id 0 */ |
Definition at line 52 of file addressmap.h.
#define VOP_LIT_BASE 0xff8f0000 /* corresponds to vop_id 1 */ |
Definition at line 53 of file addressmap.h.