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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
| #define | BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) |
| BIOS_SIZE_{1,2,4,8,16}M. More... | |
| #define | SPREAD_SPECTRUM 0 |
| 0 - Disable Spread Spectrum function 1 - Enable Spread Spectrum function More... | |
| #define | HPET_TIMER 1 |
| #define | USB_CONFIG 0x7F |
| bit[0-6] used to control USB 0 - Disable 1 - Enable Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 More... | |
| #define | PCI_CLOCK_CTRL 0x1F |
| bit[0-4] used for PCI Slots Clock Control, 0 - disable 1 - enable PCI SLOT 0 define at BIT0 PCI SLOT 1 define at BIT1 PCI SLOT 2 define at BIT2 PCI SLOT 3 define at BIT3 PCI SLOT 4 define at BIT4 More... | |
| #define | SATA_CONTROLLER CIMX_OPTION_ENABLED |
| INCHIP Sata Controller. More... | |
| #define | SATA_MODE CONFIG_SB800_SATA_MODE |
| INCHIP Sata Controller Mode NOTE: DO NOT ALLOW SATA & IDE use same mode. More... | |
| #define | IDE_LEGACY_MODE 0 |
| INCHIP Sata IDE Controller Mode. More... | |
| #define | IDE_NATIVE_MODE 1 |
| #define | SATA_IDE_MODE IDE_LEGACY_MODE |
| INCHIP Sata IDE Controller Mode NOTE: DO NOT ALLOW SATA & IDE use same mode. More... | |
| #define | EXTERNAL_CLOCK 0x00 |
| 00/10: Reference clock from crystal oscillator via PAD_XTALI and PAD_XTALO More... | |
| #define | INTERNAL_CLOCK 0x01 |
| 01/11: Reference clock from internal clock through CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL More... | |
| #define | SATA_CLOCK_SOURCE INTERNAL_CLOCK |
| #define | SATA_PORT_MULT_CAP_RESERVED 1 |
| 1 ON, 0 0FF More... | |
| #define | AZALIA_AUTO 0 |
| Detect Azalia controller automatically. More... | |
| #define | AZALIA_DISABLE 1 |
| Disable Azalia controller. More... | |
| #define | AZALIA_ENABLE 2 |
| Enable Azalia controller. More... | |
| #define | AZALIA_CONTROLLER AZALIA_AUTO |
| INCHIP HDA controller. More... | |
| #define | AZALIA_PIN_CONFIG 1 |
| 0 - disable 1 - enable More... | |
| #define | AZALIA_SDIN_PIN 0x2A |
| SDIN0 is defined at BIT0 & BIT1 00 - GPIO PIN 01 - Reserved 10 - As a Azalia SDIN pin SDIN1 is defined at BIT2 & BIT3 SDIN2 is defined at BIT4 & BIT5 SDIN3 is defined at BIT6 & BIT7. More... | |
| #define | GPP_CONTROLLER CIMX_OPTION_ENABLED |
| #define | GPP_CFGMODE GPP_CFGMODE_X1111 |
| GPP Link Configuration four possible configuration: GPP_CFGMODE_X4000 GPP_CFGMODE_X2200 GPP_CFGMODE_X2110 GPP_CFGMODE_X1111. More... | |
| #define | NB_SB_GEN2 TRUE |
| 0 - Disable 1 - Enable More... | |
| #define | SB_GPP_GEN2 TRUE |
| 0 - Disable 1 - Enable More... | |
| #define | SB_GPP_UNHIDE_PORTS FALSE |
| TRUE - ports visible always, even port empty FALSE - ports invisible if port empty. More... | |
| #define | GEC_CONFIG 0 |
| 0 - Enable 1 - Disable More... | |
| #define AZALIA_AUTO 0 |
Detect Azalia controller automatically.
Definition at line 121 of file platform_cfg.h.
| #define AZALIA_CONTROLLER AZALIA_AUTO |
INCHIP HDA controller.
Definition at line 128 of file platform_cfg.h.
| #define AZALIA_DISABLE 1 |
Disable Azalia controller.
Definition at line 122 of file platform_cfg.h.
| #define AZALIA_ENABLE 2 |
Enable Azalia controller.
Definition at line 123 of file platform_cfg.h.
| #define AZALIA_PIN_CONFIG 1 |
0 - disable 1 - enable
Definition at line 136 of file platform_cfg.h.
| #define AZALIA_SDIN_PIN 0x2A |
SDIN0 is defined at BIT0 & BIT1 00 - GPIO PIN 01 - Reserved 10 - As a Azalia SDIN pin SDIN1 is defined at BIT2 & BIT3 SDIN2 is defined at BIT4 & BIT5 SDIN3 is defined at BIT6 & BIT7.
Definition at line 150 of file platform_cfg.h.
| #define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) |
BIOS_SIZE_{1,2,4,8,16}M.
In SB800, default ROM size is 1M Bytes, if your platform ROM bigger than 1M you have to set the ROM size outside CIMx module and before AGESA module get call.
Definition at line 15 of file platform_cfg.h.
| #define EXTERNAL_CLOCK 0x00 |
00/10: Reference clock from crystal oscillator via PAD_XTALI and PAD_XTALO
Definition at line 97 of file platform_cfg.h.
| #define GEC_CONFIG 0 |
0 - Enable 1 - Disable
Definition at line 194 of file platform_cfg.h.
| #define GPP_CFGMODE GPP_CFGMODE_X1111 |
GPP Link Configuration four possible configuration: GPP_CFGMODE_X4000 GPP_CFGMODE_X2200 GPP_CFGMODE_X2110 GPP_CFGMODE_X1111.
Definition at line 166 of file platform_cfg.h.
| #define GPP_CONTROLLER CIMX_OPTION_ENABLED |
Definition at line 155 of file platform_cfg.h.
| #define HPET_TIMER 1 |
Definition at line 32 of file platform_cfg.h.
| #define IDE_LEGACY_MODE 0 |
INCHIP Sata IDE Controller Mode.
Definition at line 78 of file platform_cfg.h.
| #define IDE_NATIVE_MODE 1 |
Definition at line 79 of file platform_cfg.h.
| #define INTERNAL_CLOCK 0x01 |
01/11: Reference clock from internal clock through CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
Definition at line 98 of file platform_cfg.h.
| #define NB_SB_GEN2 TRUE |
0 - Disable 1 - Enable
Definition at line 173 of file platform_cfg.h.
| #define PCI_CLOCK_CTRL 0x1F |
bit[0-4] used for PCI Slots Clock Control, 0 - disable 1 - enable PCI SLOT 0 define at BIT0 PCI SLOT 1 define at BIT1 PCI SLOT 2 define at BIT2 PCI SLOT 3 define at BIT3 PCI SLOT 4 define at BIT4
Definition at line 60 of file platform_cfg.h.
| #define SATA_CLOCK_SOURCE INTERNAL_CLOCK |
Definition at line 103 of file platform_cfg.h.
| #define SATA_CONTROLLER CIMX_OPTION_ENABLED |
INCHIP Sata Controller.
Definition at line 66 of file platform_cfg.h.
| #define SATA_IDE_MODE IDE_LEGACY_MODE |
INCHIP Sata IDE Controller Mode NOTE: DO NOT ALLOW SATA & IDE use same mode.
Definition at line 86 of file platform_cfg.h.
| #define SATA_MODE CONFIG_SB800_SATA_MODE |
INCHIP Sata Controller Mode NOTE: DO NOT ALLOW SATA & IDE use same mode.
Definition at line 73 of file platform_cfg.h.
| #define SATA_PORT_MULT_CAP_RESERVED 1 |
1 ON, 0 0FF
Definition at line 109 of file platform_cfg.h.
| #define SB_GPP_GEN2 TRUE |
0 - Disable 1 - Enable
Definition at line 180 of file platform_cfg.h.
| #define SB_GPP_UNHIDE_PORTS FALSE |
TRUE - ports visible always, even port empty FALSE - ports invisible if port empty.
Definition at line 187 of file platform_cfg.h.
| #define SPREAD_SPECTRUM 0 |
0 - Disable Spread Spectrum function 1 - Enable Spread Spectrum function
Definition at line 24 of file platform_cfg.h.
| #define USB_CONFIG 0x7F |
bit[0-6] used to control USB 0 - Disable 1 - Enable Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
Definition at line 47 of file platform_cfg.h.
1.9.1