coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
iomap.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _SOC_IOMAP_H_
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#define _SOC_IOMAP_H_
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#define MAP_ENTRY(reg_, is_64_, is_limit_, mask_bits_, desc_) \
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{ \
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.reg = reg_, .is_64_bit = is_64_, .is_limit = is_limit_, \
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.mask_bits = mask_bits_, .description = desc_, \
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}
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#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, 0, desc_)
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#define MAP_ENTRY_LIMIT_64(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 1, 1, mask_bits_, desc_)
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#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 0, desc_)
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#define MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_)
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// SPI BAR0 MMIO base address
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#define SPI_BASE_ADDRESS 0xfe010000
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#define SPI_BASE_SIZE 0x1000
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#define TCO_BASE_ADDRESS 0x400
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#define ACPI_BASE_ADDRESS CONFIG_INTEL_ACPI_BASE_ADDRESS
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#define ACPI_BASE_SIZE 0x100
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/* Video RAM */
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#define VGA_BASE_ADDRESS 0xa0000
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#define VGA_BASE_SIZE 0x20000
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#define HECI1_BASE_ADDRESS 0xfed1a000
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#define PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS
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#define PCH_PWRM_BASE_SIZE 0x10000
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#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
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#define GPIO_BASE_SIZE 0x10000
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#endif
/* _SOC_IOMAP_H_ */
src
soc
intel
xeon_sp
include
soc
iomap.h
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