Go to the source code of this file.
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#define | MAP_ENTRY(reg_, is_64_, is_limit_, mask_bits_, desc_) |
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#define | MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, 0, desc_) |
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#define | MAP_ENTRY_LIMIT_64(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 1, 1, mask_bits_, desc_) |
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#define | MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 0, desc_) |
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#define | MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_) |
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#define | SPI_BASE_ADDRESS 0xfe010000 |
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#define | SPI_BASE_SIZE 0x1000 |
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#define | TCO_BASE_ADDRESS 0x400 |
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#define | ACPI_BASE_ADDRESS CONFIG_INTEL_ACPI_BASE_ADDRESS |
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#define | ACPI_BASE_SIZE 0x100 |
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#define | VGA_BASE_ADDRESS 0xa0000 |
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#define | VGA_BASE_SIZE 0x20000 |
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#define | HECI1_BASE_ADDRESS 0xfed1a000 |
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#define | PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS |
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#define | PCH_PWRM_BASE_SIZE 0x10000 |
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#define | P2SB_BAR CONFIG_PCR_BASE_ADDRESS |
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#define | GPIO_BASE_SIZE 0x10000 |
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◆ ACPI_BASE_ADDRESS
#define ACPI_BASE_ADDRESS CONFIG_INTEL_ACPI_BASE_ADDRESS |
◆ ACPI_BASE_SIZE
#define ACPI_BASE_SIZE 0x100 |
◆ GPIO_BASE_SIZE
#define GPIO_BASE_SIZE 0x10000 |
◆ HECI1_BASE_ADDRESS
#define HECI1_BASE_ADDRESS 0xfed1a000 |
◆ MAP_ENTRY
#define MAP_ENTRY |
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reg_, |
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is_64_, |
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is_limit_, |
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mask_bits_, |
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desc_ |
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) |
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Value: { \
.reg = reg_, .is_64_bit = is_64_, .is_limit = is_limit_, \
.mask_bits = mask_bits_, .description = desc_, \
}
Definition at line 6 of file iomap.h.
◆ MAP_ENTRY_BASE_32
#define MAP_ENTRY_BASE_32 |
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reg_, |
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desc_ |
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| MAP_ENTRY(reg_, 0, 0, 0, desc_) |
◆ MAP_ENTRY_BASE_64
#define MAP_ENTRY_BASE_64 |
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reg_, |
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desc_ |
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| MAP_ENTRY(reg_, 1, 0, 0, desc_) |
◆ MAP_ENTRY_LIMIT_32
#define MAP_ENTRY_LIMIT_32 |
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reg_, |
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mask_bits_, |
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desc_ |
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| MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_) |
◆ MAP_ENTRY_LIMIT_64
#define MAP_ENTRY_LIMIT_64 |
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reg_, |
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mask_bits_, |
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desc_ |
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| MAP_ENTRY(reg_, 1, 1, mask_bits_, desc_) |
◆ P2SB_BAR
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS |
◆ PCH_PWRM_BASE_ADDRESS
#define PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS |
◆ PCH_PWRM_BASE_SIZE
#define PCH_PWRM_BASE_SIZE 0x10000 |
◆ SPI_BASE_ADDRESS
#define SPI_BASE_ADDRESS 0xfe010000 |
◆ SPI_BASE_SIZE
#define SPI_BASE_SIZE 0x1000 |
◆ TCO_BASE_ADDRESS
#define TCO_BASE_ADDRESS 0x400 |
◆ VGA_BASE_ADDRESS
#define VGA_BASE_ADDRESS 0xa0000 |
◆ VGA_BASE_SIZE
#define VGA_BASE_SIZE 0x20000 |