coreboot
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dptx_reg.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_MEDIATEK_MT8195_DRTX_REG_H
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#define SOC_MEDIATEK_MT8195_DRTX_REG_H
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#define TOP_OFFSET 0x2000
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#define ENC0_OFFSET 0x3000
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#define ENC1_OFFSET 0x3200
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#define TRANS_OFFSET 0x3400
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#define AUX_OFFSET 0x3600
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#define SEC_OFFSET 0x4000
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#define REG_3000_DP_ENCODER0_P0 0x3000
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#define LANE_NUM_DP_ENCODER0_P0_FLDMASK 0x3
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#define LANE_NUM_DP_ENCODER0_P0_FLDMASK_POS 0
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#define LANE_NUM_DP_ENCODER0_P0_FLDMASK_LEN 2
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#define VIDEO_MUTE_SW_DP_ENCODER0_P0_FLDMASK 0x4
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#define VIDEO_MUTE_SW_DP_ENCODER0_P0_FLDMASK_POS 2
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#define VIDEO_MUTE_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VIDEO_MUTE_SEL_DP_ENCODER0_P0_FLDMASK 0x8
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#define VIDEO_MUTE_SEL_DP_ENCODER0_P0_FLDMASK_POS 3
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#define VIDEO_MUTE_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define ENHANCED_FRAME_EN_DP_ENCODER0_P0_FLDMASK 0x10
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#define ENHANCED_FRAME_EN_DP_ENCODER0_P0_FLDMASK_POS 4
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#define ENHANCED_FRAME_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define HDCP_FRAME_EN_DP_ENCODER0_P0_FLDMASK 0x20
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#define HDCP_FRAME_EN_DP_ENCODER0_P0_FLDMASK_POS 5
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#define HDCP_FRAME_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define IDP_EN_DP_ENCODER0_P0_FLDMASK 0x40
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#define IDP_EN_DP_ENCODER0_P0_FLDMASK_POS 6
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#define IDP_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define BS_SYMBOL_CNT_RESET_DP_ENCODER0_P0_FLDMASK 0x80
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#define BS_SYMBOL_CNT_RESET_DP_ENCODER0_P0_FLDMASK_POS 7
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#define BS_SYMBOL_CNT_RESET_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define MIXER_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK 0xff00
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#define MIXER_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK_POS 8
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#define MIXER_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK_LEN 8
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#define REG_3004_DP_ENCODER0_P0 0x3004
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#define MIXER_STUFF_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK 0xff
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#define MIXER_STUFF_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK_POS 0
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#define MIXER_STUFF_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK_LEN 8
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#define VIDEO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK 0x100
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#define VIDEO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK_POS 8
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#define VIDEO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define DP_TX_ENCODER_4P_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x200
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#define DP_TX_ENCODER_4P_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 9
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#define DP_TX_ENCODER_4P_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define MIXER_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x400
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#define MIXER_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 10
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#define MIXER_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VIDEO_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x800
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#define VIDEO_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 11
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#define VIDEO_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VIDEO_PATTERN_GEN_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x1000
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#define VIDEO_PATTERN_GEN_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 12
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#define VIDEO_PATTERN_GEN_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define SDP_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x2000
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#define SDP_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 13
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#define SDP_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define DP_TX_MUX_DP_ENCODER0_P0_FLDMASK 0x4000
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#define DP_TX_MUX_DP_ENCODER0_P0_FLDMASK_POS 14
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#define DP_TX_MUX_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define MIXER_FSM_RESET_DP_ENCODER0_P0_FLDMASK 0x8000
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#define MIXER_FSM_RESET_DP_ENCODER0_P0_FLDMASK_POS 15
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#define MIXER_FSM_RESET_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define REG_3008_DP_ENCODER0_P0 0x3008
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#define VIDEO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK 0xffff
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#define VIDEO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK_POS 0
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#define VIDEO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK_LEN 16
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#define REG_300C_DP_ENCODER0_P0 0x300C
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#define VIDEO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK 0xff
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#define VIDEO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK_POS 0
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#define VIDEO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK_LEN 8
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#define VIDEO_M_CODE_PULSE_DP_ENCODER0_P0_FLDMASK 0x100
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#define VIDEO_M_CODE_PULSE_DP_ENCODER0_P0_FLDMASK_POS 8
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#define VIDEO_M_CODE_PULSE_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define COMPRESSEDSTREAM_FLAG_DP_ENCODER0_P0_FLDMASK 0x200
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#define COMPRESSEDSTREAM_FLAG_DP_ENCODER0_P0_FLDMASK_POS 9
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#define COMPRESSEDSTREAM_FLAG_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define SDP_SPLIT_EN_DP_ENCODER0_P0_FLDMASK 0x400
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#define SDP_SPLIT_EN_DP_ENCODER0_P0_FLDMASK_POS 10
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#define SDP_SPLIT_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define SDP_SPLIT_FIFO_RST_DP_ENCODER0_P0_FLDMASK 0x800
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#define SDP_SPLIT_FIFO_RST_DP_ENCODER0_P0_FLDMASK_POS 11
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#define SDP_SPLIT_FIFO_RST_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VIDEO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK 0x7000
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#define VIDEO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK_POS 12
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#define VIDEO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK_LEN 3
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#define SDP_AUDIO_ONE_SAMPLE_MODE_DP_ENCODER0_P0_FLDMASK 0x8000
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#define SDP_AUDIO_ONE_SAMPLE_MODE_DP_ENCODER0_P0_FLDMASK_POS 15
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#define SDP_AUDIO_ONE_SAMPLE_MODE_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define REG_3010_DP_ENCODER0_P0 0x3010
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#define HTOTAL_SW_DP_ENCODER0_P0_FLDMASK 0xffff
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#define HTOTAL_SW_DP_ENCODER0_P0_FLDMASK_PO 0
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#define HTOTAL_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
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#define REG_3014_DP_ENCODER0_P0 0x3014
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#define VTOTAL_SW_DP_ENCODER0_P0_FLDMASK 0xffff
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#define VTOTAL_SW_DP_ENCODER0_P0_FLDMASK_POS 0
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#define VTOTAL_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
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#define REG_3018_DP_ENCODER0_P0 0x3018
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#define HSTART_SW_DP_ENCODER0_P0_FLDMASK 0xffff
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#define HSTART_SW_DP_ENCODER0_P0_FLDMASK_POS 0
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#define HSTART_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
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#define REG_301C_DP_ENCODER0_P0 0x301C
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#define VSTART_SW_DP_ENCODER0_P0_FLDMASK 0xffff
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#define VSTART_SW_DP_ENCODER0_P0_FLDMASK_POS 0
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#define VSTART_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
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#define REG_3020_DP_ENCODER0_P0 0x3020
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#define HWIDTH_SW_DP_ENCODER0_P0_FLDMASK 0xffff
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#define HWIDTH_SW_DP_ENCODER0_P0_FLDMASK_POS 0
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#define HWIDTH_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
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#define REG_3024_DP_ENCODER0_P0 0x3024
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#define VHEIGHT_SW_DP_ENCODER0_P0_FLDMASK 0xffff
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#define VHEIGHT_SW_DP_ENCODER0_P0_FLDMASK_POS 0
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#define VHEIGHT_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
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#define REG_3028_DP_ENCODER0_P0 0x3028
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#define HSW_SW_DP_ENCODER0_P0_FLDMASK 0x7fff
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#define HSW_SW_DP_ENCODER0_P0_FLDMASK_POS 0
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#define HSW_SW_DP_ENCODER0_P0_FLDMASK_LEN 15
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#define HSP_SW_DP_ENCODER0_P0_FLDMASK 0x8000
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#define HSP_SW_DP_ENCODER0_P0_FLDMASK_POS 15
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#define HSP_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define REG_302C_DP_ENCODER0_P0 0x302C
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#define VSW_SW_DP_ENCODER0_P0_FLDMASK 0x7fff
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#define VSW_SW_DP_ENCODER0_P0_FLDMASK_POS 0
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#define VSW_SW_DP_ENCODER0_P0_FLDMASK_LEN 15
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#define VSP_SW_DP_ENCODER0_P0_FLDMASK 0x8000
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#define VSP_SW_DP_ENCODER0_P0_FLDMASK_POS 15
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#define VSP_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define REG_3030_DP_ENCODER0_P0 0x3030
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#define HTOTAL_SEL_DP_ENCODER0_P0_FLDMASK 0x1
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#define HTOTAL_SEL_DP_ENCODER0_P0_FLDMASK_POS 0
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#define HTOTAL_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VTOTAL_SEL_DP_ENCODER0_P0_FLDMASK 0x2
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#define VTOTAL_SEL_DP_ENCODER0_P0_FLDMASK_POS 1
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#define VTOTAL_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define HSTART_SEL_DP_ENCODER0_P0_FLDMASK 0x4
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#define HSTART_SEL_DP_ENCODER0_P0_FLDMASK_POS 2
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#define HSTART_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VSTART_SEL_DP_ENCODER0_P0_FLDMASK 0x8
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#define VSTART_SEL_DP_ENCODER0_P0_FLDMASK_POS 3
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#define VSTART_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define HWIDTH_SEL_DP_ENCODER0_P0_FLDMASK 0x10
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#define HWIDTH_SEL_DP_ENCODER0_P0_FLDMASK_POS 4
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#define HWIDTH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VHEIGHT_SEL_DP_ENCODER0_P0_FLDMASK 0x20
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#define VHEIGHT_SEL_DP_ENCODER0_P0_FLDMASK_POS 5
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#define VHEIGHT_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define HSP_SEL_DP_ENCODER0_P0_FLDMASK 0x40
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#define HSP_SEL_DP_ENCODER0_P0_FLDMASK_POS 6
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#define HSP_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define HSW_SEL_DP_ENCODER0_P0_FLDMASK 0x80
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#define HSW_SEL_DP_ENCODER0_P0_FLDMASK_POS 7
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#define HSW_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VSP_SEL_DP_ENCODER0_P0_FLDMASK 0x100
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#define VSP_SEL_DP_ENCODER0_P0_FLDMASK_POS 8
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#define VSP_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VSW_SEL_DP_ENCODER0_P0_FLDMASK 0x200
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#define VSW_SEL_DP_ENCODER0_P0_FLDMASK_POS 9
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#define VSW_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define TX_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK 0x400
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#define TX_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK_POS 10
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#define TX_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VBID_AUDIO_MUTE_FLAG_SW_DP_ENCODER0_P0_FLDMASK 0x800
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#define VBID_AUDIO_MUTE_SW_DP_ENCODER0_P0_FLDMASK_POS 11
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#define VBID_AUDIO_MUTE_FLAG_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK 0x1000
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#define VBID_AUDIO_MUTE_SEL_DP_ENCODER0_P0_FLDMASK_POS 12
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#define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VBID_INTERLACE_FLAG_SW_DP_ENCODER0_P0_FLDMASK 0x2000
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#define VBID_INTERLACE_FLAG_SW_DP_ENCODER0_P0_FLDMASK_POS 13
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#define VBID_INTERLACE_FLAG_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VBID_INTERLACE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK 0x4000
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#define VBID_INTERLACE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK_POS 14
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#define VBID_INTERLACE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define MIXER_SDP_EN_DP_ENCODER0_P0_FLDMASK 0x8000
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#define MIXER_SDP_EN_DP_ENCODER0_P0_FLDMASK_POS 15
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#define MIXER_SDP_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define REG_3034_DP_ENCODER0_P0 0x3034
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#define MISC0_DATA_DP_ENCODER0_P0_FLDMASK 0xff
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#define MISC0_DATA_DP_ENCODER0_P0_FLDMASK_POS 0
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#define MISC0_DATA_DP_ENCODER0_P0_FLDMASK_LEN 8
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#define MISC1_DATA_DP_ENCODER0_P0_FLDMASK 0xff00
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#define MISC1_DATA_DP_ENCODER0_P0_FLDMASK_POS 8
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#define MISC1_DATA_DP_ENCODER0_P0_FLDMASK_LEN 8
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#define REG_3038_DP_ENCODER0_P0 0x3038
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#define TX_VBID_SW_DP_ENCODER0_P0_FLDMASK 0xff
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#define TX_VBID_SW_DP_ENCODER0_P0_FLDMASK_POS 0
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#define TX_VBID_SW_DP_ENCODER0_P0_FLDMASK_LEN 8
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#define VIDEO_DATA_SWAP_DP_ENCODER0_P0_FLDMASK 0x700
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#define VIDEO_DATA_SWAP_DP_ENCODER0_P0_FLDMASK_POS 8
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#define VIDEO_DATA_SWAP_DP_ENCODER0_P0_FLDMASK_LEN 3
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#define VIDEO_SOURCE_SEL_DP_ENCODER0_P0_FLDMASK 0x800
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#define VIDEO_SOURCE_SEL_DP_ENCODER0_P0_FLDMASK_POS 11
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#define VIDEO_SOURCE_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define FIELD_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK 0x1000
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#define FIELD_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK_POS 12
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#define FIELD_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define FIELD_SW_DP_ENCODER0_P0_FLDMASK 0x2000
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#define FIELD_SW_DP_ENCODER0_P0_FLDMASK_POS 13
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#define FIELD_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define V3D_EN_SW_DP_ENCODER0_P0_FLDMASK 0x4000
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#define V3D_EN_SW_DP_ENCODER0_P0_FLDMASK_POS 14
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#define V3D_EN_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define V3D_LR_HW_SWAP_DP_ENCODER0_P0_FLDMASK 0x8000
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#define V3D_LR_HW_SWAP_DP_ENCODER0_P0_FLDMASK_POS 15
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#define V3D_LR_HW_SWAP_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define REG_303C_DP_ENCODER0_P0 0x303C
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#define SRAM_START_READ_THRD_DP_ENCODER0_P0_FLDMASK 0x3f
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#define SRAM_START_READ_THRD_DP_ENCODER0_P0_FLDMASK_POS 0
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#define SRAM_START_READ_THRD_DP_ENCODER0_P0_FLDMASK_LEN 6
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#define VIDEO_COLOR_DEPTH_DP_ENCODER0_P0_FLDMASK 0x700
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#define VIDEO_COLOR_DEPTH_DP_ENCODER0_P0_FLDMASK_POS 8
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#define VIDEO_COLOR_DEPTH_DP_ENCODER0_P0_FLDMASK_LEN 3
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#define PIXEL_ENCODE_FORMAT_DP_ENCODER0_P0_FLDMASK 0x7000
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#define PIXEL_ENCODE_FORMAT_DP_ENCODER0_P0_FLDMASK_POS 12
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#define PIXEL_ENCODE_FORMAT_DP_ENCODER0_P0_FLDMASK_LEN 3
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#define VIDEO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK 0x8000
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#define VIDEO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK_POS 15
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#define VIDEO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define REG_3040_DP_ENCODER0_P0 0x3040
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#define SDP_DOWN_CNT_INIT_DP_ENCODER0_P0_FLDMASK 0xfff
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#define SDP_DOWN_CNT_INIT_DP_ENCODER0_P0_FLDMASK_POS 0
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#define SDP_DOWN_CNT_INIT_DP_ENCODER0_P0_FLDMASK_LEN 12
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#define AUDIO_32CH_EN_DP_ENCODER0_P0_FLDMASK 0x1000
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#define AUDIO_32CH_EN_DP_ENCODER0_P0_FLDMASK_POS 12
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#define AUDIO_32CH_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define AUDIO_32CH_SEL_DP_ENCODER0_P0_FLDMASK 0x2000
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#define AUDIO_32CH_SEL_DP_ENCODER0_P0_FLDMASK_POS 13
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#define AUDIO_32CH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define AUDIO_16CH_EN_DP_ENCODER0_P0_FLDMASK 0x4000
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#define AUDIO_16CH_EN_DP_ENCODER0_P0_FLDMASK_POS 14
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#define AUDIO_16CH_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define AUDIO_16CH_SEL_DP_ENCODER0_P0_FLDMASK 0x8000
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#define AUDIO_16CH_SEL_DP_ENCODER0_P0_FLDMASK_POS 15
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#define AUDIO_16CH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define REG_3044_DP_ENCODER0_P0 0x3044
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#define VIDEO_N_CODE_0_DP_ENCODER0_P0_FLDMASK 0xffff
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#define VIDEO_N_CODE_0_DP_ENCODER0_P0_FLDMASK_POS 0
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#define VIDEO_N_CODE_0_DP_ENCODER0_P0_FLDMASK_LEN 16
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#define REG_3048_DP_ENCODER0_P0 0x3048
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#define VIDEO_N_CODE_1_DP_ENCODER0_P0_FLDMASK 0xff
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#define VIDEO_N_CODE_1_DP_ENCODER0_P0_FLDMASK_POS 0
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#define VIDEO_N_CODE_1_DP_ENCODER0_P0_FLDMASK_LEN 8
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#define REG_304C_DP_ENCODER0_P0 0x304C
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#define VIDEO_SRAM_MODE_DP_ENCODER0_P0_FLDMASK 0x3
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#define VIDEO_SRAM_MODE_DP_ENCODER0_P0_FLDMASK_POS 0
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#define VIDEO_SRAM_MODE_DP_ENCODER0_P0_FLDMASK_LEN 2
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#define VBID_VIDEO_MUTE_DP_ENCODER0_P0_FLDMASK 0x4
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#define VBID_VIDEO_MUTE_DP_ENCODER0_P0_FLDMASK_POS 2
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#define VBID_VIDEO_MUTE_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define VBID_VIDEO_MUTE_IDLE_PATTERN_SYNC_EN_DP_ENCODER0_P0_FLDMASK 0x8
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#define VBID_VIDEO_MUTE_IDLE_PATTERN_SYNC_EN_DP_ENCODER0_P0_FLDMASK_POS 3
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#define VBID_VIDEO_MUTE_IDLE_PATTERN_SYNC_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define HDCP_SYNC_SEL_DP_ENCODER0_P0_FLDMASK 0x10
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#define HDCP_SYNC_SEL_DP_ENCODER0_P0_FLDMASK_POS 4
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#define HDCP_SYNC_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define HDCP_SYNC_SW_DP_ENCODER0_P0_FLDMASK 0x20
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#define HDCP_SYNC_SW_DP_ENCODER0_P0_FLDMASK_POS 5
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#define HDCP_SYNC_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define SDP_VSYNC_RISING_MASK_DP_ENCODER0_P0_FLDMASK 0x100
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#define SDP_VSYNC_RISING_MASK_DP_ENCODER0_P0_FLDMASK_POS 8
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#define SDP_VSYNC_RISING_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
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#define REG_3050_DP_ENCODER0_P0 0x3050
342
#define VIDEO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK 0xffff
343
#define VIDEO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK_POS 0
344
#define VIDEO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK_LEN 16
345
346
#define REG_3054_DP_ENCODER0_P0 0x3054
347
#define VIDEO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK 0xff
348
#define VIDEO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK_POS 0
349
#define VIDEO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK_LEN 8
350
351
#define REG_3058_DP_ENCODER0_P0 0x3058
352
#define AUDIO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK 0xffff
353
#define AUDIO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK_POS 0
354
#define AUDIO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK_LEN 16
355
356
#define REG_305C_DP_ENCODER0_P0 0x305C
357
#define AUDIO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK 0xff
358
#define AUDIO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK_POS 0
359
#define AUDIO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK_LEN 8
360
361
#define REG_3060_DP_ENCODER0_P0 0x3060
362
#define NUM_INTERLACE_FRAME_DP_ENCODER0_P0_FLDMASK 0x7
363
#define NUM_INTERLACE_FRAME_DP_ENCODER0_P0_FLDMASK_POS 0
364
#define NUM_INTERLACE_FRAME_DP_ENCODER0_P0_FLDMASK_LEN 3
365
366
#define INTERLACE_DET_EVEN_EN_DP_ENCODER0_P0_FLDMASK 0x8
367
#define INTERLACE_DET_EVEN_EN_DP_ENCODER0_P0_FLDMASK_POS 3
368
#define INTERLACE_DET_EVEN_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
369
370
#define FIELD_DETECT_EN_DP_ENCODER0_P0_FLDMASK 0x10
371
#define FIELD_DETECT_EN_DP_ENCODER0_P0_FLDMASK_POS 4
372
#define FIELD_DETECT_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
373
374
#define FIELD_DETECT_UPDATE_THRD_DP_ENCODER0_P0_FLDMASK 0xff00
375
#define FIELD_DETECT_UPDATE_THRD_DP_ENCODER0_P0_FLDMASK_POS 8
376
#define FIELD_DETECT_UPDATE_THRD_DP_ENCODER0_P0_FLDMASK_LEN 8
377
378
#define REG_3064_DP_ENCODER0_P0 0x3064
379
#define HDE_NUM_LAST_DP_ENCODER0_P0_FLDMASK 0xffff
380
#define HDE_NUM_LAST_DP_ENCODER0_P0_FLDMASK_POS 0
381
#define HDE_NUM_LAST_DP_ENCODER0_P0_FLDMASK_LEN 16
382
383
#define REG_3088_DP_ENCODER0_P0 0x3088
384
#define AUDIO_DETECT_EN_DP_ENCODER0_P0_FLDMASK 0x20
385
#define AUDIO_DETECT_EN_DP_ENCODER0_P0_FLDMASK_POS 5
386
#define AUDIO_DETECT_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
387
388
#define AU_EN_DP_ENCODER0_P0_FLDMASK 0x40
389
#define AU_EN_DP_ENCODER0_P0_FLDMASK_POS 6
390
#define AU_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
391
392
#define AUDIO_8CH_EN_DP_ENCODER0_P0_FLDMASK 0x80
393
#define AUDIO_8CH_EN_DP_ENCODER0_P0_FLDMASK_POS 7
394
#define AUDIO_8CH_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
395
396
#define AUDIO_8CH_SEL_DP_ENCODER0_P0_FLDMASK 0x100
397
#define AUDIO_8CH_SEL_DP_ENCODER0_P0_FLDMASK_POS 8
398
#define AUDIO_8CH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
399
400
#define AU_GEN_EN_DP_ENCODER0_P0_FLDMASK 0x200
401
#define AU_GEN_EN_DP_ENCODER0_P0_FLDMASK_POS 9
402
#define AU_GEN_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
403
404
#define AUDIO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK 0x1000
405
#define AUDIO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK_POS 12
406
#define AUDIO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
407
408
#define DIS_ASP_DP_ENCODER0_P0_FLDMASK 0x2000
409
#define DIS_ASP_DP_ENCODER0_P0_FLDMASK_POS 13
410
#define DIS_ASP_DP_ENCODER0_P0_FLDMASK_LEN 1
411
412
#define AUDIO_2CH_EN_DP_ENCODER0_P0_FLDMASK 0x4000
413
#define AUDIO_2CH_EN_DP_ENCODER0_P0_FLDMASK_POS 14
414
#define AUDIO_2CH_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
415
416
#define AUDIO_2CH_SEL_DP_ENCODER0_P0_FLDMASK 0x8000
417
#define AUDIO_2CH_SEL_DP_ENCODER0_P0_FLDMASK_POS 15
418
#define AUDIO_2CH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
419
420
#define REG_308C_DP_ENCODER0_P0 0x308C
421
#define CH_STATUS_0_DP_ENCODER0_P0_FLDMASK 0xffff
422
#define CH_STATUS_0_DP_ENCODER0_P0_FLDMASK_POS 0
423
#define CH_STATUS_0_DP_ENCODER0_P0_FLDMASK_LEN 16
424
425
#define REG_3090_DP_ENCODER0_P0 0x3090
426
#define CH_STATUS_1_DP_ENCODER0_P0_FLDMASK 0xffff
427
#define CH_STATUS_1_DP_ENCODER0_P0_FLDMASK_POS 0
428
#define CH_STATUS_1_DP_ENCODER0_P0_FLDMASK_LEN 16
429
430
#define REG_3094_DP_ENCODER0_P0 0x3094
431
#define CH_STATUS_2_DP_ENCODER0_P0_FLDMASK 0xff
432
#define CH_STATUS_2_DP_ENCODER0_P0_FLDMASK_POS 0
433
#define CH_STATUS_2_DP_ENCODER0_P0_FLDMASK_LEN 8
434
435
#define REG_3098_DP_ENCODER0_P0 0x3098
436
#define USER_DATA_0_DP_ENCODER0_P0_FLDMASK 0xffff
437
#define USER_DATA_0_DP_ENCODER0_P0_FLDMASK_POS 0
438
#define USER_DATA_0_DP_ENCODER0_P0_FLDMASK_LEN 16
439
440
#define REG_309C_DP_ENCODER0_P0 0x309C
441
#define USER_DATA_1_DP_ENCODER0_P0_FLDMASK 0xffff
442
#define USER_DATA_1_DP_ENCODER0_P0_FLDMASK_POS 0
443
#define USER_DATA_1_DP_ENCODER0_P0_FLDMASK_LEN 16
444
445
#define REG_30A0_DP_ENCODER0_P0 0x30A0
446
#define USER_DATA_2_DP_ENCODER0_P0_FLDMASK 0xff
447
#define USER_DATA_2_DP_ENCODER0_P0_FLDMASK_POS 0
448
#define USER_DATA_2_DP_ENCODER0_P0_FLDMASK_LEN 8
449
450
#define VSC_EXT_VESA_CFG_DP_ENCODER0_P0_FLDMASK 0xf00
451
#define VSC_EXT_VESA_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
452
#define VSC_EXT_VESA_CFG_DP_ENCODER0_P0_FLDMASK_LEN 4
453
454
#define VSC_EXT_CEA_CFG_DP_ENCODER0_P0_FLDMASK 0xf000
455
#define VSC_EXT_CEA_CFG_DP_ENCODER0_P0_FLDMASK_POS 12
456
#define VSC_EXT_CEA_CFG_DP_ENCODER0_P0_FLDMASK_LEN 4
457
458
#define REG_30A4_DP_ENCODER0_P0 0x30A4
459
#define AU_TS_CFG_DP_ENCODER0_P0_FLDMASK 0xff
460
#define AU_TS_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
461
#define AU_TS_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
462
463
#define AVI_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
464
#define AVI_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
465
#define AVI_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
466
467
#define REG_30A8_DP_ENCODER0_P0 0x30A8
468
#define AUI_CFG_DP_ENCODER0_P0_FLDMASK 0xff
469
#define AUI_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
470
#define AUI_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
471
472
#define SPD_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
473
#define SPD_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
474
#define SPD_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
475
476
#define REG_30AC_DP_ENCODER0_P0 0x30AC
477
#define MPEG_CFG_DP_ENCODER0_P0_FLDMASK 0xff
478
#define MPEG_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
479
#define MPEG_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
480
481
#define NTSC_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
482
#define NTSC_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
483
#define NTSC_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
484
485
#define REG_30B0_DP_ENCODER0_P0 0x30B0
486
#define VSP_CFG_DP_ENCODER0_P0_FLDMASK 0xff
487
#define VSP_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
488
#define VSP_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
489
490
#define EXT_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
491
#define EXT_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
492
#define EXT_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
493
494
#define REG_30B4_DP_ENCODER0_P0 0x30B4
495
#define ACM_CFG_DP_ENCODER0_P0_FLDMASK 0xff
496
#define ACM_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
497
#define ACM_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
498
499
#define ISRC_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
500
#define ISRC_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
501
#define ISRC_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
502
503
#define REG_30B8_DP_ENCODER0_P0 0x30B8
504
#define VSC_CFG_DP_ENCODER0_P0_FLDMASK 0xff
505
#define VSC_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
506
#define VSC_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
507
508
#define MSA_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
509
#define MSA_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
510
#define MSA_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
511
512
#define REG_30BC_DP_ENCODER0_P0 0x30BC
513
#define ISRC_CONT_DP_ENCODER0_P0_FLDMASK 0x1
514
#define ISRC_CONT_DP_ENCODER0_P0_FLDMASK_POS 0
515
#define ISRC_CONT_DP_ENCODER0_P0_FLDMASK_LEN 1
516
517
#define MSA_BY_SDP_DP_ENCODER0_P0_FLDMASK 0x2
518
#define MSA_BY_SDP_DP_ENCODER0_P0_FLDMASK_POS 1
519
#define MSA_BY_SDP_DP_ENCODER0_P0_FLDMASK_LEN 1
520
521
#define SDP_EN_DP_ENCODER0_P0_FLDMASK 0x4
522
#define SDP_EN_DP_ENCODER0_P0_FLDMASK_POS 2
523
#define SDP_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
524
525
#define NIBBLE_INTERLEAVER_EN_DP_ENCODER0_P0_FLDMASK 0x8
526
#define NIBBLE_INTERLEAVER_EN_DP_ENCODER0_P0_FLDMASK_POS 3
527
#define NIBBLE_INTERLEAVER_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
528
529
#define ECC_EN_DP_ENCODER0_P0_FLDMASK 0x10
530
#define ECC_EN_DP_ENCODER0_P0_FLDMASK_POS 4
531
#define ECC_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
532
533
#define ASP_MIN_PL_SIZE_DP_ENCODER0_P0_FLDMASK 0x60
534
#define ASP_MIN_PL_SIZE_DP_ENCODER0_P0_FLDMASK_POS 5
535
#define ASP_MIN_PL_SIZE_DP_ENCODER0_P0_FLDMASK_LEN 2
536
537
#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK 0x700
538
#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK_POS 8
539
#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK_LEN 3
540
541
#define AUDIO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK 0x4000
542
#define AUDIO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK_POS 14
543
#define AUDIO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
544
545
#define ASP_HB23_SEL_DP_ENCODER0_P0_FLDMASK 0x8000
546
#define ASP_HB23_SEL_DP_ENCODER0_P0_FLDMASK_POS 15
547
#define ASP_HB23_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
548
549
#define REG_30C0_DP_ENCODER0_P0 0x30C0
550
#define AU_TS_HB0_DP_ENCODER0_P0_FLDMASK 0xff
551
#define AU_TS_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
552
#define AU_TS_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
553
554
#define AU_TS_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
555
#define AU_TS_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
556
#define AU_TS_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
557
558
#define REG_30C4_DP_ENCODER0_P0 0x30C4
559
#define AU_TS_HB2_DP_ENCODER0_P0_FLDMASK 0xff
560
#define AU_TS_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
561
#define AU_TS_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
562
563
#define AU_TS_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
564
#define AU_TS_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
565
#define AU_TS_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
566
567
#define REG_30C8_DP_ENCODER0_P0 0x30C8
568
#define AUDIO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK 0xffff
569
#define AUDIO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK_POS 0
570
#define AUDIO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK_LEN 16
571
572
#define REG_30CC_DP_ENCODER0_P0 0x30CC
573
#define AUDIO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK 0xff
574
#define AUDIO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK_POS 0
575
#define AUDIO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK_LEN 8
576
577
#define REG_30D0_DP_ENCODER0_P0 0x30D0
578
#define AUDIO_N_CODE_0_DP_ENCODER0_P0_FLDMASK 0xffff
579
#define AUDIO_N_CODE_0_DP_ENCODER0_P0_FLDMASK_POS 0
580
#define AUDIO_N_CODE_0_DP_ENCODER0_P0_FLDMASK_LEN 16
581
582
#define REG_30D4_DP_ENCODER0_P0 0x30D4
583
#define AUDIO_N_CODE_1_DP_ENCODER0_P0_FLDMASK 0xff
584
#define AUDIO_N_CODE_1_DP_ENCODER0_P0_FLDMASK_POS 0
585
#define AUDIO_N_CODE_1_DP_ENCODER0_P0_FLDMASK_LEN 8
586
587
#define REG_30D8_DP_ENCODER0_P0 0x30D8
588
#define ACM_HB0_DP_ENCODER0_P0_FLDMASK 0xff
589
#define ACM_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
590
#define ACM_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
591
592
#define ACM_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
593
#define ACM_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
594
#define ACM_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
595
596
#define REG_30DC_DP_ENCODER0_P0 0x30DC
597
#define ACM_HB2_DP_ENCODER0_P0_FLDMASK 0xff
598
#define ACM_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
599
#define ACM_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
600
601
#define ACM_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
602
#define ACM_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
603
#define ACM_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
604
605
#define REG_30E0_DP_ENCODER0_P0 0x30E0
606
#define ISRC_HB0_DP_ENCODER0_P0_FLDMASK 0xff
607
#define ISRC_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
608
#define ISRC_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
609
610
#define ISRC_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
611
#define ISRC_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
612
#define ISRC_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
613
614
#define REG_30E4_DP_ENCODER0_P0 0x30E4
615
#define ISRC_HB2_DP_ENCODER0_P0_FLDMASK 0xff
616
#define ISRC_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
617
#define ISRC_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
618
619
#define ISRC0_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
620
#define ISRC0_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
621
#define ISRC0_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
622
623
#define REG_30E8_DP_ENCODER0_P0 0x30E8
624
#define AVI_HB0_DP_ENCODER0_P0_FLDMASK 0xff
625
#define AVI_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
626
#define AVI_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
627
628
#define AVI_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
629
#define AVI_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
630
#define AVI_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
631
632
#define REG_30EC_DP_ENCODER0_P0 0x30EC
633
#define AVI_HB2_DP_ENCODER0_P0_FLDMASK 0xff
634
#define AVI_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
635
#define AVI_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
636
637
#define AVI_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
638
#define AVI_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
639
#define AVI_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
640
641
#define REG_30F0_DP_ENCODER0_P0 0x30F0
642
#define AUI_HB0_DP_ENCODER0_P0_FLDMASK 0xff
643
#define AUI_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
644
#define AUI_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
645
646
#define AUI_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
647
#define AUI_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
648
#define AUI_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
649
650
#define REG_30F4_DP_ENCODER0_P0 0x30F4
651
#define AUI_HB2_DP_ENCODER0_P0_FLDMASK 0xff
652
#define AUI_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
653
#define AUI_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
654
655
#define AUI_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
656
#define AUI_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
657
#define AUI_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
658
659
#define REG_30F8_DP_ENCODER0_P0 0x30F8
660
#define SPD_HB0_DP_ENCODER0_P0_FLDMASK 0xff
661
#define SPD_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
662
#define SPD_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
663
664
#define SPD_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
665
#define SPD_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
666
#define SPD_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
667
668
#define REG_30FC_DP_ENCODER0_P0 0x30FC
669
#define SPD_HB2_DP_ENCODER0_P0_FLDMASK 0xff
670
#define SPD_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
671
#define SPD_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
672
673
#define SPD_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
674
#define SPD_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
675
#define SPD_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
676
677
#define REG_3100_DP_ENCODER0_P0 0x3100
678
#define MPEG_HB0_DP_ENCODER0_P0_FLDMASK 0xff
679
#define MPEG_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
680
#define MPEG_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
681
682
#define MPEG_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
683
#define MPEG_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
684
#define MPEG_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
685
686
#define REG_3104_DP_ENCODER0_P0 0x3104
687
#define MPEG_HB2_DP_ENCODER0_P0_FLDMASK 0xff
688
#define MPEG_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
689
#define MPEG_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
690
691
#define MPEG_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
692
#define MPEG_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
693
#define MPEG_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
694
695
#define REG_3108_DP_ENCODER0_P0 0x3108
696
#define NTSC_HB0_DP_ENCODER0_P0_FLDMASK 0xff
697
#define NTSC_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
698
#define NTSC_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
699
700
#define NTSC_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
701
#define NTSC_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
702
#define NTSC_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
703
704
#define REG_310C_DP_ENCODER0_P0 0x310C
705
#define NTSC_HB2_DP_ENCODER0_P0_FLDMASK 0xff
706
#define NTSC_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
707
#define NTSC_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
708
709
#define NTSC_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
710
#define NTSC_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
711
#define NTSC_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
712
713
#define REG_3110_DP_ENCODER0_P0 0x3110
714
#define VSP_HB0_DP_ENCODER0_P0_FLDMASK 0xff
715
#define VSP_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
716
#define VSP_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
717
718
#define VSP_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
719
#define VSP_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
720
#define VSP_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
721
722
#define REG_3114_DP_ENCODER0_P0 0x3114
723
#define VSP_HB2_DP_ENCODER0_P0_FLDMASK 0xff
724
#define VSP_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
725
#define VSP_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
726
727
#define VSP_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
728
#define VSP_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
729
#define VSP_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
730
731
#define REG_3118_DP_ENCODER0_P0 0x3118
732
#define VSC_HB0_DP_ENCODER0_P0_FLDMASK 0xff
733
#define VSC_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
734
#define VSC_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
735
736
#define VSC_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
737
#define VSC_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
738
#define VSC_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
739
740
#define REG_311C_DP_ENCODER0_P0 0x311C
741
#define VSC_HB2_DP_ENCODER0_P0_FLDMASK 0xff
742
#define VSC_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
743
#define VSC_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
744
745
#define VSC_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
746
#define VSC_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
747
#define VSC_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
748
749
#define REG_3120_DP_ENCODER0_P0 0x3120
750
#define EXT_HB0_DP_ENCODER0_P0_FLDMASK 0xff
751
#define EXT_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
752
#define EXT_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
753
754
#define EXT_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
755
#define EXT_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
756
#define EXT_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
757
758
#define REG_3124_DP_ENCODER0_P0 0x3124
759
#define EXT_HB2_DP_ENCODER0_P0_FLDMASK 0xff
760
#define EXT_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
761
#define EXT_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
762
763
#define EXT_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
764
#define EXT_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
765
#define EXT_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
766
767
#define REG_3128_DP_ENCODER0_P0 0x3128
768
#define ASP_HB0_DP_ENCODER0_P0_FLDMASK 0xff
769
#define ASP_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
770
#define ASP_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
771
772
#define ASP_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
773
#define ASP_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
774
#define ASP_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
775
776
#define REG_312C_DP_ENCODER0_P0 0x312C
777
#define ASP_HB2_DP_ENCODER0_P0_FLDMASK 0xff
778
#define ASP_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
779
#define ASP_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
780
781
#define ASP_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
782
#define ASP_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
783
#define ASP_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
784
785
#define REG_3130_DP_ENCODER0_P0 0x3130
786
#define PPS_HB0_DP_ENCODER0_P0_FLDMASK 0xff
787
#define PPS_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
788
#define PPS_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
789
790
#define PPS_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
791
#define PPS_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
792
#define PPS_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
793
794
#define REG_3134_DP_ENCODER0_P0 0x3134
795
#define PPS_HB2_DP_ENCODER0_P0_FLDMASK 0xff
796
#define PPS_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
797
#define PPS_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
798
799
#define PPS_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
800
#define PPS_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
801
#define PPS_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
802
803
#define REG_3138_DP_ENCODER0_P0 0x3138
804
#define HDR0_HB0_DP_ENCODER0_P0_FLDMASK 0xff
805
#define HDR0_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
806
#define HDR0_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
807
808
#define HDR0_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
809
#define HDR0_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
810
#define HDR0_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
811
812
#define REG_313C_DP_ENCODER0_P0 0x313C
813
#define HDR0_HB2_DP_ENCODER0_P0_FLDMASK 0xff
814
#define HDR0_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
815
#define HDR0_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
816
817
#define HDR0_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
818
#define HDR0_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
819
#define HDR0_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
820
821
#define REG_3140_DP_ENCODER0_P0 0x3140
822
#define PGEN_CURSOR_V_DP_ENCODER0_P0_FLDMASK 0x1fff
823
#define PGEN_CURSOR_V_DP_ENCODER0_P0_FLDMASK_POS 0
824
#define PGEN_CURSOR_V_DP_ENCODER0_P0_FLDMASK_LEN 13
825
826
#define PGEN_TG_SEL_DP_ENCODER0_P0_FLDMASK 0x2000
827
#define PGEN_TG_SEL_DP_ENCODER0_P0_FLDMASK_POS 13
828
#define PGEN_TG_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
829
830
#define PGEN_PG_SEL_DP_ENCODER0_P0_FLDMASK 0x4000
831
#define PGEN_PG_SEL_DP_ENCODER0_P0_FLDMASK_POS 14
832
#define PGEN_PG_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
833
834
#define PGEN_CURSOR_EN_DP_ENCODER0_P0_FLDMASK 0x8000
835
#define PGEN_CURSOR_EN_DP_ENCODER0_P0_FLDMASK_POS 15
836
#define PGEN_CURSOR_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
837
838
#define REG_3144_DP_ENCODER0_P0 0x3144
839
#define PGEN_CURSOR_H_DP_ENCODER0_P0_FLDMASK 0x3fff
840
#define PGEN_CURSOR_H_DP_ENCODER0_P0_FLDMASK_POS 0
841
#define PGEN_CURSOR_H_DP_ENCODER0_P0_FLDMASK_LEN 14
842
843
#define REG_3148_DP_ENCODER0_P0 0x3148
844
#define PGEN_CURSOR_RGB_COLOR_CODE_0_DP_ENCODER0_P0_FLDMASK 0xffff
845
#define PGEN_CURSOR_RGB_COLOR_CODE_0_DP_ENCODER0_P0_FLDMASK_POS 0
846
#define PGEN_CURSOR_RGB_COLOR_CODE_0_DP_ENCODER0_P0_FLDMASK_LEN 16
847
848
#define REG_314C_DP_ENCODER0_P0 0x314C
849
#define PGEN_CURSOR_RGB_COLOR_CODE_1_DP_ENCODER0_P0_FLDMASK 0xffff
850
#define PGEN_CURSOR_RGB_COLOR_CODE_1_DP_ENCODER0_P0_FLDMASK_POS 0
851
#define PGEN_CURSOR_RGB_COLOR_CODE_1_DP_ENCODER0_P0_FLDMASK_LEN 16
852
853
#define REG_3150_DP_ENCODER0_P0 0x3150
854
#define PGEN_CURSOR_RGB_COLOR_CODE_2_DP_ENCODER0_P0_FLDMASK 0xf
855
#define PGEN_CURSOR_RGB_COLOR_CODE_2_DP_ENCODER0_P0_FLDMASK_POS 0
856
#define PGEN_CURSOR_RGB_COLOR_CODE_2_DP_ENCODER0_P0_FLDMASK_LEN 4
857
858
#define REG_3154_DP_ENCODER0_P0 0x3154
859
#define PGEN_HTOTAL_DP_ENCODER0_P0_FLDMASK 0x3fff
860
#define PGEN_HTOTAL_DP_ENCODER0_P0_FLDMASK_POS 0
861
#define PGEN_HTOTAL_DP_ENCODER0_P0_FLDMASK_LEN 14
862
863
#define REG_3158_DP_ENCODER0_P0 0x3158
864
#define PGEN_HSYNC_RISING_DP_ENCODER0_P0_FLDMASK 0x3fff
865
#define PGEN_HSYNC_RISING_DP_ENCODER0_P0_FLDMASK_POS 0
866
#define PGEN_HSYNC_RISING_DP_ENCODER0_P0_FLDMASK_LEN 14
867
868
#define REG_315C_DP_ENCODER0_P0 0x315C
869
#define PGEN_HSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK 0x3fff
870
#define PGEN_HSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
871
#define PGEN_HSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK_LEN 14
872
873
#define REG_3160_DP_ENCODER0_P0 0x3160
874
#define PGEN_HFDE_START_DP_ENCODER0_P0_FLDMASK 0x3fff
875
#define PGEN_HFDE_START_DP_ENCODER0_P0_FLDMASK_POS 0
876
#define PGEN_HFDE_START_DP_ENCODER0_P0_FLDMASK_LEN 14
877
878
#define REG_3164_DP_ENCODER0_P0 0x3164
879
#define PGEN_HFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK 0x3fff
880
#define PGEN_HFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
881
#define PGEN_HFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK_LEN 14
882
883
#define REG_3168_DP_ENCODER0_P0 0x3168
884
#define PGEN_VTOTAL_DP_ENCODER0_P0_FLDMASK 0x1fff
885
#define PGEN_VTOTAL_DP_ENCODER0_P0_FLDMASK_POS 0
886
#define PGEN_VTOTAL_DP_ENCODER0_P0_FLDMASK_LEN 13
887
888
#define REG_316C_DP_ENCODER0_P0 0x316C
889
#define PGEN_VSYNC_RISING_DP_ENCODER0_P0_FLDMASK 0x1fff
890
#define PGEN_VSYNC_RISING_DP_ENCODER0_P0_FLDMASK_POS 0
891
#define PGEN_VSYNC_RISING_DP_ENCODER0_P0_FLDMASK_LEN 13
892
893
#define REG_3170_DP_ENCODER0_P0 0x3170
894
#define PGEN_VSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK 0x1fff
895
#define PGEN_VSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
896
#define PGEN_VSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK_LEN 13
897
898
#define REG_3174_DP_ENCODER0_P0 0x3174
899
#define PGEN_VFDE_START_DP_ENCODER0_P0_FLDMASK 0x1fff
900
#define PGEN_VFDE_START_DP_ENCODER0_P0_FLDMASK_POS 0
901
#define PGEN_VFDE_START_DP_ENCODER0_P0_FLDMASK_LEN 13
902
903
#define REG_3178_DP_ENCODER0_P0 0x3178
904
#define PGEN_VFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK 0x1fff
905
#define PGEN_VFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
906
#define PGEN_VFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK_LEN 13
907
908
#define REG_317C_DP_ENCODER0_P0 0x317C
909
#define PGEN_PAT_BASE_PIXEL_0_DP_ENCODER0_P0_FLDMASK 0xfff
910
#define PGEN_PAT_BASE_PIXEL_0_DP_ENCODER0_P0_FLDMASK_POS 0
911
#define PGEN_PAT_BASE_PIXEL_0_DP_ENCODER0_P0_FLDMASK_LEN 12
912
913
#define REG_3180_DP_ENCODER0_P0 0x3180
914
#define PGEN_PAT_BASE_PIXEL_1_DP_ENCODER0_P0_FLDMASK 0xfff
915
#define PGEN_PAT_BASE_PIXEL_1_DP_ENCODER0_P0_FLDMASK_POS 0
916
#define PGEN_PAT_BASE_PIXEL_1_DP_ENCODER0_P0_FLDMASK_LEN 12
917
918
#define REG_3184_DP_ENCODER0_P0 0x3184
919
#define PGEN_PAT_BASE_PIXEL_2_DP_ENCODER0_P0_FLDMASK 0xfff
920
#define PGEN_PAT_BASE_PIXEL_2_DP_ENCODER0_P0_FLDMASK_POS 0
921
#define PGEN_PAT_BASE_PIXEL_2_DP_ENCODER0_P0_FLDMASK_LEN 12
922
923
#define REG_3188_DP_ENCODER0_P0 0x3188
924
#define PGEN_INITIAL_H_CNT_DP_ENCODER0_P0_FLDMASK 0x3fff
925
#define PGEN_INITIAL_H_CNT_DP_ENCODER0_P0_FLDMASK_POS 0
926
#define PGEN_INITIAL_H_CNT_DP_ENCODER0_P0_FLDMASK_LEN 14
927
928
#define REG_318C_DP_ENCODER0_P0 0x318C
929
#define PGEN_INITIAL_V_CNT_DP_ENCODER0_P0_FLDMASK 0x1fff
930
#define PGEN_INITIAL_V_CNT_DP_ENCODER0_P0_FLDMASK_POS 0
931
#define PGEN_INITIAL_V_CNT_DP_ENCODER0_P0_FLDMASK_LEN 13
932
933
#define REG_3190_DP_ENCODER0_P0 0x3190
934
#define PGEN_INITIAL_CB_SEL_DP_ENCODER0_P0_FLDMASK 0x7
935
#define PGEN_INITIAL_CB_SEL_DP_ENCODER0_P0_FLDMASK_POS 0
936
#define PGEN_INITIAL_CB_SEL_DP_ENCODER0_P0_FLDMASK_LEN 3
937
938
#define PGEN_FRAME_8K4K_MODE_EN_DP_ENCODER0_P0_FLDMASK 0x10
939
#define PGEN_FRAME_8K4K_MODE_EN_DP_ENCODER0_P0_FLDMASK_POS 4
940
#define PGEN_FRAME_8K4K_MODE_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
941
942
#define PGEN_FRAME_8K4K_MODE_SET_DP_ENCODER0_P0_FLDMASK 0x20
943
#define PGEN_FRAME_8K4K_MODE_SET_DP_ENCODER0_P0_FLDMASK_POS 5
944
#define PGEN_FRAME_8K4K_MODE_SET_DP_ENCODER0_P0_FLDMASK_LEN 1
945
946
#define PGEN_INITIAL_H_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK 0x40
947
#define PGEN_INITIAL_H_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK_POS 6
948
#define PGEN_INITIAL_H_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK_LEN 1
949
950
#define PGEN_INITIAL_V_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK 0x80
951
#define PGEN_INITIAL_V_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK_POS 7
952
#define PGEN_INITIAL_V_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK_LEN 1
953
954
#define PGEN_FRAME_END_H_EN_DP_ENCODER0_P0_FLDMASK 0x100
955
#define PGEN_FRAME_END_H_EN_DP_ENCODER0_P0_FLDMASK_POS 8
956
#define PGEN_FRAME_END_H_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
957
958
#define PGEN_FRAME_END_V_EN_DP_ENCODER0_P0_FLDMASK 0x200
959
#define PGEN_FRAME_END_V_EN_DP_ENCODER0_P0_FLDMASK_POS 9
960
#define PGEN_FRAME_END_V_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
961
962
#define REG_3194_DP_ENCODER0_P0 0x3194
963
#define PGEN_PAT_EXTRA_PIXEL_0_DP_ENCODER0_P0_FLDMASK 0xfff
964
#define PGEN_PAT_EXTRA_PIXEL_0_DP_ENCODER0_P0_FLDMASK_POS 0
965
#define PGEN_PAT_EXTRA_PIXEL_0_DP_ENCODER0_P0_FLDMASK_LEN 12
966
967
#define REG_3198_DP_ENCODER0_P0 0x3198
968
#define PGEN_PAT_EXTRA_PIXEL_1_DP_ENCODER0_P0_FLDMASK 0xfff
969
#define PGEN_PAT_EXTRA_PIXEL_1_DP_ENCODER0_P0_FLDMASK_POS 0
970
#define PGEN_PAT_EXTRA_PIXEL_1_DP_ENCODER0_P0_FLDMASK_LEN 12
971
972
#define REG_319C_DP_ENCODER0_P0 0x319C
973
#define PGEN_PAT_EXTRA_PIXEL_2_DP_ENCODER0_P0_FLDMASK 0xfff
974
#define PGEN_PAT_EXTRA_PIXEL_2_DP_ENCODER0_P0_FLDMASK_POS 0
975
#define PGEN_PAT_EXTRA_PIXEL_2_DP_ENCODER0_P0_FLDMASK_LEN 12
976
977
#define REG_31A0_DP_ENCODER0_P0 0x31A0
978
#define PGEN_PAT_INCREMENT_0_DP_ENCODER0_P0_FLDMASK 0xffff
979
#define PGEN_PAT_INCREMENT_0_DP_ENCODER0_P0_FLDMASK_POS 0
980
#define PGEN_PAT_INCREMENT_0_DP_ENCODER0_P0_FLDMASK_LEN 16
981
982
#define REG_31A4_DP_ENCODER0_P0 0x31A4
983
#define PGEN_PAT_INCREMENT_1_DP_ENCODER0_P0_FLDMASK 0x1
984
#define PGEN_PAT_INCREMENT_1_DP_ENCODER0_P0_FLDMASK_POS 0
985
#define PGEN_PAT_INCREMENT_1_DP_ENCODER0_P0_FLDMASK_LEN 1
986
987
#define REG_31A8_DP_ENCODER0_P0 0x31A8
988
#define PGEN_PAT_HWIDTH_DP_ENCODER0_P0_FLDMASK 0x3fff
989
#define PGEN_PAT_HWIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
990
#define PGEN_PAT_HWIDTH_DP_ENCODER0_P0_FLDMASK_LEN 14
991
992
#define REG_31AC_DP_ENCODER0_P0 0x31AC
993
#define PGEN_PAT_VWIDTH_DP_ENCODER0_P0_FLDMASK 0x1fff
994
#define PGEN_PAT_VWIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
995
#define PGEN_PAT_VWIDTH_DP_ENCODER0_P0_FLDMASK_LEN 13
996
997
#define REG_31B0_DP_ENCODER0_P0 0x31B0
998
#define PGEN_PAT_RGB_ENABLE_DP_ENCODER0_P0_FLDMASK 0x7
999
#define PGEN_PAT_RGB_ENABLE_DP_ENCODER0_P0_FLDMASK_POS 0
1000
#define PGEN_PAT_RGB_ENABLE_DP_ENCODER0_P0_FLDMASK_LEN 3
1001
1002
#define PGEN_PATTERN_SEL_DP_ENCODER0_P0_FLDMASK 0x70
1003
#define PGEN_PATTERN_SEL_DP_ENCODER0_P0_FLDMASK_POS 4
1004
#define PGEN_PATTERN_SEL_DP_ENCODER0_P0_FLDMASK_LEN 3
1005
1006
#define PGEN_PAT_DIRECTION_DP_ENCODER0_P0_FLDMASK 0x80
1007
#define PGEN_PAT_DIRECTION_DP_ENCODER0_P0_FLDMASK_POS 7
1008
#define PGEN_PAT_DIRECTION_DP_ENCODER0_P0_FLDMASK_LEN 1
1009
1010
#define PGEN_PAT_GRADIENT_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK 0x100
1011
#define PGEN_PAT_GRADIENT_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK_POS 8
1012
#define PGEN_PAT_GRADIENT_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK_LEN 1
1013
1014
#define PGEN_PAT_COLOR_BAR_GRADIENT_EN_DP_ENCODER0_P0_FLDMASK 0x200
1015
#define PGEN_PAT_COLOR_BAR_GRADIENT_EN_DP_ENCODER0_P0_FLDMASK_POS 9
1016
#define PGEN_PAT_COLOR_BAR_GRADIENT_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
1017
1018
#define PGEN_PAT_CHESSBOARD_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK 0x400
1019
#define PGEN_PAT_CHESSBOARD_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK_POS 10
1020
#define PGEN_PAT_CHESSBOARD_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK_LEN 1
1021
1022
#define PGEN_PAT_EXCHANGE_DP_ENCODER0_P0_FLDMASK 0x800
1023
#define PGEN_PAT_EXCHANGE_DP_ENCODER0_P0_FLDMASK_POS 11
1024
#define PGEN_PAT_EXCHANGE_DP_ENCODER0_P0_FLDMASK_LEN 1
1025
1026
#define PGEN_PAT_RGB_SUB_PIXEL_MASK_DP_ENCODER0_P0_FLDMASK 0x1000
1027
#define PGEN_PAT_RGB_SUB_PIXEL_MASK_DP_ENCODER0_P0_FLDMASK_POS 12
1028
#define PGEN_PAT_RGB_SUB_PIXEL_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
1029
1030
#define REG_31B4_DP_ENCODER0_P0 0x31B4
1031
#define PGEN_PAT_THICKNESS_DP_ENCODER0_P0_FLDMASK 0xf
1032
#define PGEN_PAT_THICKNESS_DP_ENCODER0_P0_FLDMASK_POS 0
1033
#define PGEN_PAT_THICKNESS_DP_ENCODER0_P0_FLDMASK_LEN 4
1034
1035
#define REG_31C0_DP_ENCODER0_P0 0x31C0
1036
#define VIDEO_MUTE_CNT_THRD_DP_ENCODER0_P0_FLDMASK 0xfff
1037
#define VIDEO_MUTE_CNT_THRD_DP_ENCODER0_P0_FLDMASK_POS 0
1038
#define VIDEO_MUTE_CNT_THRD_DP_ENCODER0_P0_FLDMASK_LEN 12
1039
1040
#define REG_31C4_DP_ENCODER0_P0 0x31C4
1041
#define PPS_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK 0x800
1042
#define PPS_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_POS 11
1043
#define PPS_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
1044
1045
#define MST_EN_DP_ENCODER0_P0_FLDMASK 0x1000
1046
#define MST_EN_DP_ENCODER0_P0_FLDMASK_POS 12
1047
#define MST_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
1048
1049
#define DSC_BYPASS_EN_DP_ENCODER0_P0_FLDMASK 0x2000
1050
#define DSC_BYPASS_EN_DP_ENCODER0_P0_FLDMASK_POS 13
1051
#define DSC_BYPASS_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
1052
1053
#define VSC_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK 0x4000
1054
#define VSC_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_POS 14
1055
#define VSC_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
1056
1057
#define HDR0_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK 0x8000
1058
#define HDR0_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_POS 15
1059
#define HDR0_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
1060
1061
#define REG_31C8_DP_ENCODER0_P0 0x31C8
1062
#define VSC_EXT_VESA_HB0_DP_ENCODER0_P0_FLDMASK 0xff
1063
#define VSC_EXT_VESA_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
1064
#define VSC_EXT_VESA_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
1065
1066
#define VSC_EXT_VESA_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
1067
#define VSC_EXT_VESA_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
1068
#define VSC_EXT_VESA_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
1069
1070
#define REG_31CC_DP_ENCODER0_P0 0x31CC
1071
#define VSC_EXT_VESA_HB2_DP_ENCODER0_P0_FLDMASK 0xff
1072
#define VSC_EXT_VESA_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
1073
#define VSC_EXT_VESA_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
1074
1075
#define VSC_EXT_VESA_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
1076
#define VSC_EXT_VESA_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
1077
#define VSC_EXT_VESA_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
1078
1079
#define REG_31D0_DP_ENCODER0_P0 0x31D0
1080
#define VSC_EXT_CEA_HB0_DP_ENCODER0_P0_FLDMASK 0xff
1081
#define VSC_EXT_CEA_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
1082
#define VSC_EXT_CEA_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
1083
1084
#define VSC_EXT_CEA_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
1085
#define VSC_EXT_CEA_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
1086
#define VSC_EXT_CEA_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
1087
1088
#define REG_31D4_DP_ENCODER0_P0 0x31D4
1089
#define VSC_EXT_CEA_HB2_DP_ENCODER0_P0_FLDMASK 0xff
1090
#define VSC_EXT_CEA_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
1091
#define VSC_EXT_CEA_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
1092
1093
#define VSC_EXT_CEA_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
1094
#define VSC_EXT_CEA_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
1095
#define VSC_EXT_CEA_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
1096
1097
#define REG_31D8_DP_ENCODER0_P0 0x31D8
1098
#define VSC_EXT_VESA_NUM_DP_ENCODER0_P0_FLDMASK 0x3f
1099
#define VSC_EXT_VESA_NUM_DP_ENCODER0_P0_FLDMASK_POS 0
1100
#define VSC_EXT_VESA_NUM_DP_ENCODER0_P0_FLDMASK_LEN 6
1101
1102
#define VSC_EXT_CEA_NUM_DP_ENCODER0_P0_FLDMASK 0x3f00
1103
#define VSC_EXT_CEA_NUM_DP_ENCODER0_P0_FLDMASK_POS 8
1104
#define VSC_EXT_CEA_NUM_DP_ENCODER0_P0_FLDMASK_LEN 6
1105
1106
#define REG_31DC_DP_ENCODER0_P0 0x31DC
1107
#define HDR0_CFG_DP_ENCODER0_P0_FLDMASK 0xff
1108
#define HDR0_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
1109
#define HDR0_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
1110
1111
#define RESERVED_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
1112
#define RESERVED_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
1113
#define RESERVED_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
1114
1115
#define REG_31E0_DP_ENCODER0_P0 0x31E0
1116
#define RESERVED_HB0_DP_ENCODER0_P0_FLDMASK 0xff
1117
#define RESERVED_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
1118
#define RESERVED_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
1119
1120
#define RESERVED_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
1121
#define RESERVED_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
1122
#define RESERVED_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
1123
1124
#define REG_31E4_DP_ENCODER0_P0 0x31E4
1125
#define RESERVED_HB2_DP_ENCODER0_P0_FLDMASK 0xff
1126
#define RESERVED_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
1127
#define RESERVED_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
1128
1129
#define RESERVED_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
1130
#define RESERVED_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
1131
#define RESERVED_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
1132
1133
#define REG_31E8_DP_ENCODER0_P0 0x31E8
1134
#define PPS_CFG_DP_ENCODER0_P0_FLDMASK 0xff
1135
#define PPS_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
1136
#define PPS_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
1137
1138
#define PPS_CFG_ONE_TIME_DP_ENCODER0_P0_FLDMASK 0x100
1139
#define PPS_CFG_ONE_TIME_DP_ENCODER0_P0_FLDMASK_POS 8
1140
#define PPS_CFG_ONE_TIME_DP_ENCODER0_P0_FLDMASK_LEN 1
1141
1142
#define SDP_SPLIT_FIFO_READ_START_POINT_DP_ENCODER0_P0_FLDMASK 0xf000
1143
#define SDP_SPLIT_FIFO_READ_START_POINT_DP_ENCODER0_P0_FLDMASK_POS 12
1144
#define SDP_SPLIT_FIFO_READ_START_POINT_DP_ENCODER0_P0_FLDMASK_LEN 4
1145
1146
#define REG_31EC_DP_ENCODER0_P0 0x31EC
1147
#define VIDEO_M_CODE_FROM_DPRX_DP_ENCODER0_P0_FLDMASK 0x1
1148
#define VIDEO_M_CODE_FROM_DPRX_DP_ENCODER0_P0_FLDMASK_POS 0
1149
#define VIDEO_M_CODE_FROM_DPRX_DP_ENCODER0_P0_FLDMASK_LEN 1
1150
1151
#define MSA_MISC_FROM_DPRX_DP_ENCODER0_P0_FLDMASK 0x2
1152
#define MSA_MISC_FROM_DPRX_DP_ENCODER0_P0_FLDMASK_POS 1
1153
#define MSA_MISC_FROM_DPRX_DP_ENCODER0_P0_FLDMASK_LEN 1
1154
1155
#define ADS_CFG_DP_ENCODER0_P0_FLDMASK 0x4
1156
#define ADS_CFG_DP_ENCODER0_P0_FLDMASK_POS 2
1157
#define ADS_CFG_DP_ENCODER0_P0_FLDMASK_LEN 1
1158
1159
#define ADS_MODE_DP_ENCODER0_P0_FLDMASK 0x8
1160
#define ADS_MODE_DP_ENCODER0_P0_FLDMASK_POS 3
1161
#define ADS_MODE_DP_ENCODER0_P0_FLDMASK_LEN 1
1162
1163
#define AUDIO_CH_SRC_SEL_DP_ENCODER0_P0_FLDMASK 0x10
1164
#define AUDIO_CH_SRC_SEL_DP_ENCODER0_P0_FLDMASK_POS 4
1165
#define AUDIO_CH_SRC_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
1166
1167
#define ISRC1_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
1168
#define ISRC1_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
1169
#define ISRC1_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
1170
1171
#define REG_31F0_DP_ENCODER0_P0 0x31F0
1172
#define ADS_HB0_DP_ENCODER0_P0_FLDMASK 0xff
1173
#define ADS_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
1174
#define ADS_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
1175
1176
#define ADS_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
1177
#define ADS_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
1178
#define ADS_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
1179
1180
#define REG_31F8_DP_ENCODER0_P0 0x31F8
1181
#define ADS_HB2_DP_ENCODER0_P0_FLDMASK 0xff
1182
#define ADS_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
1183
#define ADS_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
1184
1185
#define ADS_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
1186
#define ADS_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
1187
#define ADS_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
1188
1189
#define REG_31FC_DP_ENCODER0_P0 0x31FC
1190
#define VIDEO_ARBITER_DE_LAST_NUM0_SW_DP_ENCODER0_P0_FLDMASK 0x3
1191
#define VIDEO_ARBITER_DE_LAST_NUM0_SW_DP_ENCODER0_P0_FLDMASK_POS 0
1192
#define VIDEO_ARBITER_DE_LAST_NUM0_SW_DP_ENCODER0_P0_FLDMASK_LEN 2
1193
1194
#define VIDEO_ARBITER_DE_LAST_NUM1_SW_DP_ENCODER0_P0_FLDMASK 0xc
1195
#define VIDEO_ARBITER_DE_LAST_NUM1_SW_DP_ENCODER0_P0_FLDMASK_POS 2
1196
#define VIDEO_ARBITER_DE_LAST_NUM1_SW_DP_ENCODER0_P0_FLDMASK_LEN 2
1197
1198
#define VIDEO_ARBITER_DE_LAST_NUM2_SW_DP_ENCODER0_P0_FLDMASK 0x30
1199
#define VIDEO_ARBITER_DE_LAST_NUM2_SW_DP_ENCODER0_P0_FLDMASK_POS 4
1200
#define VIDEO_ARBITER_DE_LAST_NUM2_SW_DP_ENCODER0_P0_FLDMASK_LEN 2
1201
1202
#define VIDEO_ARBITER_DE_LAST_NUM3_SW_DP_ENCODER0_P0_FLDMASK 0xc0
1203
#define VIDEO_ARBITER_DE_LAST_NUM3_SW_DP_ENCODER0_P0_FLDMASK_POS 6
1204
#define VIDEO_ARBITER_DE_LAST_NUM3_SW_DP_ENCODER0_P0_FLDMASK_LEN 2
1205
1206
#define HDE_NUM_EVEN_EN_SW_LANE0_DP_ENCODER0_P0_FLDMASK 0x100
1207
#define HDE_NUM_EVEN_EN_SW_LANE0_DP_ENCODER0_P0_FLDMASK_POS 8
1208
#define HDE_NUM_EVEN_EN_SW_LANE0_DP_ENCODER0_P0_FLDMASK_LEN 1
1209
1210
#define HDE_NUM_EVEN_EN_SW_LANE1_DP_ENCODER0_P0_FLDMASK 0x200
1211
#define HDE_NUM_EVEN_EN_SW_LANE1_DP_ENCODER0_P0_FLDMASK_POS 9
1212
#define HDE_NUM_EVEN_EN_SW_LANE1_DP_ENCODER0_P0_FLDMASK_LEN 1
1213
1214
#define HDE_NUM_EVEN_EN_SW_LANE2_DP_ENCODER0_P0_FLDMASK 0x400
1215
#define HDE_NUM_EVEN_EN_SW_LANE2_DP_ENCODER0_P0_FLDMASK_POS 10
1216
#define HDE_NUM_EVEN_EN_SW_LANE2_DP_ENCODER0_P0_FLDMASK_LEN 1
1217
1218
#define HDE_NUM_EVEN_EN_SW_LANE3_DP_ENCODER0_P0_FLDMASK 0x800
1219
#define HDE_NUM_EVEN_EN_SW_LANE3_DP_ENCODER0_P0_FLDMASK_POS 11
1220
#define HDE_NUM_EVEN_EN_SW_LANE3_DP_ENCODER0_P0_FLDMASK_LEN 1
1221
1222
#define DE_LAST_NUM_SW_DP_ENCODER0_P0_FLDMASK 0x1000
1223
#define DE_LAST_NUM_SW_DP_ENCODER0_P0_FLDMASK_POS 12
1224
#define DE_LAST_NUM_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
1225
1226
#define REG_3200_DP_ENCODER1_P0 0x3200
1227
#define SDP_DB0_DP_ENCODER1_P0_FLDMASK 0xff
1228
#define SDP_DB0_DP_ENCODER1_P0_FLDMASK_POS 0
1229
#define SDP_DB0_DP_ENCODER1_P0_FLDMASK_LEN 8
1230
1231
#define SDP_DB1_DP_ENCODER1_P0_FLDMASK 0xff00
1232
#define SDP_DB1_DP_ENCODER1_P0_FLDMASK_POS 8
1233
#define SDP_DB1_DP_ENCODER1_P0_FLDMASK_LEN 8
1234
1235
#define REG_3204_DP_ENCODER1_P0 0x3204
1236
#define SDP_DB2_DP_ENCODER1_P0_FLDMASK 0xff
1237
#define SDP_DB2_DP_ENCODER1_P0_FLDMASK_POS 0
1238
#define SDP_DB2_DP_ENCODER1_P0_FLDMASK_LEN 8
1239
1240
#define SDP_DB3_DP_ENCODER1_P0_FLDMASK 0xff00
1241
#define SDP_DB3_DP_ENCODER1_P0_FLDMASK_POS 8
1242
#define SDP_DB3_DP_ENCODER1_P0_FLDMASK_LEN 8
1243
1244
#define REG_3208_DP_ENCODER1_P0 0x3208
1245
#define SDP_DB4_DP_ENCODER1_P0_FLDMASK 0xff
1246
#define SDP_DB4_DP_ENCODER1_P0_FLDMASK_POS 0
1247
#define SDP_DB4_DP_ENCODER1_P0_FLDMASK_LEN 8
1248
1249
#define SDP_DB5_DP_ENCODER1_P0_FLDMASK 0xff00
1250
#define SDP_DB5_DP_ENCODER1_P0_FLDMASK_POS 8
1251
#define SDP_DB5_DP_ENCODER1_P0_FLDMASK_LEN 8
1252
1253
#define REG_320C_DP_ENCODER1_P0 0x320C
1254
#define SDP_DB6_DP_ENCODER1_P0_FLDMASK 0xff
1255
#define SDP_DB6_DP_ENCODER1_P0_FLDMASK_POS 0
1256
#define SDP_DB6_DP_ENCODER1_P0_FLDMASK_LEN 8
1257
1258
#define SDP_DB7_DP_ENCODER1_P0_FLDMASK 0xff00
1259
#define SDP_DB7_DP_ENCODER1_P0_FLDMASK_POS 8
1260
#define SDP_DB7_DP_ENCODER1_P0_FLDMASK_LEN 8
1261
1262
#define REG_3210_DP_ENCODER1_P0 0x3210
1263
#define SDP_DB8_DP_ENCODER1_P0_FLDMASK 0xff
1264
#define SDP_DB8_DP_ENCODER1_P0_FLDMASK_POS 0
1265
#define SDP_DB8_DP_ENCODER1_P0_FLDMASK_LEN 8
1266
1267
#define SDP_DB9_DP_ENCODER1_P0_FLDMASK 0xff00
1268
#define SDP_DB9_DP_ENCODER1_P0_FLDMASK_POS 8
1269
#define SDP_DB9_DP_ENCODER1_P0_FLDMASK_LEN 8
1270
1271
#define REG_3214_DP_ENCODER1_P0 0x3214
1272
#define SDP_DB10_DP_ENCODER1_P0_FLDMASK 0xff
1273
#define SDP_DB10_DP_ENCODER1_P0_FLDMASK_POS 0
1274
#define SDP_DB10_DP_ENCODER1_P0_FLDMASK_LEN 8
1275
1276
#define SDP_DB11_DP_ENCODER1_P0_FLDMASK 0xff00
1277
#define SDP_DB11_DP_ENCODER1_P0_FLDMASK_POS 8
1278
#define SDP_DB11_DP_ENCODER1_P0_FLDMASK_LEN 8
1279
1280
#define REG_3218_DP_ENCODER1_P0 0x3218
1281
#define SDP_DB12_DP_ENCODER1_P0_FLDMASK 0xff
1282
#define SDP_DB12_DP_ENCODER1_P0_FLDMASK_POS 0
1283
#define SDP_DB12_DP_ENCODER1_P0_FLDMASK_LEN 8
1284
1285
#define SDP_DB13_DP_ENCODER1_P0_FLDMASK 0xff00
1286
#define SDP_DB13_DP_ENCODER1_P0_FLDMASK_POS 8
1287
#define SDP_DB13_DP_ENCODER1_P0_FLDMASK_LEN 8
1288
1289
#define REG_321C_DP_ENCODER1_P0 0x321C
1290
#define SDP_DB14_DP_ENCODER1_P0_FLDMASK 0xff
1291
#define SDP_DB14_DP_ENCODER1_P0_FLDMASK_POS 0
1292
#define SDP_DB14_DP_ENCODER1_P0_FLDMASK_LEN 8
1293
1294
#define SDP_DB15_DP_ENCODER1_P0_FLDMASK 0xff00
1295
#define SDP_DB15_DP_ENCODER1_P0_FLDMASK_POS 8
1296
#define SDP_DB15_DP_ENCODER1_P0_FLDMASK_LEN 8
1297
1298
#define REG_3220_DP_ENCODER1_P0 0x3220
1299
#define SDP_DB16_DP_ENCODER1_P0_FLDMASK 0xff
1300
#define SDP_DB16_DP_ENCODER1_P0_FLDMASK_POS 0
1301
#define SDP_DB16_DP_ENCODER1_P0_FLDMASK_LEN 8
1302
1303
#define SDP_DB17_DP_ENCODER1_P0_FLDMASK 0xff00
1304
#define SDP_DB17_DP_ENCODER1_P0_FLDMASK_POS 8
1305
#define SDP_DB17_DP_ENCODER1_P0_FLDMASK_LEN 8
1306
1307
#define REG_3224_DP_ENCODER1_P0 0x3224
1308
#define SDP_DB18_DP_ENCODER1_P0_FLDMASK 0xff
1309
#define SDP_DB18_DP_ENCODER1_P0_FLDMASK_POS 0
1310
#define SDP_DB18_DP_ENCODER1_P0_FLDMASK_LEN 8
1311
1312
#define SDP_DB19_DP_ENCODER1_P0_FLDMASK 0xff00
1313
#define SDP_DB19_DP_ENCODER1_P0_FLDMASK_POS 8
1314
#define SDP_DB19_DP_ENCODER1_P0_FLDMASK_LEN 8
1315
1316
#define REG_3228_DP_ENCODER1_P0 0x3228
1317
#define SDP_DB20_DP_ENCODER1_P0_FLDMASK 0xff
1318
#define SDP_DB20_DP_ENCODER1_P0_FLDMASK_POS 0
1319
#define SDP_DB20_DP_ENCODER1_P0_FLDMASK_LEN 8
1320
1321
#define SDP_DB21_DP_ENCODER1_P0_FLDMASK 0xff00
1322
#define SDP_DB21_DP_ENCODER1_P0_FLDMASK_POS 8
1323
#define SDP_DB21_DP_ENCODER1_P0_FLDMASK_LEN 8
1324
1325
#define REG_322C_DP_ENCODER1_P0 0x322C
1326
#define SDP_DB22_DP_ENCODER1_P0_FLDMASK 0xff
1327
#define SDP_DB22_DP_ENCODER1_P0_FLDMASK_POS 0
1328
#define SDP_DB22_DP_ENCODER1_P0_FLDMASK_LEN 8
1329
1330
#define SDP_DB23_DP_ENCODER1_P0_FLDMASK 0xff00
1331
#define SDP_DB23_DP_ENCODER1_P0_FLDMASK_POS 8
1332
#define SDP_DB23_DP_ENCODER1_P0_FLDMASK_LEN 8
1333
1334
#define REG_3230_DP_ENCODER1_P0 0x3230
1335
#define SDP_DB24_DP_ENCODER1_P0_FLDMASK 0xff
1336
#define SDP_DB24_DP_ENCODER1_P0_FLDMASK_POS 0
1337
#define SDP_DB24_DP_ENCODER1_P0_FLDMASK_LEN 8
1338
1339
#define SDP_DB25_DP_ENCODER1_P0_FLDMASK 0xff00
1340
#define SDP_DB25_DP_ENCODER1_P0_FLDMASK_POS 8
1341
#define SDP_DB25_DP_ENCODER1_P0_FLDMASK_LEN 8
1342
1343
#define REG_3234_DP_ENCODER1_P0 0x3234
1344
#define SDP_DB26_DP_ENCODER1_P0_FLDMASK 0xff
1345
#define SDP_DB26_DP_ENCODER1_P0_FLDMASK_POS 0
1346
#define SDP_DB26_DP_ENCODER1_P0_FLDMASK_LEN 8
1347
1348
#define SDP_DB27_DP_ENCODER1_P0_FLDMASK 0xff00
1349
#define SDP_DB27_DP_ENCODER1_P0_FLDMASK_POS 8
1350
#define SDP_DB27_DP_ENCODER1_P0_FLDMASK_LEN 8
1351
1352
#define REG_3238_DP_ENCODER1_P0 0x3238
1353
#define SDP_DB28_DP_ENCODER1_P0_FLDMASK 0xff
1354
#define SDP_DB28_DP_ENCODER1_P0_FLDMASK_POS 0
1355
#define SDP_DB28_DP_ENCODER1_P0_FLDMASK_LEN 8
1356
1357
#define SDP_DB29_DP_ENCODER1_P0_FLDMASK 0xff00
1358
#define SDP_DB29_DP_ENCODER1_P0_FLDMASK_POS 8
1359
#define SDP_DB29_DP_ENCODER1_P0_FLDMASK_LEN 8
1360
1361
#define REG_323C_DP_ENCODER1_P0 0x323C
1362
#define SDP_DB30_DP_ENCODER1_P0_FLDMASK 0xff
1363
#define SDP_DB30_DP_ENCODER1_P0_FLDMASK_POS 0
1364
#define SDP_DB30_DP_ENCODER1_P0_FLDMASK_LEN 8
1365
1366
#define SDP_DB31_DP_ENCODER1_P0_FLDMASK 0xff00
1367
#define SDP_DB31_DP_ENCODER1_P0_FLDMASK_POS 8
1368
#define SDP_DB31_DP_ENCODER1_P0_FLDMASK_LEN 8
1369
1370
#define REG_3240_DP_ENCODER1_P0 0x3240
1371
#define SDP_DB0_R_DP_ENCODER1_P0_FLDMASK 0xff
1372
#define SDP_DB0_R_DP_ENCODER1_P0_FLDMASK_POS 0
1373
#define SDP_DB0_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1374
1375
#define SDP_DB1_R_DP_ENCODER1_P0_FLDMASK 0xff00
1376
#define SDP_DB1_R_DP_ENCODER1_P0_FLDMASK_POS 8
1377
#define SDP_DB1_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1378
1379
#define REG_3244_DP_ENCODER1_P0 0x3244
1380
#define SDP_DB2_R_DP_ENCODER1_P0_FLDMASK 0xff
1381
#define SDP_DB2_R_DP_ENCODER1_P0_FLDMASK_POS 0
1382
#define SDP_DB2_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1383
1384
#define SDP_DB3_R_DP_ENCODER1_P0_FLDMASK 0xff00
1385
#define SDP_DB3_R_DP_ENCODER1_P0_FLDMASK_POS 8
1386
#define SDP_DB3_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1387
1388
#define REG_3248_DP_ENCODER1_P0 0x3248
1389
#define SDP_DB4_R_DP_ENCODER1_P0_FLDMASK 0xff
1390
#define SDP_DB4_R_DP_ENCODER1_P0_FLDMASK_POS 0
1391
#define SDP_DB4_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1392
1393
#define SDP_DB5_R_DP_ENCODER1_P0_FLDMASK 0xff00
1394
#define SDP_DB5_R_DP_ENCODER1_P0_FLDMASK_POS 8
1395
#define SDP_DB5_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1396
1397
#define REG_324C_DP_ENCODER1_P0 0x324C
1398
#define SDP_DB6_R_DP_ENCODER1_P0_FLDMASK 0xff
1399
#define SDP_DB6_R_DP_ENCODER1_P0_FLDMASK_POS 0
1400
#define SDP_DB6_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1401
1402
#define SDP_DB7_R_DP_ENCODER1_P0_FLDMASK 0xff00
1403
#define SDP_DB7_R_DP_ENCODER1_P0_FLDMASK_POS 8
1404
#define SDP_DB7_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1405
1406
#define REG_3250_DP_ENCODER1_P0 0x3250
1407
#define SDP_DB8_R_DP_ENCODER1_P0_FLDMASK 0xff
1408
#define SDP_DB8_R_DP_ENCODER1_P0_FLDMASK_POS 0
1409
#define SDP_DB8_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1410
1411
#define SDP_DB9_R_DP_ENCODER1_P0_FLDMASK 0xff00
1412
#define SDP_DB9_R_DP_ENCODER1_P0_FLDMASK_POS 8
1413
#define SDP_DB9_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1414
1415
#define REG_3254_DP_ENCODER1_P0 0x3254
1416
#define SDP_DB10_R_DP_ENCODER1_P0_FLDMASK 0xff
1417
#define SDP_DB10_R_DP_ENCODER1_P0_FLDMASK_POS 0
1418
#define SDP_DB10_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1419
1420
#define SDP_DB11_R_DP_ENCODER1_P0_FLDMASK 0xff00
1421
#define SDP_DB11_R_DP_ENCODER1_P0_FLDMASK_POS 8
1422
#define SDP_DB11_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1423
1424
#define REG_3258_DP_ENCODER1_P0 0x3258
1425
#define SDP_DB12_R_DP_ENCODER1_P0_FLDMASK 0xff
1426
#define SDP_DB12_R_DP_ENCODER1_P0_FLDMASK_POS 0
1427
#define SDP_DB12_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1428
1429
#define SDP_DB13_R_DP_ENCODER1_P0_FLDMASK 0xff00
1430
#define SDP_DB13_R_DP_ENCODER1_P0_FLDMASK_POS 8
1431
#define SDP_DB13_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1432
1433
#define REG_325C_DP_ENCODER1_P0 0x325C
1434
#define SDP_DB14_R_DP_ENCODER1_P0_FLDMASK 0xff
1435
#define SDP_DB14_R_DP_ENCODER1_P0_FLDMASK_POS 0
1436
#define SDP_DB14_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1437
1438
#define SDP_DB15_R_DP_ENCODER1_P0_FLDMASK 0xff00
1439
#define SDP_DB15_R_DP_ENCODER1_P0_FLDMASK_POS 8
1440
#define SDP_DB15_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1441
1442
#define REG_3260_DP_ENCODER1_P0 0x3260
1443
#define SDP_DB16_R_DP_ENCODER1_P0_FLDMASK 0xff
1444
#define SDP_DB16_R_DP_ENCODER1_P0_FLDMASK_POS 0
1445
#define SDP_DB16_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1446
1447
#define SDP_DB17_R_DP_ENCODER1_P0_FLDMASK 0xff00
1448
#define SDP_DB17_R_DP_ENCODER1_P0_FLDMASK_POS 8
1449
#define SDP_DB17_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1450
1451
#define REG_3264_DP_ENCODER1_P0 0x3264
1452
#define SDP_DB18_R_DP_ENCODER1_P0_FLDMASK 0xff
1453
#define SDP_DB18_R_DP_ENCODER1_P0_FLDMASK_POS 0
1454
#define SDP_DB18_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1455
1456
#define SDP_DB19_R_DP_ENCODER1_P0_FLDMASK 0xff00
1457
#define SDP_DB19_R_DP_ENCODER1_P0_FLDMASK_POS 8
1458
#define SDP_DB19_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1459
1460
#define REG_3268_DP_ENCODER1_P0 0x3268
1461
#define SDP_DB20_R_DP_ENCODER1_P0_FLDMASK 0xff
1462
#define SDP_DB20_R_DP_ENCODER1_P0_FLDMASK_POS 0
1463
#define SDP_DB20_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1464
1465
#define SDP_DB21_R_DP_ENCODER1_P0_FLDMASK 0xff00
1466
#define SDP_DB21_R_DP_ENCODER1_P0_FLDMASK_POS 8
1467
#define SDP_DB21_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1468
1469
#define REG_326C_DP_ENCODER1_P0 0x326C
1470
#define SDP_DB22_R_DP_ENCODER1_P0_FLDMASK 0xff
1471
#define SDP_DB22_R_DP_ENCODER1_P0_FLDMASK_POS 0
1472
#define SDP_DB22_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1473
1474
#define SDP_DB23_R_DP_ENCODER1_P0_FLDMASK 0xff00
1475
#define SDP_DB23_R_DP_ENCODER1_P0_FLDMASK_POS 8
1476
#define SDP_DB23_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1477
1478
#define REG_3270_DP_ENCODER1_P0 0x3270
1479
#define SDP_DB24_R_DP_ENCODER1_P0_FLDMASK 0xff
1480
#define SDP_DB24_R_DP_ENCODER1_P0_FLDMASK_POS 0
1481
#define SDP_DB24_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1482
1483
#define SDP_DB25_R_DP_ENCODER1_P0_FLDMASK 0xff00
1484
#define SDP_DB25_R_DP_ENCODER1_P0_FLDMASK_POS 8
1485
#define SDP_DB25_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1486
1487
#define REG_3274_DP_ENCODER1_P0 0x3274
1488
#define SDP_DB26_R_DP_ENCODER1_P0_FLDMASK 0xff
1489
#define SDP_DB26_R_DP_ENCODER1_P0_FLDMASK_POS 0
1490
#define SDP_DB26_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1491
1492
#define SDP_DB27_R_DP_ENCODER1_P0_FLDMASK 0xff00
1493
#define SDP_DB27_R_DP_ENCODER1_P0_FLDMASK_POS 8
1494
#define SDP_DB27_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1495
1496
#define REG_3278_DP_ENCODER1_P0 0x3278
1497
#define SDP_DB28_R_DP_ENCODER1_P0_FLDMASK 0xff
1498
#define SDP_DB28_R_DP_ENCODER1_P0_FLDMASK_POS 0
1499
#define SDP_DB28_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1500
1501
#define SDP_DB29_R_DP_ENCODER1_P0_FLDMASK 0xff00
1502
#define SDP_DB29_R_DP_ENCODER1_P0_FLDMASK_POS 8
1503
#define SDP_DB29_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1504
1505
#define REG_327C_DP_ENCODER1_P0 0x327C
1506
#define SDP_DB30_R_DP_ENCODER1_P0_FLDMASK 0xff
1507
#define SDP_DB30_R_DP_ENCODER1_P0_FLDMASK_POS 0
1508
#define SDP_DB30_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1509
1510
#define SDP_DB31_R_DP_ENCODER1_P0_FLDMASK 0xff00
1511
#define SDP_DB31_R_DP_ENCODER1_P0_FLDMASK_POS 8
1512
#define SDP_DB31_R_DP_ENCODER1_P0_FLDMASK_LEN 8
1513
1514
#define REG_3280_DP_ENCODER1_P0 0x3280
1515
#define SDP_PACKET_TYPE_DP_ENCODER1_P0_FLDMASK 0x1f
1516
#define SDP_PACKET_TYPE_DP_ENCODER1_P0_FLDMASK_POS 0
1517
#define SDP_PACKET_TYPE_DP_ENCODER1_P0_FLDMASK_LEN 5
1518
1519
#define SDP_PACKET_W_DP_ENCODER1_P0_FLDMASK 0x20
1520
#define SDP_PACKET_W_DP_ENCODER1_P0_FLDMASK_POS 5
1521
#define SDP_PACKET_W_DP_ENCODER1_P0_FLDMASK_LEN 1
1522
1523
#define SDP_PACKET_R_DP_ENCODER1_P0_FLDMASK 0x40
1524
#define SDP_PACKET_R_DP_ENCODER1_P0_FLDMASK_POS 6
1525
#define SDP_PACKET_R_DP_ENCODER1_P0_FLDMASK_LEN 1
1526
1527
#define REG_328C_DP_ENCODER1_P0 0x328C
1528
#define VSC_SW_HW_SEL_VESA_DP_ENCODER1_P0_FLDMASK 0x1
1529
#define VSC_SW_HW_SEL_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
1530
#define VSC_SW_HW_SEL_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1531
1532
#define VSC_SRAM_HW_RST_VESA_DP_ENCODER1_P0_FLDMASK 0x2
1533
#define VSC_SRAM_HW_RST_VESA_DP_ENCODER1_P0_FLDMASK_POS 1
1534
#define VSC_SRAM_HW_RST_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1535
1536
#define VSC_SRAM_SW_RST_VESA_DP_ENCODER1_P0_FLDMASK 0x4
1537
#define VSC_SRAM_SW_RST_VESA_DP_ENCODER1_P0_FLDMASK_POS 2
1538
#define VSC_SRAM_SW_RST_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1539
1540
#define VSC_SRAM_HW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK 0x8
1541
#define VSC_SRAM_HW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK_POS 3
1542
#define VSC_SRAM_HW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1543
1544
#define VSC_SRAM_HW_FULL_VESA_DP_ENCODER1_P0_FLDMASK 0x10
1545
#define VSC_SRAM_HW_FULL_VESA_DP_ENCODER1_P0_FLDMASK_POS 4
1546
#define VSC_SRAM_HW_FULL_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1547
1548
#define VSC_SRAM_HW_FULL_CLR_VESA_DP_ENCODER1_P0_FLDMASK 0x20
1549
#define VSC_SRAM_HW_FULL_CLR_VESA_DP_ENCODER1_P0_FLDMASK_POS 5
1550
#define VSC_SRAM_HW_FULL_CLR_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1551
1552
#define VSC_DATA_TOGGLE_VESA_DP_ENCODER1_P0_FLDMASK 0x40
1553
#define VSC_DATA_TOGGLE_VESA_DP_ENCODER1_P0_FLDMASK_POS 6
1554
#define VSC_DATA_TOGGLE_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1555
1556
#define VSC_DATA_RDY_VESA_DP_ENCODER1_P0_FLDMASK 0x80
1557
#define VSC_DATA_RDY_VESA_DP_ENCODER1_P0_FLDMASK_POS 7
1558
#define VSC_DATA_RDY_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1559
1560
#define VSC_SRAM_SW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK 0x100
1561
#define VSC_SRAM_SW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
1562
#define VSC_SRAM_SW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1563
1564
#define REG_3290_DP_ENCODER1_P0 0x3290
1565
#define VSC_DATA_BYTE0_VESA_DP_ENCODER1_P0_FLDMASK 0xff
1566
#define VSC_DATA_BYTE0_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
1567
#define VSC_DATA_BYTE0_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
1568
1569
#define VSC_DATA_BYTE1_VESA_DP_ENCODER1_P0_FLDMASK 0xff00
1570
#define VSC_DATA_BYTE1_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
1571
#define VSC_DATA_BYTE1_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
1572
1573
#define REG_3294_DP_ENCODER1_P0 0x3294
1574
#define VSC_DATA_BYTE2_VESA_DP_ENCODER1_P0_FLDMASK 0xff
1575
#define VSC_DATA_BYTE2_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
1576
#define VSC_DATA_BYTE2_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
1577
1578
#define VSC_DATA_BYTE3_VESA_DP_ENCODER1_P0_FLDMASK 0xff00
1579
#define VSC_DATA_BYTE3_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
1580
#define VSC_DATA_BYTE3_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
1581
1582
#define REG_3298_DP_ENCODER1_P0 0x3298
1583
#define VSC_DATA_BYTE4_VESA_DP_ENCODER1_P0_FLDMASK 0xff
1584
#define VSC_DATA_BYTE4_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
1585
#define VSC_DATA_BYTE4_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
1586
1587
#define VSC_DATA_BYTE5_VESA_DP_ENCODER1_P0_FLDMASK 0xff00
1588
#define VSC_DATA_BYTE5_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
1589
#define VSC_DATA_BYTE5_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
1590
1591
#define REG_329C_DP_ENCODER1_P0 0x329C
1592
#define VSC_DATA_BYTE6_VESA_DP_ENCODER1_P0_FLDMASK 0xff
1593
#define VSC_DATA_BYTE6_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
1594
#define VSC_DATA_BYTE6_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
1595
1596
#define VSC_DATA_BYTE7_VESA_DP_ENCODER1_P0_FLDMASK 0xff00
1597
#define VSC_DATA_BYTE7_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
1598
#define VSC_DATA_BYTE7_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
1599
1600
#define REG_32A0_DP_ENCODER1_P0 0x32A0
1601
#define VSC_SW_HW_SEL_CEA_DP_ENCODER1_P0_FLDMASK 0x1
1602
#define VSC_SW_HW_SEL_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
1603
#define VSC_SW_HW_SEL_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1604
1605
#define VSC_SRAM_HW_RST_CEA_DP_ENCODER1_P0_FLDMASK 0x2
1606
#define VSC_SRAM_HW_RST_CEA_DP_ENCODER1_P0_FLDMASK_POS 1
1607
#define VSC_SRAM_HW_RST_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1608
1609
#define VSC_SRAM_SW_RST_CEA_DP_ENCODER1_P0_FLDMASK 0x4
1610
#define VSC_SRAM_SW_RST_CEA_DP_ENCODER1_P0_FLDMASK_POS 2
1611
#define VSC_SRAM_SW_RST_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1612
1613
#define VSC_SRAM_HW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK 0x8
1614
#define VSC_SRAM_HW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK_POS 3
1615
#define VSC_SRAM_HW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1616
1617
#define VSC_SRAM_HW_FULL_CEA_DP_ENCODER1_P0_FLDMASK 0x10
1618
#define VSC_SRAM_HW_FULL_CEA_DP_ENCODER1_P0_FLDMASK_POS 4
1619
#define VSC_SRAM_HW_FULL_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1620
1621
#define VSC_SRAM_HW_FULL_CLR_CEA_DP_ENCODER1_P0_FLDMASK 0x20
1622
#define VSC_SRAM_HW_FULL_CLR_CEA_DP_ENCODER1_P0_FLDMASK_POS 5
1623
#define VSC_SRAM_HW_FULL_CLR_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1624
1625
#define VSC_DATA_TOGGLE_CEA_DP_ENCODER1_P0_FLDMASK 0x40
1626
#define VSC_DATA_TOGGLE_CEA_DP_ENCODER1_P0_FLDMASK_POS 6
1627
#define VSC_DATA_TOGGLE_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1628
1629
#define VSC_DATA_RDY_CEA_DP_ENCODER1_P0_FLDMASK 0x80
1630
#define VSC_DATA_RDY_CEA_DP_ENCODER1_P0_FLDMASK_POS 7
1631
#define VSC_DATA_RDY_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1632
1633
#define VSC_SRAM_SW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK 0x100
1634
#define VSC_SRAM_SW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
1635
#define VSC_SRAM_SW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1636
1637
#define REG_32A4_DP_ENCODER1_P0 0x32A4
1638
#define VSC_DATA_BYTE0_CEA_DP_ENCODER1_P0_FLDMASK 0xff
1639
#define VSC_DATA_BYTE0_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
1640
#define VSC_DATA_BYTE0_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
1641
1642
#define VSC_DATA_BYTE1_CEA_DP_ENCODER1_P0_FLDMASK 0xff00
1643
#define VSC_DATA_BYTE1_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
1644
#define VSC_DATA_BYTE1_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
1645
1646
#define REG_32A8_DP_ENCODER1_P0 0x32A8
1647
#define VSC_DATA_BYTE2_CEA_DP_ENCODER1_P0_FLDMASK 0xff
1648
#define VSC_DATA_BYTE2_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
1649
#define VSC_DATA_BYTE2_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
1650
1651
#define VSC_DATA_BYTE3_CEA_DP_ENCODER1_P0_FLDMASK 0xff00
1652
#define VSC_DATA_BYTE3_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
1653
#define VSC_DATA_BYTE3_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
1654
1655
#define REG_32AC_DP_ENCODER1_P0 0x32AC
1656
#define VSC_DATA_BYTE4_CEA_DP_ENCODER1_P0_FLDMASK 0xff
1657
#define VSC_DATA_BYTE4_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
1658
#define VSC_DATA_BYTE4_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
1659
1660
#define VSC_DATA_BYTE5_CEA_DP_ENCODER1_P0_FLDMASK 0xff00
1661
#define VSC_DATA_BYTE5_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
1662
#define VSC_DATA_BYTE5_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
1663
1664
#define REG_32B0_DP_ENCODER1_P0 0x32B0
1665
#define VSC_DATA_BYTE6_CEA_DP_ENCODER1_P0_FLDMASK 0xff
1666
#define VSC_DATA_BYTE6_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
1667
#define VSC_DATA_BYTE6_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
1668
1669
#define VSC_DATA_BYTE7_CEA_DP_ENCODER1_P0_FLDMASK 0xff00
1670
#define VSC_DATA_BYTE7_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
1671
#define VSC_DATA_BYTE7_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
1672
1673
#define REG_32B4_DP_ENCODER1_P0 0x32B4
1674
#define VSC_DATA_SW_CAN_WRITE_VESA_DP_ENCODER1_P0_FLDMASK 0x1
1675
#define VSC_DATA_SW_CAN_WRITE_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
1676
#define VSC_DATA_SW_CAN_WRITE_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1677
1678
#define VSC_DATA_SW_CAN_WRITE_CEA_DP_ENCODER1_P0_FLDMASK 0x2
1679
#define VSC_DATA_SW_CAN_WRITE_CEA_DP_ENCODER1_P0_FLDMASK_POS 1
1680
#define VSC_DATA_SW_CAN_WRITE_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1681
1682
#define VSC_DATA_TRANSMIT_SEL_VESA_DP_ENCODER1_P0_FLDMASK 0x4
1683
#define VSC_DATA_TRANSMIT_SEL_VESA_DP_ENCODER1_P0_FLDMASK_POS 2
1684
#define VSC_DATA_TRANSMIT_SEL_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
1685
1686
#define VSC_DATA_TRANSMIT_SEL_CEA_DP_ENCODER1_P0_FLDMASK 0x8
1687
#define VSC_DATA_TRANSMIT_SEL_CEA_DP_ENCODER1_P0_FLDMASK_POS 3
1688
#define VSC_DATA_TRANSMIT_SEL_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
1689
1690
#define REG_32C0_DP_ENCODER1_P0 0x32C0
1691
#define IRQ_MASK_DP_ENCODER1_P0_FLDMASK 0xffff
1692
#define IRQ_MASK_DP_ENCODER1_P0_FLDMASK_POS 0
1693
#define IRQ_MASK_DP_ENCODER1_P0_FLDMASK_LEN 16
1694
1695
#define REG_32C4_DP_ENCODER1_P0 0x32C4
1696
#define IRQ_CLR_DP_ENCODER1_P0_FLDMASK 0xffff
1697
#define IRQ_CLR_DP_ENCODER1_P0_FLDMASK_POS 0
1698
#define IRQ_CLR_DP_ENCODER1_P0_FLDMASK_LEN 16
1699
1700
#define REG_32C8_DP_ENCODER1_P0 0x32C8
1701
#define IRQ_FORCE_DP_ENCODER1_P0_FLDMASK 0xffff
1702
#define IRQ_FORCE_DP_ENCODER1_P0_FLDMASK_POS 0
1703
#define IRQ_FORCE_DP_ENCODER1_P0_FLDMASK_LEN 16
1704
1705
#define REG_32CC_DP_ENCODER1_P0 0x32CC
1706
#define IRQ_STATUS_DP_ENCODER1_P0_FLDMASK 0xffff
1707
#define IRQ_STATUS_DP_ENCODER1_P0_FLDMASK_POS 0
1708
#define IRQ_STATUS_DP_ENCODER1_P0_FLDMASK_LEN 16
1709
1710
#define REG_32D0_DP_ENCODER1_P0 0x32D0
1711
#define IRQ_FINAL_STATUS_DP_ENCODER1_P0_FLDMASK 0xffff
1712
#define IRQ_FINAL_STATUS_DP_ENCODER1_P0_FLDMASK_POS 0
1713
#define IRQ_FINAL_STATUS_DP_ENCODER1_P0_FLDMASK_LEN 16
1714
1715
#define REG_32D4_DP_ENCODER1_P0 0x32D4
1716
#define IRQ_MASK_51_DP_ENCODER1_P0_FLDMASK 0xffff
1717
#define IRQ_MASK_51_DP_ENCODER1_P0_FLDMASK_POS 0
1718
#define IRQ_MASK_51_DP_ENCODER1_P0_FLDMASK_LEN 16
1719
1720
#define REG_32D8_DP_ENCODER1_P0 0x32D8
1721
#define IRQ_CLR_51_DP_ENCODER1_P0_FLDMASK 0xffff
1722
#define IRQ_CLR_51_DP_ENCODER1_P0_FLDMASK_POS 0
1723
#define IRQ_CLR_51_DP_ENCODER1_P0_FLDMASK_LEN 16
1724
1725
#define REG_32DC_DP_ENCODER1_P0 0x32DC
1726
#define IRQ_FORCE_51_DP_ENCODER1_P0_FLDMASK 0xffff
1727
#define IRQ_FORCE_51_DP_ENCODER1_P0_FLDMASK_POS 0
1728
#define IRQ_FORCE_51_DP_ENCODER1_P0_FLDMASK_LEN 16
1729
1730
#define REG_32E0_DP_ENCODER1_P0 0x32E0
1731
#define IRQ_STATUS_51_DP_ENCODER1_P0_FLDMASK 0xffff
1732
#define IRQ_STATUS_51_DP_ENCODER1_P0_FLDMASK_POS 0
1733
#define IRQ_STATUS_51_DP_ENCODER1_P0_FLDMASK_LEN 16
1734
1735
#define REG_32E4_DP_ENCODER1_P0 0x32E4
1736
#define IRQ_FINAL_STATUS_51_DP_ENCODER1_P0_FLDMASK 0xffff
1737
#define IRQ_FINAL_STATUS_51_DP_ENCODER1_P0_FLDMASK_POS 0
1738
#define IRQ_FINAL_STATUS_51_DP_ENCODER1_P0_FLDMASK_LEN 16
1739
1740
#define REG_32E8_DP_ENCODER1_P0 0x32E8
1741
#define AUDIO_SRAM_WRITE_ADDR_0_DP_ENCODER1_P0_FLDMASK 0x7f
1742
#define AUDIO_SRAM_WRITE_ADDR_0_DP_ENCODER1_P0_FLDMASK_POS 0
1743
#define AUDIO_SRAM_WRITE_ADDR_0_DP_ENCODER1_P0_FLDMASK_LEN 7
1744
1745
#define AUDIO_SRAM_WRITE_ADDR_1_DP_ENCODER1_P0_FLDMASK 0x7f00
1746
#define AUDIO_SRAM_WRITE_ADDR_1_DP_ENCODER1_P0_FLDMASK_POS 8
1747
#define AUDIO_SRAM_WRITE_ADDR_1_DP_ENCODER1_P0_FLDMASK_LEN 7
1748
1749
#define REG_32EC_DP_ENCODER1_P0 0x32EC
1750
#define AUDIO_SRAM_WRITE_ADDR_2_DP_ENCODER1_P0_FLDMASK 0x7f
1751
#define AUDIO_SRAM_WRITE_ADDR_2_DP_ENCODER1_P0_FLDMASK_POS 0
1752
#define AUDIO_SRAM_WRITE_ADDR_2_DP_ENCODER1_P0_FLDMASK_LEN 7
1753
1754
#define AUDIO_SRAM_WRITE_ADDR_3_DP_ENCODER1_P0_FLDMASK 0x7f00
1755
#define AUDIO_SRAM_WRITE_ADDR_3_DP_ENCODER1_P0_FLDMASK_POS 8
1756
#define AUDIO_SRAM_WRITE_ADDR_3_DP_ENCODER1_P0_FLDMASK_LEN 7
1757
1758
#define REG_32F0_DP_ENCODER1_P0 0x32F0
1759
#define M_CODE_FEC_MERGE_0_DP_ENCODER1_P0_FLDMASK 0xffff
1760
#define M_CODE_FEC_MERGE_0_DP_ENCODER1_P0_FLDMASK_POS 0
1761
#define M_CODE_FEC_MERGE_0_DP_ENCODER1_P0_FLDMASK_LEN 16
1762
1763
#define REG_32F4_DP_ENCODER1_P0 0x32F4
1764
#define M_CODE_FEC_MERGE_1_DP_ENCODER1_P0_FLDMASK 0xff
1765
#define M_CODE_FEC_MERGE_1_DP_ENCODER1_P0_FLDMASK_POS 0
1766
#define M_CODE_FEC_MERGE_1_DP_ENCODER1_P0_FLDMASK_LEN 8
1767
1768
#define REG_32F8_DP_ENCODER1_P0 0x32F8
1769
#define MSA_UPDATE_LINE_CNT_THRD_DP_ENCODER1_P0_FLDMASK 0xff
1770
#define MSA_UPDATE_LINE_CNT_THRD_DP_ENCODER1_P0_FLDMASK_POS 0
1771
#define MSA_UPDATE_LINE_CNT_THRD_DP_ENCODER1_P0_FLDMASK_LEN 8
1772
1773
#define SDP_SPLIT_BUG_FIX_DP_ENCODER1_P0_FLDMASK 0x200
1774
#define SDP_SPLIT_BUG_FIX_DP_ENCODER1_P0_FLDMASK_POS 9
1775
#define SDP_SPLIT_BUG_FIX_DP_ENCODER1_P0_FLDMASK_LEN 1
1776
1777
#define MSA_MUTE_MASK_DP_ENCODER1_P0_FLDMASK 0x400
1778
#define MSA_MUTE_MASK_DP_ENCODER1_P0_FLDMASK_POS 10
1779
#define MSA_MUTE_MASK_DP_ENCODER1_P0_FLDMASK_LEN 1
1780
1781
#define MSA_UPDATE_SEL_DP_ENCODER1_P0_FLDMASK 0x3000
1782
#define MSA_UPDATE_SEL_DP_ENCODER1_P0_FLDMASK_POS 12
1783
#define MSA_UPDATE_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
1784
1785
#define VIDEO_MUTE_TOGGLE_SEL_DP_ENCODER1_P0_FLDMASK 0xc000
1786
#define VIDEO_MUTE_TOGGLE_SEL_DP_ENCODER1_P0_FLDMASK_POS 14
1787
#define VIDEO_MUTE_TOGGLE_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
1788
1789
#define REG_3300_DP_ENCODER1_P0 0x3300
1790
#define AUDIO_AFIFO_CNT_SEL_DP_ENCODER1_P0_FLDMASK 0x1
1791
#define AUDIO_AFIFO_CNT_SEL_DP_ENCODER1_P0_FLDMASK_POS 0
1792
#define AUDIO_AFIFO_CNT_SEL_DP_ENCODER1_P0_FLDMASK_LEN 1
1793
1794
#define AUDIO_SRAM_CNT_SEL_DP_ENCODER1_P0_FLDMASK 0x2
1795
#define AUDIO_SRAM_CNT_SEL_DP_ENCODER1_P0_FLDMASK_POS 1
1796
#define AUDIO_SRAM_CNT_SEL_DP_ENCODER1_P0_FLDMASK_LEN 1
1797
1798
#define AUDIO_AFIFO_CNT_DP_ENCODER1_P0_FLDMASK 0xf0
1799
#define AUDIO_AFIFO_CNT_DP_ENCODER1_P0_FLDMASK_POS 4
1800
#define AUDIO_AFIFO_CNT_DP_ENCODER1_P0_FLDMASK_LEN 4
1801
1802
#define VIDEO_AFIFO_RDY_SEL_DP_ENCODER1_P0_FLDMASK 0x300
1803
#define VIDEO_AFIFO_RDY_SEL_DP_ENCODER1_P0_FLDMASK_POS 8
1804
#define VIDEO_AFIFO_RDY_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
1805
1806
#define REG_3304_DP_ENCODER1_P0 0x3304
1807
#define AUDIO_SRAM_CNT_DP_ENCODER1_P0_FLDMASK 0x7f
1808
#define AUDIO_SRAM_CNT_DP_ENCODER1_P0_FLDMASK_POS 0
1809
#define AUDIO_SRAM_CNT_DP_ENCODER1_P0_FLDMASK_LEN 7
1810
1811
#define AU_PRTY_REGEN_DP_ENCODER1_P0_FLDMASK 0x100
1812
#define AU_PRTY_REGEN_DP_ENCODER1_P0_FLDMASK_POS 8
1813
#define AU_PRTY_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
1814
1815
#define AU_CH_STS_REGEN_DP_ENCODER1_P0_FLDMASK 0x200
1816
#define AU_CH_STS_REGEN_DP_ENCODER1_P0_FLDMASK_POS 9
1817
#define AU_CH_STS_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
1818
1819
#define AUDIO_VALIDITY_REGEN_DP_ENCODER1_P0_FLDMASK 0x400
1820
#define AUDIO_VALIDITY_REGEN_DP_ENCODER1_P0_FLDMASK_POS 10
1821
#define AUDIO_VALIDITY_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
1822
1823
#define AUDIO_RESERVED_REGEN_DP_ENCODER1_P0_FLDMASK 0x800
1824
#define AUDIO_RESERVED_REGEN_DP_ENCODER1_P0_FLDMASK_POS 11
1825
#define AUDIO_RESERVED_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
1826
1827
#define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENCODER1_P0_FLDMASK 0x1000
1828
#define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENCODER1_P0_FLDMASK_POS 12
1829
#define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
1830
1831
#define REG_3320_DP_ENCODER1_P0 0x3320
1832
#define AUDIO_PATTERN_GEN_DSTB_CNT_THRD_DP_ENCODER1_P0_FLDMASK 0x1ff
1833
#define AUDIO_PATTERN_GEN_DSTB_CNT_THRD_DP_ENCODER1_P0_FLDMASK_POS 0
1834
#define AUDIO_PATTERN_GEN_DSTB_CNT_THRD_DP_ENCODER1_P0_FLDMASK_LEN 9
1835
1836
#define REG_3324_DP_ENCODER1_P0 0x3324
1837
#define AUDIO_SOURCE_MUX_DP_ENCODER1_P0_FLDMASK 0x300
1838
#define AUDIO_SOURCE_MUX_DP_ENCODER1_P0_FLDMASK_POS 8
1839
#define AUDIO_SOURCE_MUX_DP_ENCODER1_P0_FLDMASK_LEN 2
1840
1841
#define AUDIO_PATTERN_GEN_CH_NUM_DP_ENCODER1_P0_FLDMASK 0x3000
1842
#define AUDIO_PATGEN_CH_NUM_DP_ENCODER1_P0_FLDMASK_POS 12
1843
#define AUDIO_PATTERN_GEN_CH_NUM_DP_ENCODER1_P0_FLDMASK_LEN 2
1844
1845
#define AUDIO_PATTERN_GEN_FS_SEL_DP_ENCODER1_P0_FLDMASK 0xc000
1846
#define AUDIO_PATGEN_FS_SEL_DP_ENCODER1_P0_FLDMASK_POS 14
1847
#define AUDIO_PATTERN_GEN_FS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
1848
1849
#define REG_3328_DP_ENCODER1_P0 0x3328
1850
#define VSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK 0x1
1851
#define VSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK_POS 0
1852
#define VSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK_LEN 1
1853
1854
#define HSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK 0x2
1855
#define HSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK_POS 1
1856
#define HSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK_LEN 1
1857
1858
#define HTOTAL_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK 0x4
1859
#define HTOTAL_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK_POS 2
1860
#define HTOTAL_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK_LEN 1
1861
1862
#define HDE_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK 0x8
1863
#define HDE_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK_POS 3
1864
#define HDE_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK_LEN 1
1865
1866
#define REG_332C_DP_ENCODER1_P0 0x332C
1867
#define VTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK 0xffff
1868
#define VTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK_POS 0
1869
#define VTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK_LEN 16
1870
1871
#define REG_3330_DP_ENCODER1_P0 0x3330
1872
#define VDE_DETECT_DP_ENCODER1_P0_FLDMASK 0xffff
1873
#define VDE_DETECT_DP_ENCODER1_P0_FLDMASK_POS 0
1874
#define VDE_DETECT_DP_ENCODER1_P0_FLDMASK_LEN 16
1875
1876
#define REG_3334_DP_ENCODER1_P0 0x3334
1877
#define HTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK 0xffff
1878
#define HTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK_POS 0
1879
#define HTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK_LEN 16
1880
1881
#define REG_3338_DP_ENCODER1_P0 0x3338
1882
#define HDE_DETECT_DP_ENCODER1_P0_FLDMASK 0xffff
1883
#define HDE_DETECT_DP_ENCODER1_P0_FLDMASK_POS 0
1884
#define HDE_DETECT_DP_ENCODER1_P0_FLDMASK_LEN 16
1885
1886
#define REG_3340_DP_ENCODER1_P0 0x3340
1887
#define BIST_FAIL_VIDEO_L0_DP_ENCODER1_P0_FLDMASK 0x1
1888
#define BIST_FAIL_VIDEO_L0_DP_ENCODER1_P0_FLDMASK_POS 0
1889
#define BIST_FAIL_VIDEO_L0_DP_ENCODER1_P0_FLDMASK_LEN 1
1890
1891
#define BIST_FAIL_VIDEO_L1_DP_ENCODER1_P0_FLDMASK 0x2
1892
#define BIST_FAIL_VIDEO_L1_DP_ENCODER1_P0_FLDMASK_POS 1
1893
#define BIST_FAIL_VIDEO_L1_DP_ENCODER1_P0_FLDMASK_LEN 1
1894
1895
#define BIST_FAIL_VIDEO_L2_DP_ENCODER1_P0_FLDMASK 0x4
1896
#define BIST_FAIL_VIDEO_L2_DP_ENCODER1_P0_FLDMASK_POS 2
1897
#define BIST_FAIL_VIDEO_L2_DP_ENCODER1_P0_FLDMASK_LEN 1
1898
1899
#define BIST_FAIL_VIDEO_L3_DP_ENCODER1_P0_FLDMASK 0x8
1900
#define BIST_FAIL_VIDEO_L3_DP_ENCODER1_P0_FLDMASK_POS 3
1901
#define BIST_FAIL_VIDEO_L3_DP_ENCODER1_P0_FLDMASK_LEN 1
1902
1903
#define BIST_FAIL_AUDIO_L0_DP_ENCODER1_P0_FLDMASK 0x10
1904
#define BIST_FAIL_AUDIO_L0_DP_ENCODER1_P0_FLDMASK_POS 4
1905
#define BIST_FAIL_AUDIO_L0_DP_ENCODER1_P0_FLDMASK_LEN 1
1906
1907
#define BIST_FAIL_AUDIO_L1_DP_ENCODER1_P0_FLDMASK 0x20
1908
#define BIST_FAIL_AUDIO_L1_DP_ENCODER1_P0_FLDMASK_POS 5
1909
#define BIST_FAIL_AUDIO_L1_DP_ENCODER1_P0_FLDMASK_LEN 1
1910
1911
#define BIST_FAIL_AUDIO_L2_DP_ENCODER1_P0_FLDMASK 0x40
1912
#define BIST_FAIL_AUDIO_L2_DP_ENCODER1_P0_FLDMASK_POS 6
1913
#define BIST_FAIL_AUDIO_L2_DP_ENCODER1_P0_FLDMASK_LEN 1
1914
1915
#define BIST_FAIL_AUDIO_L3_DP_ENCODER1_P0_FLDMASK 0x80
1916
#define BIST_FAIL_AUDIO_L3_DP_ENCODER1_P0_FLDMASK_POS 7
1917
#define BIST_FAIL_AUDIO_L3_DP_ENCODER1_P0_FLDMASK_LEN 1
1918
1919
#define BIST_FAIL_VSC_VESA_HW_DP_ENCODER1_P0_FLDMASK 0x100
1920
#define BIST_FAIL_VSC_VESA_HW_DP_ENCODER1_P0_FLDMASK_POS 8
1921
#define BIST_FAIL_VSC_VESA_HW_DP_ENCODER1_P0_FLDMASK_LEN 1
1922
1923
#define BIST_FAIL_VSC_CEA_HW_DP_ENCODER1_P0_FLDMASK 0x200
1924
#define BIST_FAIL_VSC_CEA_HW_DP_ENCODER1_P0_FLDMASK_POS 9
1925
#define BIST_FAIL_VSC_CEA_HW_DP_ENCODER1_P0_FLDMASK_LEN 1
1926
1927
#define BIST_FAIL_VSC_VESA_SW_DP_ENCODER1_P0_FLDMASK 0x400
1928
#define BIST_FAIL_VSC_VESA_SW_DP_ENCODER1_P0_FLDMASK_POS 10
1929
#define BIST_FAIL_VSC_VESA_SW_DP_ENCODER1_P0_FLDMASK_LEN 1
1930
1931
#define BIST_FAIL_VSC_CEA_SW_DP_ENCODER1_P0_FLDMASK 0x800
1932
#define BIST_FAIL_VSC_CEA_SW_DP_ENCODER1_P0_FLDMASK_POS 11
1933
#define BIST_FAIL_VSC_CEA_SW_DP_ENCODER1_P0_FLDMASK_LEN 1
1934
1935
#define LR_FIELD_SYNC_SEL_DP_ENCODER1_P0_FLDMASK 0x7000
1936
#define LR_FIELD_SYNC_SEL_DP_ENCODER1_P0_FLDMASK_POS 12
1937
#define LR_FIELD_SYNC_SEL_DP_ENCODER1_P0_FLDMASK_LEN 3
1938
1939
#define REG_3344_DP_ENCODER1_P0 0x3344
1940
#define DP_CH1_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f
1941
#define DP_CH1_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 0
1942
#define DP_CH1_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
1943
1944
#define DP_CH2_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f00
1945
#define DP_CH2_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 8
1946
#define DP_CH2_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
1947
1948
#define REG_3348_DP_ENCODER1_P0 0x3348
1949
#define DP_CH3_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f
1950
#define DP_CH3_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 0
1951
#define DP_CH3_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
1952
1953
#define DP_CH4_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f00
1954
#define DP_CH4_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 8
1955
#define DP_CH4_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
1956
1957
#define REG_334C_DP_ENCODER1_P0 0x334C
1958
#define DP_CH5_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f
1959
#define DP_CH5_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 0
1960
#define DP_CH5_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
1961
1962
#define DP_CH6_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f00
1963
#define DP_CH6_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 8
1964
#define DP_CH6_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
1965
1966
#define REG_3350_DP_ENCODER1_P0 0x3350
1967
#define DP_CH7_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f
1968
#define DP_CH7_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 0
1969
#define DP_CH7_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
1970
1971
#define DP_CH8_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f00
1972
#define DP_CH8_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 8
1973
#define DP_CH8_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
1974
1975
#define REG_3354_DP_ENCODER1_P0 0x3354
1976
#define DP_S2P_LAUNCH_CFG_DP_ENCODER1_P0_FLDMASK 0x7f
1977
#define DP_S2P_LAUNCH_CFG_DP_ENCODER1_P0_FLDMASK_POS 0
1978
#define DP_S2P_LAUNCH_CFG_DP_ENCODER1_P0_FLDMASK_LEN 7
1979
1980
#define AUDIO_HAYDN_EN_FORCE_DP_ENCODER1_P0_FLDMASK 0x1000
1981
#define AUDIO_HAYDN_EN_FORCE_DP_ENCODER1_P0_FLDMASK_POS 12
1982
#define AUDIO_HAYDN_EN_FORCE_DP_ENCODER1_P0_FLDMASK_LEN 1
1983
1984
#define AUDIO_HAYDN_FORMAT_DP_ENCODER1_P0_FLDMASK 0xf00
1985
#define AUDIO_HAYDN_FORMAT_DP_ENCODER1_P0_FLDMASK_POS 8
1986
#define AUDIO_HAYDN_FORMAT_DP_ENCODER1_P0_FLDMASK_LEN 4
1987
1988
#define REG_3358_DP_ENCODER1_P0 0x3358
1989
#define TU_SIZE_DP_ENCODER1_P0_FLDMASK 0x7f
1990
#define TU_SIZE_DP_ENCODER1_P0_FLDMASK_POS 0
1991
#define TU_SIZE_DP_ENCODER1_P0_FLDMASK_LEN 7
1992
1993
#define TU_CALC_SW_DP_ENCODER1_P0_FLDMASK 0x80
1994
#define TU_CALC_SW_DP_ENCODER1_P0_FLDMASK_POS 7
1995
#define TU_CALC_SW_DP_ENCODER1_P0_FLDMASK_LEN 1
1996
1997
#define REG_335C_DP_ENCODER1_P0 0x335C
1998
#define SYMBOL_DATA_PER_TU_SW_0_DP_ENCODER1_P0_FLDMASK 0xffff
1999
#define SYMBOL_DATA_PER_TU_SW_0_DP_ENCODER1_P0_FLDMASK_POS 0
2000
#define SYMBOL_DATA_PER_TU_SW_0_DP_ENCODER1_P0_FLDMASK_LEN 16
2001
2002
#define REG_3360_DP_ENCODER1_P0 0x3360
2003
#define SYMBOL_DATA_PER_TU_SW_1_DP_ENCODER1_P0_FLDMASK 0x7fff
2004
#define SYMBOL_DATA_PER_TU_SW_1_DP_ENCODER1_P0_FLDMASK_POS 0
2005
#define SYMBOL_DATA_PER_TU_SW_1_DP_ENCODER1_P0_FLDMASK_LEN 15
2006
2007
#define REG_3364_DP_ENCODER1_P0 0x3364
2008
#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENCODER1_P0_FLDMASK 0xfff
2009
#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENCODER1_P0_FLDMASK_POS 0
2010
#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENCODER1_P0_FLDMASK_LEN 12
2011
2012
#define FIFO_READ_START_POINT_DP_ENCODER1_P0_FLDMASK 0xf000
2013
#define FIFO_READ_START_POINT_DP_ENCODER1_P0_FLDMASK_POS 12
2014
#define FIFO_READ_START_POINT_DP_ENCODER1_P0_FLDMASK_LEN 4
2015
2016
#define REG_3368_DP_ENCODER1_P0 0x3368
2017
#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENCODER1_P0_FLDMASK 0x3
2018
#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENCODER1_P0_FLDMASK_POS 0
2019
#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
2020
2021
#define VIDEO_STABLE_EN_DP_ENCODER1_P0_FLDMASK 0x4
2022
#define VIDEO_STABLE_EN_DP_ENCODER1_P0_FLDMASK_POS 2
2023
#define VIDEO_STABLE_EN_DP_ENCODER1_P0_FLDMASK_LEN 1
2024
2025
#define VIDEO_STABLE_CNT_THRD_DP_ENCODER1_P0_FLDMASK 0xf0
2026
#define VIDEO_STABLE_CNT_THRD_DP_ENCODER1_P0_FLDMASK_POS 4
2027
#define VIDEO_STABLE_CNT_THRD_DP_ENCODER1_P0_FLDMASK_LEN 4
2028
2029
#define SDP_DP13_EN_DP_ENCODER1_P0_FLDMASK 0x100
2030
#define SDP_DP13_EN_DP_ENCODER1_P0_FLDMASK_POS 8
2031
#define SDP_DP13_EN_DP_ENCODER1_P0_FLDMASK_LEN 1
2032
2033
#define VIDEO_PIXEL_SWAP_DP_ENCODER1_P0_FLDMASK 0x600
2034
#define VIDEO_PIXEL_SWAP_DP_ENCODER1_P0_FLDMASK_POS 9
2035
#define VIDEO_PIXEL_SWAP_DP_ENCODER1_P0_FLDMASK_LEN 2
2036
2037
#define BS2BS_MODE_DP_ENCODER1_P0_FLDMASK 0x3000
2038
#define BS2BS_MODE_DP_ENCODER1_P0_FLDMASK_POS 12
2039
#define BS2BS_MODE_DP_ENCODER1_P0_FLDMASK_LEN 2
2040
2041
#define REG_336C_DP_ENCODER1_P0 0x336C
2042
#define DSC_EN_DP_ENCODER1_P0_FLDMASK 0x1
2043
#define DSC_EN_DP_ENCODER1_P0_FLDMASK_POS 0
2044
#define DSC_EN_DP_ENCODER1_P0_FLDMASK_LEN 1
2045
2046
#define DSC_BYTE_SWAP_DP_ENCODER1_P0_FLDMASK 0x2
2047
#define DSC_BYTE_SWAP_DP_ENCODER1_P0_FLDMASK_POS 1
2048
#define DSC_BYTE_SWAP_DP_ENCODER1_P0_FLDMASK_LEN 1
2049
2050
#define DSC_SLICE_NUM_DP_ENCODER1_P0_FLDMASK 0xf0
2051
#define DSC_SLICE_NUM_DP_ENCODER1_P0_FLDMASK_POS 4
2052
#define DSC_SLICE_NUM_DP_ENCODER1_P0_FLDMASK_LEN 4
2053
2054
#define DSC_CHUNK_REMAINDER_DP_ENCODER1_P0_FLDMASK 0xf00
2055
#define DSC_CHUNK_REMAINDER_DP_ENCODER1_P0_FLDMASK_POS 8
2056
#define DSC_CHUNK_REMAINDER_DP_ENCODER1_P0_FLDMASK_LEN 4
2057
2058
#define REG_3370_DP_ENCODER1_P0 0x3370
2059
#define DSC_CHUNK_NUM_DP_ENCODER1_P0_FLDMASK 0xffff
2060
#define DSC_CHUNK_NUM_DP_ENCODER1_P0_FLDMASK_POS 0
2061
#define DSC_CHUNK_NUM_DP_ENCODER1_P0_FLDMASK_LEN 16
2062
2063
#define REG_33AC_DP_ENCODER1_P0 0x33AC
2064
#define TEST_CRC_R_CR_DP_ENCODER1_P0_FLDMASK 0xffff
2065
#define TEST_CRC_R_CR_DP_ENCODER1_P0_FLDMASK_POS 0
2066
#define TEST_CRC_R_CR_DP_ENCODER1_P0_FLDMASK_LEN 16
2067
2068
#define REG_33B0_DP_ENCODER1_P0 0x33B0
2069
#define TEST_CRC_G_Y_DP_ENCODER1_P0_FLDMASK 0xffff
2070
#define TEST_CRC_G_Y_DP_ENCODER1_P0_FLDMASK_POS 0
2071
#define TEST_CRC_G_Y_DP_ENCODER1_P0_FLDMASK_LEN 16
2072
2073
#define REG_33B4_DP_ENCODER1_P0 0x33B4
2074
#define TEST_CRC_B_CB_DP_ENCODER1_P0_FLDMASK 0xffff
2075
#define TEST_CRC_B_CB_DP_ENCODER1_P0_FLDMASK_POS 0
2076
#define TEST_CRC_B_CB_DP_ENCODER1_P0_FLDMASK_LEN 16
2077
2078
#define REG_33B8_DP_ENCODER1_P0 0x33B8
2079
#define TEST_CRC_WRAP_CNT_DP_ENCODER1_P0_FLDMASK 0xf
2080
#define TEST_CRC_WRAP_CNT_DP_ENCODER1_P0_FLDMASK_POS 0
2081
#define TEST_CRC_WRAP_CNT_DP_ENCODER1_P0_FLDMASK_LEN 4
2082
2083
#define CRC_COLOR_FORMAT_DP_ENCODER1_P0_FLDMASK 0x1f0
2084
#define CRC_COLOR_FORMAT_DP_ENCODER1_P0_FLDMASK_POS 4
2085
#define CRC_COLOR_FORMAT_DP_ENCODER1_P0_FLDMASK_LEN 5
2086
2087
#define CRC_TEST_SINK_START_DP_ENCODER1_P0_FLDMASK 0x200
2088
#define CRC_TEST_SINK_START_DP_ENCODER1_P0_FLDMASK_POS 9
2089
#define CRC_TEST_SINK_START_DP_ENCODER1_P0_FLDMASK_LEN 1
2090
2091
#define REG_33BC_DP_ENCODER1_P0 0x33BC
2092
#define CRC_TEST_CONFIG_DP_ENCODER1_P0_FLDMASK 0x1fff
2093
#define CRC_TEST_CONFIG_DP_ENCODER1_P0_FLDMASK_POS 0
2094
#define CRC_TEST_CONFIG_DP_ENCODER1_P0_FLDMASK_LEN 13
2095
2096
#define REG_33C0_DP_ENCODER1_P0 0x33C0
2097
#define VIDEO_TU_VALUE_DP_ENCODER1_P0_FLDMASK 0x7f
2098
#define VIDEO_TU_VALUE_DP_ENCODER1_P0_FLDMASK_POS 0
2099
#define VIDEO_TU_VALUE_DP_ENCODER1_P0_FLDMASK_LEN 7
2100
2101
#define DP_TX_MIXER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK 0xf00
2102
#define DP_TX_MIXER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_POS 8
2103
#define DP_TX_MIXER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 4
2104
2105
#define DP_TX_SDP_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK 0xf000
2106
#define DP_TX_SDP_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_POS 12
2107
#define DP_TX_SDP_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 4
2108
2109
#define REG_33C4_DP_ENCODER1_P0 0x33C4
2110
#define DP_TX_VIDEO_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK 0x1f
2111
#define DP_TX_VIDEO_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_POS 0
2112
#define DP_TX_VIDEO_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 5
2113
2114
#define DP_TX_ENCODER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK 0x60
2115
#define DP_TX_ENCODER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_POS 5
2116
#define DP_TX_ENCODER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
2117
2118
#define REG_33C8_DP_ENCODER1_P0 0x33C8
2119
#define VIDEO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK 0xffff
2120
#define VIDEO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK_POS 0
2121
#define VIDEO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK_LEN 16
2122
2123
#define REG_33CC_DP_ENCODER1_P0 0x33CC
2124
#define VIDEO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK 0xff
2125
#define VIDEO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK_POS 0
2126
#define VIDEO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK_LEN 8
2127
2128
#define REG_33D0_DP_ENCODER1_P0 0x33D0
2129
#define AUDIO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK 0xffff
2130
#define AUDIO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK_POS 0
2131
#define AUDIO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK_LEN 16
2132
2133
#define REG_33D4_DP_ENCODER1_P0 0x33D4
2134
#define AUDIO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK 0xff
2135
#define AUDIO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK_POS 0
2136
#define AUDIO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK_LEN 8
2137
2138
#define REG_33D8_DP_ENCODER1_P0 0x33D8
2139
#define VSC_EXT_CFG_DP_ENCODER1_P0_FLDMASK 0xff
2140
#define VSC_EXT_CFG_DP_ENCODER1_P0_FLDMASK_POS 0
2141
#define VSC_EXT_CFG_DP_ENCODER1_P0_FLDMASK_LEN 8
2142
2143
#define SDP_SPLIT_FIFO_EMPTY_DP_ENCODER1_P0_FLDMASK 0x100
2144
#define SDP_SPLIT_FIFO_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 8
2145
#define SDP_SPLIT_FIFO_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
2146
2147
#define SDP_SPLIT_FIFO_FULL_DP_ENCODER1_P0_FLDMASK 0x200
2148
#define SDP_SPLIT_FIFO_FULL_DP_ENCODER1_P0_FLDMASK_POS 9
2149
#define SDP_SPLIT_FIFO_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
2150
2151
#define SDP_SPLIT_FIFO_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x400
2152
#define SDP_SPLIT_FIFO_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 10
2153
#define SDP_SPLIT_FIFO_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2154
2155
#define SDP_SPLIT_INSERT_INVALID_CNT_THRD_DP_ENCODER1_P0_FLDMASK 0xf000
2156
#define SDP_SPLIT_INSERT_INVALID_CNT_THRD_DP_ENCODER1_P0_FLDMASK_POS 12
2157
#define SDP_SPLIT_INSERT_INVALID_CNT_THRD_DP_ENCODER1_P0_FLDMASK_LEN 4
2158
2159
#define REG_33DC_DP_ENCODER1_P0 0x33DC
2160
#define VIDEO_SRAM0_FULL_DP_ENCODER1_P0_FLDMASK 0x1
2161
#define VIDEO_SRAM0_FULL_DP_ENCODER1_P0_FLDMASK_POS 0
2162
#define VIDEO_SRAM0_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
2163
2164
#define VIDEO_SRAM0_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x2
2165
#define VIDEO_SRAM0_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 1
2166
#define VIDEO_SRAM0_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2167
2168
#define VIDEO_SRAM1_FULL_DP_ENCODER1_P0_FLDMASK 0x4
2169
#define VIDEO_SRAM1_FULL_DP_ENCODER1_P0_FLDMASK_POS 2
2170
#define VIDEO_SRAM1_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
2171
2172
#define VIDEO_SRAM1_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x8
2173
#define VIDEO_SRAM1_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 3
2174
#define VIDEO_SRAM1_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2175
2176
#define VIDEO_SRAM2_FULL_DP_ENCODER1_P0_FLDMASK 0x10
2177
#define VIDEO_SRAM2_FULL_DP_ENCODER1_P0_FLDMASK_POS 4
2178
#define VIDEO_SRAM2_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
2179
2180
#define VIDEO_SRAM2_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x20
2181
#define VIDEO_SRAM2_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 5
2182
#define VIDEO_SRAM2_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2183
2184
#define VIDEO_SRAM3_FULL_DP_ENCODER1_P0_FLDMASK 0x40
2185
#define VIDEO_SRAM3_FULL_DP_ENCODER1_P0_FLDMASK_POS 6
2186
#define VIDEO_SRAM3_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
2187
2188
#define VIDEO_SRAM3_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x80
2189
#define VIDEO_SRAM3_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 7
2190
#define VIDEO_SRAM3_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2191
2192
#define VIDEO_SRAM0_EMPTY_DP_ENCODER1_P0_FLDMASK 0x100
2193
#define VIDEO_SRAM0_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 8
2194
#define VIDEO_SRAM0_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
2195
2196
#define VIDEO_SRAM0_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK 0x200
2197
#define VIDEO_SRAM0_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_POS 9
2198
#define VIDEO_SRAM0_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2199
2200
#define VIDEO_SRAM1_EMPTY_DP_ENCODER1_P0_FLDMASK 0x400
2201
#define VIDEO_SRAM1_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 10
2202
#define VIDEO_SRAM1_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
2203
2204
#define VIDEO_SRAM1_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK 0x800
2205
#define VIDEO_SRAM1_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_POS 11
2206
#define VIDEO_SRAM1_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2207
2208
#define VIDEO_SRAM2_EMPTY_DP_ENCODER1_P0_FLDMASK 0x1000
2209
#define VIDEO_SRAM2_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 12
2210
#define VIDEO_SRAM2_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
2211
2212
#define VIDEO_SRAM2_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK 0x2000
2213
#define VIDEO_SRAM2_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_POS 13
2214
#define VIDEO_SRAM2_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2215
2216
#define VIDEO_SRAM3_EMPTY_DP_ENCODER1_P0_FLDMASK 0x4000
2217
#define VIDEO_SRAM3_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 14
2218
#define VIDEO_SRAM3_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
2219
2220
#define VIDEO_SRAM3_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK 0x8000
2221
#define VIDEO_SRAM3_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_POS 15
2222
#define VIDEO_SRAM3_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2223
2224
#define REG_33E0_DP_ENCODER1_P0 0x33E0
2225
#define BS2BS_CNT_SW_DP_ENCODER1_P0_FLDMASK 0xffff
2226
#define BS2BS_CNT_SW_DP_ENCODER1_P0_FLDMASK_POS 0
2227
#define BS2BS_CNT_SW_DP_ENCODER1_P0_FLDMASK_LEN 16
2228
2229
#define REG_33E4_DP_ENCODER1_P0 0x33E4
2230
#define MIXER_STATE_0_DP_ENCODER1_P0_FLDMASK 0xffff
2231
#define MIXER_STATE_0_DP_ENCODER1_P0_FLDMASK_POS 0
2232
#define MIXER_STATE_0_DP_ENCODER1_P0_FLDMASK_LEN 16
2233
2234
#define REG_33E8_DP_ENCODER1_P0 0x33E8
2235
#define MIXER_STATE_1_DP_ENCODER1_P0_FLDMASK 0xffff
2236
#define MIXER_STATE_1_DP_ENCODER1_P0_FLDMASK_POS 0
2237
#define MIXER_STATE_1_DP_ENCODER1_P0_FLDMASK_LEN 16
2238
2239
#define REG_33EC_DP_ENCODER1_P0 0x33EC
2240
#define MIXER_STATE_2_DP_ENCODER1_P0_FLDMASK 0xff
2241
#define MIXER_STATE_2_DP_ENCODER1_P0_FLDMASK_POS 0
2242
#define MIXER_STATE_2_DP_ENCODER1_P0_FLDMASK_LEN 8
2243
2244
#define VIDEO_PERIOD_ENABLE_DP_ENCODER1_P0_FLDMASK 0x200
2245
#define VIDEO_PERIOD_ENABLE_DP_ENCODER1_P0_FLDMASK_POS 9
2246
#define VIDEO_PERIOD_ENABLE_DP_ENCODER1_P0_FLDMASK_LEN 1
2247
2248
#define BS2BS_CNT_SW_SEL_DP_ENCODER1_P0_FLDMASK 0x400
2249
#define BS2BS_CNT_SW_SEL_DP_ENCODER1_P0_FLDMASK_POS 10
2250
#define BS2BS_CNT_SW_SEL_DP_ENCODER1_P0_FLDMASK_LEN 1
2251
2252
#define AUDIO_SRAM_FULL_DP_ENCODER1_P0_FLDMASK 0x800
2253
#define AUDIO_SRAM_FULL_DP_ENCODER1_P0_FLDMASK_POS 11
2254
#define AUDIO_SRAM_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
2255
2256
#define AUDIO_SRAM_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x1000
2257
#define AUDIO_SRAM_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 12
2258
#define AUDIO_SRAM_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
2259
2260
#define AUDIO_SRAM_EMPTY_DP_ENCODER1_P0_FLDMASK 0x2000
2261
#define AUDIO_SRAM_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 13
2262
#define AUDIO_SRAM_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
2263
2264
#define REG_33F0_DP_ENCODER1_P0 0x33F0
2265
#define DP_ENCODER_DUMMY_RW_0_DP_ENCODER1_P0_FLDMASK 0xffff
2266
#define DP_ENCODER_DUMMY_RW_0_DP_ENCODER1_P0_FLDMASK_POS 0
2267
#define DP_ENCODER_DUMMY_RW_0_DP_ENCODER1_P0_FLDMASK_LEN 16
2268
2269
#define REG_33F4_DP_ENCODER1_P0 0x33F4
2270
#define DP_ENCODER_DUMMY_RW_1_DP_ENCODER1_P0_FLDMASK 0xffff
2271
#define DP_ENCODER_DUMMY_RW_1_DP_ENCODER1_P0_FLDMASK_POS 0
2272
#define DP_ENCODER_DUMMY_RW_1_DP_ENCODER1_P0_FLDMASK_LEN 16
2273
2274
#define REG_33F8_DP_ENCODER1_P0 0x33F8
2275
#define DP_ENCODER_DUMMY_R_0_DP_ENCODER1_P0_FLDMASK 0xffff
2276
#define DP_ENCODER_DUMMY_R_0_DP_ENCODER1_P0_FLDMASK_POS 0
2277
#define DP_ENCODER_DUMMY_R_0_DP_ENCODER1_P0_FLDMASK_LEN 16
2278
2279
#define REG_33FC_DP_ENCODER1_P0 0x33FC
2280
#define DP_ENCODER_DUMMY_R_1_DP_ENCODER1_P0_FLDMASK 0xffff
2281
#define DP_ENCODER_DUMMY_R_1_DP_ENCODER1_P0_FLDMASK_POS 0
2282
#define DP_ENCODER_DUMMY_R_1_DP_ENCODER1_P0_FLDMASK_LEN 16
2283
2284
#define REG_3400_DP_TRANS_P0 0x3400
2285
#define PRE_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK 0x3
2286
#define PRE_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK_POS 0
2287
#define PRE_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK_LEN 2
2288
2289
#define PRE_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK 0xc
2290
#define PRE_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK_POS 2
2291
#define PRE_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK_LEN 2
2292
2293
#define PRE_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK 0x30
2294
#define PRE_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK_POS 4
2295
#define PRE_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK_LEN 2
2296
2297
#define PRE_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK 0xc0
2298
#define PRE_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK_POS 6
2299
#define PRE_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK_LEN 2
2300
2301
#define PRE_MISC_PORT_MUX_DP_TRANS_P0_FLDMASK 0x700
2302
#define PRE_MISC_PORT_MUX_DP_TRANS_P0_FLDMASK_POS 8
2303
#define PRE_MISC_PORT_MUX_DP_TRANS_P0_FLDMASK_LEN 3
2304
2305
#define HDCP_SEL_DP_TRANS_P0_FLDMASK 0x800
2306
#define HDCP_SEL_DP_TRANS_P0_FLDMASK_POS 11
2307
#define HDCP_SEL_DP_TRANS_P0_FLDMASK_LEN 1
2308
2309
#define PATTERN1_EN_DP_TRANS_P0_FLDMASK 0x1000
2310
#define PATTERN1_EN_DP_TRANS_P0_FLDMASK_POS 12
2311
#define PATTERN1_EN_DP_TRANS_P0_FLDMASK_LEN 1
2312
2313
#define PATTERN2_EN_DP_TRANS_P0_FLDMASK 0x2000
2314
#define PATTERN2_EN_DP_TRANS_P0_FLDMASK_POS 13
2315
#define PATTERN2_EN_DP_TRANS_P0_FLDMASK_LEN 1
2316
2317
#define PATTERN3_EN_DP_TRANS_P0_FLDMASK 0x4000
2318
#define PATTERN3_EN_DP_TRANS_P0_FLDMASK_POS 14
2319
#define PATTERN3_EN_DP_TRANS_P0_FLDMASK_LEN 1
2320
2321
#define PATTERN4_EN_DP_TRANS_P0_FLDMASK 0x8000
2322
#define PATTERN4_EN_DP_TRANS_P0_FLDMASK_POS 15
2323
#define PATTERN4_EN_DP_TRANS_P0_FLDMASK_LEN 1
2324
2325
#define REG_3404_DP_TRANS_P0 0x3404
2326
#define DP_SCR_EN_DP_TRANS_P0_FLDMASK 0x1
2327
#define DP_SCR_EN_DP_TRANS_P0_FLDMASK_POS 0
2328
#define DP_SCR_EN_DP_TRANS_P0_FLDMASK_LEN 1
2329
2330
#define ALTER_SCRAMBLER_RESET_EN_DP_TRANS_P0_FLDMASK 0x2
2331
#define ALTER_SCRAMBLER_RESET_EN_DP_TRANS_P0_FLDMASK_POS 1
2332
#define ALTER_SCRAMBLER_RESET_EN_DP_TRANS_P0_FLDMASK_LEN 1
2333
2334
#define SCRAMB_BYPASS_IN_EN_DP_TRANS_P0_FLDMASK 0x4
2335
#define SCRAMB_BYPASS_IN_EN_DP_TRANS_P0_FLDMASK_POS 2
2336
#define SCRAMB_BYPASS_IN_EN_DP_TRANS_P0_FLDMASK_LEN 1
2337
2338
#define SCRAMB_BYPASS_MASK_DP_TRANS_P0_FLDMASK 0x8
2339
#define SCRAMB_BYPASS_MASK_DP_TRANS_P0_FLDMASK_POS 3
2340
#define SCRAMB_BYPASS_MASK_DP_TRANS_P0_FLDMASK_LEN 1
2341
2342
#define INDEX_SCR_MODE_DP_TRANS_P0_FLDMASK 0x30
2343
#define INDEX_SCR_MODE_DP_TRANS_P0_FLDMASK_POS 4
2344
#define INDEX_SCR_MODE_DP_TRANS_P0_FLDMASK_LEN 2
2345
2346
#define PAT_INIT_DISPARITY_DP_TRANS_P0_FLDMASK 0x40
2347
#define PAT_INIT_DISPARITY_DP_TRANS_P0_FLDMASK_POS 6
2348
#define PAT_INIT_DISPARITY_DP_TRANS_P0_FLDMASK_LEN 1
2349
2350
#define TPS_DISPARITY_RESET_DP_TRANS_P0_FLDMASK 0x80
2351
#define TPS_DISPARITY_RESET_DP_TRANS_P0_FLDMASK_POS 7
2352
#define TPS_DISPARITY_RESET_DP_TRANS_P0_FLDMASK_LEN 1
2353
2354
#define REG_3408_DP_TRANS_P0 0x3408
2355
#define LANE_SKEW_SEL_LANE0_DP_TRANS_P0_FLDMASK 0x3
2356
#define LANE_SKEW_SEL_LANE0_DP_TRANS_P0_FLDMASK_POS 0
2357
#define LANE_SKEW_SEL_LANE0_DP_TRANS_P0_FLDMASK_LEN 2
2358
2359
#define LANE_SKEW_SEL_LANE1_DP_TRANS_P0_FLDMASK 0xc
2360
#define LANE_SKEW_SEL_LANE1_DP_TRANS_P0_FLDMASK_POS 2
2361
#define LANE_SKEW_SEL_LANE1_DP_TRANS_P0_FLDMASK_LEN 2
2362
2363
#define LANE_SKEW_SEL_LANE2_DP_TRANS_P0_FLDMASK 0x30
2364
#define LANE_SKEW_SEL_LANE2_DP_TRANS_P0_FLDMASK_POS 4
2365
#define LANE_SKEW_SEL_LANE2_DP_TRANS_P0_FLDMASK_LEN 2
2366
2367
#define LANE_SKEW_SEL_LANE3_DP_TRANS_P0_FLDMASK 0xc0
2368
#define LANE_SKEW_SEL_LANE3_DP_TRANS_P0_FLDMASK_POS 6
2369
#define LANE_SKEW_SEL_LANE3_DP_TRANS_P0_FLDMASK_LEN 2
2370
2371
#define POST_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK 0x300
2372
#define POST_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK_POS 8
2373
#define POST_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK_LEN 2
2374
2375
#define POST_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK 0xc00
2376
#define POST_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK_POS 10
2377
#define POST_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK_LEN 2
2378
2379
#define POST_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK 0x3000
2380
#define POST_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK_POS 12
2381
#define POST_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK_LEN 2
2382
2383
#define POST_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK 0xc000
2384
#define POST_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK_POS 14
2385
#define POST_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK_LEN 2
2386
2387
#define REG_340C_DP_TRANS_P0 0x340C
2388
#define TOP_RESET_SW_DP_TRANS_P0_FLDMASK 0x100
2389
#define TOP_RESET_SW_DP_TRANS_P0_FLDMASK_POS 8
2390
#define TOP_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
2391
2392
#define LANE0_RESET_SW_DP_TRANS_P0_FLDMASK 0x200
2393
#define LANE0_RESET_SW_DP_TRANS_P0_FLDMASK_POS 9
2394
#define LANE0_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
2395
2396
#define LANE1_RESET_SW_DP_TRANS_P0_FLDMASK 0x400
2397
#define LANE1_RESET_SW_DP_TRANS_P0_FLDMASK_POS 10
2398
#define LANE1_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
2399
2400
#define LANE2_RESET_SW_DP_TRANS_P0_FLDMASK 0x800
2401
#define LANE2_RESET_SW_DP_TRANS_P0_FLDMASK_POS 11
2402
#define LANE2_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
2403
2404
#define LANE3_RESET_SW_DP_TRANS_P0_FLDMASK 0x1000
2405
#define LANE3_RESET_SW_DP_TRANS_P0_FLDMASK_POS 12
2406
#define LANE3_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
2407
2408
#define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_FLDMASK 0x2000
2409
#define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_FLDMASK_POS 13
2410
#define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
2411
2412
#define HDCP13_RST_SW_DP_TRANS_P0_FLDMASK 0x4000
2413
#define HDCP13_RST_SW_DP_TRANS_P0_FLDMASK_POS 14
2414
#define HDCP13_RST_SW_DP_TRANS_P0_FLDMASK_LEN 1
2415
2416
#define HDCP22_RST_SW_DP_TRANS_P0_FLDMASK 0x8000
2417
#define HDCP22_RST_SW_DP_TRANS_P0_FLDMASK_POS 15
2418
#define HDCP22_RST_SW_DP_TRANS_P0_FLDMASK_LEN 1
2419
2420
#define REG_3410_DP_TRANS_P0 0x3410
2421
#define HPD_DEB_THD_DP_TRANS_P0_FLDMASK 0xf
2422
#define HPD_DEB_THD_DP_TRANS_P0_FLDMASK_POS 0
2423
#define HPD_DEB_THD_DP_TRANS_P0_FLDMASK_LEN 4
2424
2425
#define HPD_INT_THD_DP_TRANS_P0_FLDMASK 0xf0
2426
#define HPD_INT_THD_DP_TRANS_P0_FLDMASK_POS 4
2427
#define HPD_INT_THD_DP_TRANS_P0_FLDMASK_LEN 4
2428
2429
#define HPD_DISC_THD_DP_TRANS_P0_FLDMASK 0xf00
2430
#define HPD_DISC_THD_DP_TRANS_P0_FLDMASK_POS 8
2431
#define HPD_DISC_THD_DP_TRANS_P0_FLDMASK_LEN 4
2432
2433
#define HPD_CONN_THD_DP_TRANS_P0_FLDMASK 0xf000
2434
#define HPD_CONN_THD_DP_TRANS_P0_FLDMASK_POS 12
2435
#define HPD_CONN_THD_DP_TRANS_P0_FLDMASK_LEN 4
2436
2437
#define REG_3414_DP_TRANS_P0 0x3414
2438
#define HPD_OVR_EN_DP_TRANS_P0_FLDMASK 0x1
2439
#define HPD_OVR_EN_DP_TRANS_P0_FLDMASK_POS 0
2440
#define HPD_OVR_EN_DP_TRANS_P0_FLDMASK_LEN 1
2441
2442
#define HPD_SET_DP_TRANS_P0_FLDMASK 0x2
2443
#define HPD_SET_DP_TRANS_P0_FLDMASK_POS 1
2444
#define HPD_SET_DP_TRANS_P0_FLDMASK_LEN 1
2445
2446
#define HPD_DB_DP_TRANS_P0_FLDMASK 0x4
2447
#define HPD_DB_DP_TRANS_P0_FLDMASK_POS 2
2448
#define HPD_DB_DP_TRANS_P0_FLDMASK_LEN 1
2449
2450
#define REG_3418_DP_TRANS_P0 0x3418
2451
#define IRQ_CLR_DP_TRANS_P0_FLDMASK 0xf
2452
#define IRQ_CLR_DP_TRANS_P0_FLDMASK_POS 0
2453
#define IRQ_CLR_DP_TRANS_P0_FLDMASK_LEN 4
2454
2455
#define IRQ_MASK_DP_TRANS_P0_FLDMASK 0xf0
2456
#define IRQ_MASK_DP_TRANS_P0_FLDMASK_POS 4
2457
#define IRQ_MASK_DP_TRANS_P0_FLDMASK_LEN 4
2458
2459
#define IRQ_FORCE_DP_TRANS_P0_FLDMASK 0xf00
2460
#define IRQ_FORCE_DP_TRANS_P0_FLDMASK_POS 8
2461
#define IRQ_FORCE_DP_TRANS_P0_FLDMASK_LEN 4
2462
2463
#define IRQ_STATUS_DP_TRANS_P0_FLDMASK 0xf000
2464
#define IRQ_STATUS_DP_TRANS_P0_FLDMASK_POS 12
2465
#define IRQ_STATUS_DP_TRANS_P0_FLDMASK_LEN 4
2466
2467
#define REG_341C_DP_TRANS_P0 0x341C
2468
#define IRQ_CLR_51_DP_TRANS_P0_FLDMASK 0xf
2469
#define IRQ_CLR_51_DP_TRANS_P0_FLDMASK_POS 0
2470
#define IRQ_CLR_51_DP_TRANS_P0_FLDMASK_LEN 4
2471
2472
#define IRQ_MASK_51_DP_TRANS_P0_FLDMASK 0xf0
2473
#define IRQ_MASK_51_DP_TRANS_P0_FLDMASK_POS 4
2474
#define IRQ_MASK_51_DP_TRANS_P0_FLDMASK_LEN 4
2475
2476
#define IRQ_FORCE_51_DP_TRANS_P0_FLDMASK 0xf00
2477
#define IRQ_FORCE_51_DP_TRANS_P0_FLDMASK_POS 8
2478
#define IRQ_FORCE_51_DP_TRANS_P0_FLDMASK_LEN 4
2479
2480
#define IRQ_STATUS_51_DP_TRANS_P0_FLDMASK 0xf000
2481
#define IRQ_STATUS_51_DP_TRANS_P0_FLDMASK_POS 12
2482
#define IRQ_STATUS_51_DP_TRANS_P0_FLDMASK_LEN 4
2483
2484
#define REG_3420_DP_TRANS_P0 0x3420
2485
#define HPD_STATUS_DP_TRANS_P0_FLDMASK 0x1
2486
#define HPD_STATUS_DP_TRANS_P0_FLDMASK_POS 0
2487
#define HPD_STATUS_DP_TRANS_P0_FLDMASK_LEN 1
2488
2489
#define REG_3428_DP_TRANS_P0 0x3428
2490
#define POST_MISC_BIT_REVERSE_EN_LANE0_DP_TRANS_P0_FLDMASK 0x1
2491
#define POST_MISC_BIT_REVERSE_EN_LANE0_DP_TRANS_P0_FLDMASK_POS 0
2492
#define POST_MISC_BIT_REVERSE_EN_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
2493
2494
#define POST_MISC_BIT_REVERSE_EN_LANE1_DP_TRANS_P0_FLDMASK 0x2
2495
#define POST_MISC_BIT_REVERSE_EN_LANE1_DP_TRANS_P0_FLDMASK_POS 1
2496
#define POST_MISC_BIT_REVERSE_EN_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
2497
2498
#define POST_MISC_BIT_REVERSE_EN_LANE2_DP_TRANS_P0_FLDMASK 0x4
2499
#define POST_MISC_BIT_REVERSE_EN_LANE2_DP_TRANS_P0_FLDMASK_POS 2
2500
#define POST_MISC_BIT_REVERSE_EN_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
2501
2502
#define POST_MISC_BIT_REVERSE_EN_LANE3_DP_TRANS_P0_FLDMASK 0x8
2503
#define POST_MISC_BIT_REVERSE_EN_LANE3_DP_TRANS_P0_FLDMASK_POS 3
2504
#define POST_MISC_BIT_REVERSE_EN_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
2505
2506
#define POST_MISC_PN_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK 0x10
2507
#define POST_MISC_PN_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK_POS 4
2508
#define POST_MISC_PN_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
2509
2510
#define POST_MISC_PN_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK 0x20
2511
#define POST_MISC_PN_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK_POS 5
2512
#define POST_MISC_PN_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
2513
2514
#define POST_MISC_PN_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK 0x40
2515
#define POST_MISC_PN_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK_POS 6
2516
#define POST_MISC_PN_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
2517
2518
#define POST_MISC_PN_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK 0x80
2519
#define POST_MISC_PN_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK_POS 7
2520
#define POST_MISC_PN_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
2521
2522
#define POST_MISC_DATA_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK 0x100
2523
#define POST_MISC_DATA_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK_POS 8
2524
#define POST_MISC_DATA_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
2525
2526
#define POST_MISC_DATA_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK 0x200
2527
#define POST_MISC_DATA_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK_POS 9
2528
#define POST_MISC_DATA_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
2529
2530
#define POST_MISC_DATA_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK 0x400
2531
#define POST_MISC_DATA_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK_POS 10
2532
#define POST_MISC_DATA_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
2533
2534
#define POST_MISC_DATA_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK 0x800
2535
#define POST_MISC_DATA_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK_POS 11
2536
#define POST_MISC_DATA_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
2537
2538
#define REG_342C_DP_TRANS_P0 0x342C
2539
#define XTAL_FREQ_DP_TRANS_P0_FLDMASK 0xff
2540
#define XTAL_FREQ_DP_TRANS_P0_FLDMASK_POS 0
2541
#define XTAL_FREQ_DP_TRANS_P0_FLDMASK_LEN 8
2542
2543
#define REG_3430_DP_TRANS_P0 0x3430
2544
#define HPD_INT_THD_ECO_DP_TRANS_P0_FLDMASK 0x3
2545
#define HPD_INT_THD_ECO_DP_TRANS_P0_FLDMASK_POS 0
2546
#define HPD_INT_THD_ECO_DP_TRANS_P0_FLDMASK_LEN 2
2547
2548
#define REG_3440_DP_TRANS_P0 0x3440
2549
#define PGM_PAT_EN_DP_TRANS_P0_FLDMASK 0xf
2550
#define PGM_PAT_EN_DP_TRANS_P0_FLDMASK_POS 0
2551
#define PGM_PAT_EN_DP_TRANS_P0_FLDMASK_LEN 4
2552
2553
#define PGM_PAT_SEL_L0_DP_TRANS_P0_FLDMASK 0x70
2554
#define PGM_PAT_SEL_L0_DP_TRANS_P0_FLDMASK_POS 4
2555
#define PGM_PAT_SEL_L0_DP_TRANS_P0_FLDMASK_LEN 3
2556
2557
#define PGM_PAT_SEL_L1_DP_TRANS_P0_FLDMASK 0x700
2558
#define PGM_PAT_SEL_L1_DP_TRANS_P0_FLDMASK_POS 8
2559
#define PGM_PAT_SEL_L1_DP_TRANS_P0_FLDMASK_LEN 3
2560
2561
#define PGM_PAT_SEL_L2_DP_TRANS_P0_FLDMASK 0x7000
2562
#define PGM_PAT_SEL_L2_DP_TRANS_P0_FLDMASK_POS 12
2563
#define PGM_PAT_SEL_L2_DP_TRANS_P0_FLDMASK_LEN 3
2564
2565
#define REG_3444_DP_TRANS_P0 0x3444
2566
#define PGM_PAT_SEL_L3_DP_TRANS_P0_FLDMASK 0x7
2567
#define PGM_PAT_SEL_L3_DP_TRANS_P0_FLDMASK_POS 0
2568
#define PGM_PAT_SEL_L3_DP_TRANS_P0_FLDMASK_LEN 3
2569
2570
#define PRBS_EN_DP_TRANS_P0_FLDMASK 0x8
2571
#define PRBS_EN_DP_TRANS_P0_FLDMASK_POS 3
2572
#define PRBS_EN_DP_TRANS_P0_FLDMASK_LEN 1
2573
2574
#define REG_3448_DP_TRANS_P0 0x3448
2575
#define PGM_PAT_L0_0_DP_TRANS_P0_FLDMASK 0xffff
2576
#define PGM_PAT_L0_0_DP_TRANS_P0_FLDMASK_POS 0
2577
#define PGM_PAT_L0_0_DP_TRANS_P0_FLDMASK_LEN 16
2578
2579
#define REG_344C_DP_TRANS_P0 0x344C
2580
#define PGM_PAT_L0_1_DP_TRANS_P0_FLDMASK 0xffff
2581
#define PGM_PAT_L0_1_DP_TRANS_P0_FLDMASK_POS 0
2582
#define PGM_PAT_L0_1_DP_TRANS_P0_FLDMASK_LEN 16
2583
2584
#define REG_3450_DP_TRANS_P0 0x3450
2585
#define PGM_PAT_L0_2_DP_TRANS_P0_FLDMASK 0xff
2586
#define PGM_PAT_L0_2_DP_TRANS_P0_FLDMASK_POS 0
2587
#define PGM_PAT_L0_2_DP_TRANS_P0_FLDMASK_LEN 8
2588
2589
#define REG_3454_DP_TRANS_P0 0x3454
2590
#define PGM_PAT_L1_0_DP_TRANS_P0_FLDMASK 0xffff
2591
#define PGM_PAT_L1_0_DP_TRANS_P0_FLDMASK_POS 0
2592
#define PGM_PAT_L1_0_DP_TRANS_P0_FLDMASK_LEN 16
2593
2594
#define REG_3458_DP_TRANS_P0 0x3458
2595
#define PGM_PAT_L1_1_DP_TRANS_P0_FLDMASK 0xffff
2596
#define PGM_PAT_L1_1_DP_TRANS_P0_FLDMASK_POS 0
2597
#define PGM_PAT_L1_1_DP_TRANS_P0_FLDMASK_LEN 16
2598
2599
#define REG_345C_DP_TRANS_P0 0x345C
2600
#define PGM_PAT_L1_2_DP_TRANS_P0_FLDMASK 0xff
2601
#define PGM_PAT_L1_2_DP_TRANS_P0_FLDMASK_POS 0
2602
#define PGM_PAT_L1_2_DP_TRANS_P0_FLDMASK_LEN 8
2603
2604
#define REG_3460_DP_TRANS_P0 0x3460
2605
#define PGM_PAT_L2_0_DP_TRANS_P0_FLDMASK 0xffff
2606
#define PGM_PAT_L2_0_DP_TRANS_P0_FLDMASK_POS 0
2607
#define PGM_PAT_L2_0_DP_TRANS_P0_FLDMASK_LEN 16
2608
2609
#define REG_3464_DP_TRANS_P0 0x3464
2610
#define PGM_PAT_L2_1_DP_TRANS_P0_FLDMASK 0xffff
2611
#define PGM_PAT_L2_1_DP_TRANS_P0_FLDMASK_POS 0
2612
#define PGM_PAT_L2_1_DP_TRANS_P0_FLDMASK_LEN 16
2613
2614
#define REG_3468_DP_TRANS_P0 0x3468
2615
#define PGM_PAT_L2_2_DP_TRANS_P0_FLDMASK 0xff
2616
#define PGM_PAT_L2_2_DP_TRANS_P0_FLDMASK_POS 0
2617
#define PGM_PAT_L2_2_DP_TRANS_P0_FLDMASK_LEN 8
2618
2619
#define REG_346C_DP_TRANS_P0 0x346C
2620
#define PGM_PAT_L3_0_DP_TRANS_P0_FLDMASK 0xffff
2621
#define PGM_PAT_L3_0_DP_TRANS_P0_FLDMASK_POS 0
2622
#define PGM_PAT_L3_0_DP_TRANS_P0_FLDMASK_LEN 16
2623
2624
#define REG_3470_DP_TRANS_P0 0x3470
2625
#define PGM_PAT_L3_1_DP_TRANS_P0_FLDMASK 0xffff
2626
#define PGM_PAT_L3_1_DP_TRANS_P0_FLDMASK_POS 0
2627
#define PGM_PAT_L3_1_DP_TRANS_P0_FLDMASK_LEN 16
2628
2629
#define REG_3474_DP_TRANS_P0 0x3474
2630
#define PGM_PAT_L3_2_DP_TRANS_P0_FLDMASK 0xff
2631
#define PGM_PAT_L3_2_DP_TRANS_P0_FLDMASK_POS 0
2632
#define PGM_PAT_L3_2_DP_TRANS_P0_FLDMASK_LEN 8
2633
2634
#define REG_3478_DP_TRANS_P0 0x3478
2635
#define CP2520_PATTERN1_DP_TRANS_P0_FLDMASK 0x1
2636
#define CP2520_PATTERN1_DP_TRANS_P0_FLDMASK_POS 0
2637
#define CP2520_PATTERN1_DP_TRANS_P0_FLDMASK_LEN 1
2638
2639
#define CP2520_PATTERN2_DP_TRANS_P0_FLDMASK 0x2
2640
#define CP2520_PATTERN2_DP_TRANS_P0_FLDMASK_POS 1
2641
#define CP2520_PATTERN2_DP_TRANS_P0_FLDMASK_LEN 1
2642
2643
#define CP2520_PATTERN1_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x10
2644
#define CP2520_PATTERN1_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 4
2645
#define CP2520_PATTERN1_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
2646
2647
#define CP2520_PATTERN1_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x20
2648
#define CP2520_PATTERN1_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 5
2649
#define CP2520_PATTERN1_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
2650
2651
#define CP2520_PATTERN1_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x40
2652
#define CP2520_PATTERN1_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 6
2653
#define CP2520_PATTERN1_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
2654
2655
#define CP2520_PATTERN1_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x80
2656
#define CP2520_PATTERN1_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 7
2657
#define CP2520_PATTERN1_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
2658
2659
#define CP2520_PATTERN1_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x100
2660
#define CP2520_PATTERN1_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 8
2661
#define CP2520_PATTERN1_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
2662
2663
#define CP2520_PATTERN1_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x200
2664
#define CP2520_PATTERN1_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 9
2665
#define CP2520_PATTERN1_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
2666
2667
#define CP2520_PATTERN1_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x400
2668
#define CP2520_PATTERN1_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 10
2669
#define CP2520_PATTERN1_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
2670
2671
#define CP2520_PATTERN1_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x800
2672
#define CP2520_PATTERN1_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 11
2673
#define CP2520_PATTERN1_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
2674
2675
#define REG_347C_DP_TRANS_P0 0x347C
2676
#define CP2520_PATTERN2_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x1
2677
#define CP2520_PATTERN2_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 0
2678
#define CP2520_PATTERN2_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
2679
2680
#define CP2520_PATTERN2_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x2
2681
#define CP2520_PATTERN2_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 1
2682
#define CP2520_PATTERN2_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
2683
2684
#define CP2520_PATTERN2_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x4
2685
#define CP2520_PATTERN2_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 2
2686
#define CP2520_PATTERN2_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
2687
2688
#define CP2520_PATTERN2_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x8
2689
#define CP2520_PATTERN2_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 3
2690
#define CP2520_PATTERN2_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
2691
2692
#define CP2520_PATTERN2_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x10
2693
#define CP2520_PATTERN2_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 4
2694
#define CP2520_PATTERN2_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
2695
2696
#define CP2520_PATTERN2_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x20
2697
#define CP2520_PATTERN2_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 5
2698
#define CP2520_PATTERN2_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
2699
2700
#define CP2520_PATTERN2_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x40
2701
#define CP2520_PATTERN2_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 6
2702
#define CP2520_PATTERN2_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
2703
2704
#define CP2520_PATTERN2_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x80
2705
#define CP2520_PATTERN2_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 7
2706
#define CP2520_PATTERN2_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
2707
2708
#define CP2520_PATTERN3_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x100
2709
#define CP2520_PATTERN3_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 8
2710
#define CP2520_PATTERN3_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
2711
2712
#define CP2520_PATTERN3_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x200
2713
#define CP2520_PATTERN3_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 9
2714
#define CP2520_PATTERN3_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
2715
2716
#define CP2520_PATTERN3_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x400
2717
#define CP2520_PATTERN3_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 10
2718
#define CP2520_PATTERN3_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
2719
2720
#define CP2520_PATTERN3_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x800
2721
#define CP2520_PATTERN3_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 11
2722
#define CP2520_PATTERN3_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
2723
2724
#define CP2520_PATTERN3_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x1000
2725
#define CP2520_PATTERN3_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 12
2726
#define CP2520_PATTERN3_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
2727
2728
#define CP2520_PATTERN3_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x2000
2729
#define CP2520_PATTERN3_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 13
2730
#define CP2520_PATTERN3_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
2731
2732
#define CP2520_PATTERN3_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x4000
2733
#define CP2520_PATTERN3_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 14
2734
#define CP2520_PATTERN3_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
2735
2736
#define CP2520_PATTERN3_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x8000
2737
#define CP2520_PATTERN3_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 15
2738
#define CP2520_PATTERN3_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
2739
2740
#define REG_3480_DP_TRANS_P0 0x3480
2741
#define DP_EN_DP_TRANS_P0_FLDMASK 0x1
2742
#define DP_EN_DP_TRANS_P0_FLDMASK_POS 0
2743
#define DP_EN_DP_TRANS_P0_FLDMASK_LEN 1
2744
2745
#define HDCP_CAPABLE_DP_TRANS_P0_FLDMASK 0x2
2746
#define HDCP_CAPABLE_DP_TRANS_P0_FLDMASK_POS 1
2747
#define HDCP_CAPABLE_DP_TRANS_P0_FLDMASK_LEN 1
2748
2749
#define SELECT_INTERNAL_AN_DP_TRANS_P0_FLDMASK 0x4
2750
#define SELECT_INTERNAL_AN_DP_TRANS_P0_FLDMASK_POS 2
2751
#define SELECT_INTERNAL_AN_DP_TRANS_P0_FLDMASK_LEN 1
2752
2753
#define AN_FREERUN_DP_TRANS_P0_FLDMASK 0x8
2754
#define AN_FREERUN_DP_TRANS_P0_FLDMASK_POS 3
2755
#define AN_FREERUN_DP_TRANS_P0_FLDMASK_LEN 1
2756
2757
#define KM_GENERATED_DP_TRANS_P0_FLDMASK 0x10
2758
#define KM_GENERATED_DP_TRANS_P0_FLDMASK_POS 4
2759
#define KM_GENERATED_DP_TRANS_P0_FLDMASK_LEN 1
2760
2761
#define REQ_BLOCK_CIPHER_AUTH_DP_TRANS_P0_FLDMASK 0x1000
2762
#define REQ_BLOCK_CIPHER_AUTH_DP_TRANS_P0_FLDMASK_POS 12
2763
#define REQ_BLOCK_CIPHER_AUTH_DP_TRANS_P0_FLDMASK_LEN 1
2764
2765
#define HDCP_1LANE_SEL_DP_TRANS_P0_FLDMASK 0x2000
2766
#define HDCP_1LANE_SEL_DP_TRANS_P0_FLDMASK_POS 13
2767
#define HDCP_1LANE_SEL_DP_TRANS_P0_FLDMASK_LEN 1
2768
2769
#define HDCP_24LANE_SEL_DP_TRANS_P0_FLDMASK 0x4000
2770
#define HDCP_24LANE_SEL_DP_TRANS_P0_FLDMASK_POS 14
2771
#define HDCP_24LANE_SEL_DP_TRANS_P0_FLDMASK_LEN 1
2772
2773
#define MST_EN_DP_TRANS_P0_FLDMASK 0x8000
2774
#define MST_EN_DP_TRANS_P0_FLDMASK_POS 15
2775
#define MST_EN_DP_TRANS_P0_FLDMASK_LEN 1
2776
2777
#define REG_34A4_DP_TRANS_P0 0x34A4
2778
#define EN_COPY_2LANE_MSA_DP_TRANS_P0_FLDMASK 0x1
2779
#define EN_COPY_2LANE_MSA_DP_TRANS_P0_FLDMASK_POS 0
2780
#define EN_COPY_2LANE_MSA_DP_TRANS_P0_FLDMASK_LEN 1
2781
2782
#define EN_COPY_4LANE_MSA_DP_TRANS_P0_FLDMASK 0x2
2783
#define EN_COPY_4LANE_MSA_DP_TRANS_P0_FLDMASK_POS 1
2784
#define EN_COPY_4LANE_MSA_DP_TRANS_P0_FLDMASK_LEN 1
2785
2786
#define LANE_NUM_DP_TRANS_P0_FLDMASK 0xc
2787
#define LANE_NUM_DP_TRANS_P0_FLDMASK_POS 2
2788
#define LANE_NUM_DP_TRANS_P0_FLDMASK_LEN 2
2789
2790
#define HDCP22_AUTH_DONE_DP_TRANS_P0_FLDMASK 0x10
2791
#define HDCP22_AUTH_DONE_DP_TRANS_P0_FLDMASK_POS 4
2792
#define HDCP22_AUTH_DONE_DP_TRANS_P0_FLDMASK_LEN 1
2793
2794
#define DISCARD_UNUSED_CIPHER_DP_TRANS_P0_FLDMASK 0x20
2795
#define DISCARD_UNUSED_CIPHER_DP_TRANS_P0_FLDMASK_POS 5
2796
#define DISCARD_UNUSED_CIPHER_DP_TRANS_P0_FLDMASK_LEN 1
2797
2798
#define HDCP22_CIPHER_REVERSE_DP_TRANS_P0_FLDMASK 0x40
2799
#define HDCP22_CIPHER_REVERSE_DP_TRANS_P0_FLDMASK_POS 6
2800
#define HDCP22_CIPHER_REVERSE_DP_TRANS_P0_FLDMASK_LEN 1
2801
2802
#define MST_DELAY_CYCLE_FLAG_SEL_DP_TRANS_P0_FLDMASK 0x80
2803
#define MST_DELAY_CYCLE_FLAG_SEL_DP_TRANS_P0_FLDMASK_POS 7
2804
#define MST_DELAY_CYCLE_FLAG_SEL_DP_TRANS_P0_FLDMASK_LEN 1
2805
2806
#define TEST_CONFIG_HDCP22_DP_TRANS_P0_FLDMASK 0xf00
2807
#define TEST_CONFIG_HDCP22_DP_TRANS_P0_FLDMASK_POS 8
2808
#define TEST_CONFIG_HDCP22_DP_TRANS_P0_FLDMASK_LEN 4
2809
2810
#define R0_AVAILABLE_DP_TRANS_P0_FLDMASK 0x1000
2811
#define R0_AVAILABLE_DP_TRANS_P0_FLDMASK_POS 12
2812
#define R0_AVAILABLE_DP_TRANS_P0_FLDMASK_LEN 1
2813
2814
#define DPES_TX_HDCP22_DP_TRANS_P0_FLDMASK 0x2000
2815
#define DPES_TX_HDCP22_DP_TRANS_P0_FLDMASK_POS 13
2816
#define DPES_TX_HDCP22_DP_TRANS_P0_FLDMASK_LEN 1
2817
2818
#define DP_AES_OUT_RDY_L_DP_TRANS_P0_FLDMASK 0x4000
2819
#define DP_AES_OUT_RDY_L_DP_TRANS_P0_FLDMASK_POS 14
2820
#define DP_AES_OUT_RDY_L_DP_TRANS_P0_FLDMASK_LEN 1
2821
2822
#define REPEATER_I_DP_TRANS_P0_FLDMASK 0x8000
2823
#define REPEATER_I_DP_TRANS_P0_FLDMASK_POS 15
2824
#define REPEATER_I_DP_TRANS_P0_FLDMASK_LEN 1
2825
2826
#define REG_34A8_DP_TRANS_P0 0x34A8
2827
#define TEST_CONFIG_HDCP13_DP_TRANS_P0_FLDMASK 0xff00
2828
#define TEST_CONFIG_HDCP13_DP_TRANS_P0_FLDMASK_POS 8
2829
#define TEST_CONFIG_HDCP13_DP_TRANS_P0_FLDMASK_LEN 8
2830
2831
#define REG_34D0_DP_TRANS_P0 0x34D0
2832
#define TX_HDCP22_TYPE_DP_TRANS_P0_FLDMASK 0xff
2833
#define TX_HDCP22_TYPE_DP_TRANS_P0_FLDMASK_POS 0
2834
#define TX_HDCP22_TYPE_DP_TRANS_P0_FLDMASK_LEN 8
2835
2836
#define PIPE_DELAY_EN_CNT_DP_TRANS_P0_FLDMASK 0xf00
2837
#define PIPE_DELAY_EN_CNT_DP_TRANS_P0_FLDMASK_POS 8
2838
#define PIPE_DELAY_EN_CNT_DP_TRANS_P0_FLDMASK_LEN 4
2839
2840
#define PIPE_DELAY_DP_TRANS_P0_FLDMASK 0xf000
2841
#define PIPE_DELAY_DP_TRANS_P0_FLDMASK_POS 12
2842
#define PIPE_DELAY_DP_TRANS_P0_FLDMASK_LEN 4
2843
2844
#define REG_34D4_DP_TRANS_P0 0x34D4
2845
#define DP_AES_INCTR_L_0_DP_TRANS_P0_FLDMASK 0xffff
2846
#define DP_AES_INCTR_L_0_DP_TRANS_P0_FLDMASK_POS 0
2847
#define DP_AES_INCTR_L_0_DP_TRANS_P0_FLDMASK_LEN 16
2848
2849
#define REG_34D8_DP_TRANS_P0 0x34D8
2850
#define DP_AES_INCTR_L_1_DP_TRANS_P0_FLDMASK 0xffff
2851
#define DP_AES_INCTR_L_1_DP_TRANS_P0_FLDMASK_POS 0
2852
#define DP_AES_INCTR_L_1_DP_TRANS_P0_FLDMASK_LEN 16
2853
2854
#define REG_34DC_DP_TRANS_P0 0x34DC
2855
#define DP_AES_INCTR_L_2_DP_TRANS_P0_FLDMASK 0xffff
2856
#define DP_AES_INCTR_L_2_DP_TRANS_P0_FLDMASK_POS 0
2857
#define DP_AES_INCTR_L_2_DP_TRANS_P0_FLDMASK_LEN 16
2858
2859
#define REG_34E0_DP_TRANS_P0 0x34E0
2860
#define DP_AES_INCTR_L_3_DP_TRANS_P0_FLDMASK 0xffff
2861
#define DP_AES_INCTR_L_3_DP_TRANS_P0_FLDMASK_POS 0
2862
#define DP_AES_INCTR_L_3_DP_TRANS_P0_FLDMASK_LEN 16
2863
2864
#define REG_34E4_DP_TRANS_P0 0x34E4
2865
#define HDCP_TYPE_TX_0_DP_TRANS_P0_FLDMASK 0xffff
2866
#define HDCP_TYPE_TX_0_DP_TRANS_P0_FLDMASK_POS 0
2867
#define HDCP_TYPE_TX_0_DP_TRANS_P0_FLDMASK_LEN 16
2868
2869
#define REG_34E8_DP_TRANS_P0 0x34E8
2870
#define HDCP_TYPE_TX_1_DP_TRANS_P0_FLDMASK 0xffff
2871
#define HDCP_TYPE_TX_1_DP_TRANS_P0_FLDMASK_POS 0
2872
#define HDCP_TYPE_TX_1_DP_TRANS_P0_FLDMASK_LEN 16
2873
2874
#define REG_34EC_DP_TRANS_P0 0x34EC
2875
#define HDCP_TYPE_TX_2_DP_TRANS_P0_FLDMASK 0xffff
2876
#define HDCP_TYPE_TX_2_DP_TRANS_P0_FLDMASK_POS 0
2877
#define HDCP_TYPE_TX_2_DP_TRANS_P0_FLDMASK_LEN 16
2878
2879
#define REG_34F0_DP_TRANS_P0 0x34F0
2880
#define HDCP_TYPE_TX_3_DP_TRANS_P0_FLDMASK 0xffff
2881
#define HDCP_TYPE_TX_3_DP_TRANS_P0_FLDMASK_POS 0
2882
#define HDCP_TYPE_TX_3_DP_TRANS_P0_FLDMASK_LEN 16
2883
2884
#define REG_34F4_DP_TRANS_P0 0x34F4
2885
#define SST_HDCP_TYPE_TX_DP_TRANS_P0_FLDMASK 0xff
2886
#define SST_HDCP_TYPE_TX_DP_TRANS_P0_FLDMASK_POS 0
2887
#define SST_HDCP_TYPE_TX_DP_TRANS_P0_FLDMASK_LEN 8
2888
2889
#define PIPE_OV_VALUE_DP_TRANS_P0_FLDMASK 0xf00
2890
#define PIPE_OV_VALUE_DP_TRANS_P0_FLDMASK_POS 8
2891
#define PIPE_OV_VALUE_DP_TRANS_P0_FLDMASK_LEN 4
2892
2893
#define PIPE_OV_ENABLE_DP_TRANS_P0_FLDMASK 0x1000
2894
#define PIPE_OV_ENABLE_DP_TRANS_P0_FLDMASK_POS 12
2895
#define PIPE_OV_ENABLE_DP_TRANS_P0_FLDMASK_LEN 1
2896
2897
#define REG_34F8_DP_TRANS_P0 0x34F8
2898
#define DP_AES_OUT_RDY_H_DP_TRANS_P0_FLDMASK 0x4000
2899
#define DP_AES_OUT_RDY_H_DP_TRANS_P0_FLDMASK_POS 14
2900
#define DP_AES_OUT_RDY_H_DP_TRANS_P0_FLDMASK_LEN 1
2901
2902
#define REG_34FC_DP_TRANS_P0 0x34FC
2903
#define HDCP_4P_TO_2P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK 0xff
2904
#define HDCP_4P_TO_2P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK_POS 0
2905
#define HDCP_4P_TO_2P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK_LEN 8
2906
2907
#define HDCP_2P_TO_4P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK 0xff00
2908
#define HDCP_2P_TO_4P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK_POS 8
2909
#define HDCP_2P_TO_4P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK_LEN 8
2910
2911
#define REG_3500_DP_TRANS_P0 0x3500
2912
#define DP_AES_INCTR_H_0_DP_TRANS_P0_FLDMASK 0xffff
2913
#define DP_AES_INCTR_H_0_DP_TRANS_P0_FLDMASK_POS 0
2914
#define DP_AES_INCTR_H_0_DP_TRANS_P0_FLDMASK_LEN 16
2915
2916
#define REG_3504_DP_TRANS_P0 0x3504
2917
#define DP_AES_INCTR_H_1_DP_TRANS_P0_FLDMASK 0xffff
2918
#define DP_AES_INCTR_H_1_DP_TRANS_P0_FLDMASK_POS 0
2919
#define DP_AES_INCTR_H_1_DP_TRANS_P0_FLDMASK_LEN 16
2920
2921
#define REG_3508_DP_TRANS_P0 0x3508
2922
#define DP_AES_INCTR_H_2_DP_TRANS_P0_FLDMASK 0xffff
2923
#define DP_AES_INCTR_H_2_DP_TRANS_P0_FLDMASK_POS 0
2924
#define DP_AES_INCTR_H_2_DP_TRANS_P0_FLDMASK_LEN 16
2925
2926
#define REG_350C_DP_TRANS_P0 0x350C
2927
#define DP_AES_INCTR_H_3_DP_TRANS_P0_FLDMASK 0xffff
2928
#define DP_AES_INCTR_H_3_DP_TRANS_P0_FLDMASK_POS 0
2929
#define DP_AES_INCTR_H_3_DP_TRANS_P0_FLDMASK_LEN 16
2930
2931
#define REG_3510_DP_TRANS_P0 0x3510
2932
#define HDCP22_TYPE_DP_TRANS_P0_FLDMASK 0xff
2933
#define HDCP22_TYPE_DP_TRANS_P0_FLDMASK_POS 0
2934
#define HDCP22_TYPE_DP_TRANS_P0_FLDMASK_LEN 8
2935
2936
#define REG_3540_DP_TRANS_P0 0x3540
2937
#define FEC_EN_DP_TRANS_P0_FLDMASK 0x1
2938
#define FEC_EN_DP_TRANS_P0_FLDMASK_POS 0
2939
#define FEC_EN_DP_TRANS_P0_FLDMASK_LEN 1
2940
2941
#define FEC_END_MODE_DP_TRANS_P0_FLDMASK 0x6
2942
#define FEC_END_MODE_DP_TRANS_P0_FLDMASK_POS 1
2943
#define FEC_END_MODE_DP_TRANS_P0_FLDMASK_LEN 2
2944
2945
#define FEC_CLOCK_EN_MODE_DP_TRANS_P0_FLDMASK 0x8
2946
#define FEC_CLOCK_EN_MODE_DP_TRANS_P0_FLDMASK_POS 3
2947
#define FEC_CLOCK_EN_MODE_DP_TRANS_P0_FLDMASK_LEN 1
2948
2949
#define FEC_FIFO_READ_START_DP_TRANS_P0_FLDMASK 0xf0
2950
#define FEC_FIFO_READ_START_DP_TRANS_P0_FLDMASK_POS 4
2951
#define FEC_FIFO_READ_START_DP_TRANS_P0_FLDMASK_LEN 4
2952
2953
#define FEC_FIFO_UNDER_POINT_DP_TRANS_P0_FLDMASK 0xf00
2954
#define FEC_FIFO_UNDER_POINT_DP_TRANS_P0_FLDMASK_POS 8
2955
#define FEC_FIFO_UNDER_POINT_DP_TRANS_P0_FLDMASK_LEN 4
2956
2957
#define FEC_FIFO_OVER_POINT_DP_TRANS_P0_FLDMASK 0xf000
2958
#define FEC_FIFO_OVER_POINT_DP_TRANS_P0_FLDMASK_POS 12
2959
#define FEC_FIFO_OVER_POINT_DP_TRANS_P0_FLDMASK_LEN 4
2960
2961
#define REG_3544_DP_TRANS_P0 0x3544
2962
#define FEC_FIFO_RST_DP_TRANS_P0_FLDMASK 0x1
2963
#define FEC_FIFO_RST_DP_TRANS_P0_FLDMASK_POS 0
2964
#define FEC_FIFO_RST_DP_TRANS_P0_FLDMASK_LEN 1
2965
2966
#define FEC_SUPPORT_DP_TRANS_P0_FLDMASK 0x2
2967
#define FEC_SUPPORT_DP_TRANS_P0_FLDMASK_POS 1
2968
#define FEC_SUPPORT_DP_TRANS_P0_FLDMASK_LEN 1
2969
2970
#define FEC_PATTERN_NEW_DP_TRANS_P0_FLDMASK 0x4
2971
#define FEC_PATTERN_NEW_DP_TRANS_P0_FLDMASK_POS 2
2972
#define FEC_PATTERN_NEW_DP_TRANS_P0_FLDMASK_LEN 1
2973
2974
#define FEC_INSERT_FIFO_EMPTY_DP_TRANS_P0_FLDMASK 0x10
2975
#define FEC_INSERT_FIFO_EMPTY_DP_TRANS_P0_FLDMASK_POS 4
2976
#define FEC_INSERT_FIFO_EMPTY_DP_TRANS_P0_FLDMASK_LEN 1
2977
2978
#define FEC_INSERT_FIFO_EMPTY_CLR_DP_TRANS_P0_FLDMASK 0x20
2979
#define FEC_INSERT_FIFO_EMPTY_CLR_DP_TRANS_P0_FLDMASK_POS 5
2980
#define FEC_INSERT_FIFO_EMPTY_CLR_DP_TRANS_P0_FLDMASK_LEN 1
2981
2982
#define FEC_INSERT_FIFO_FULL_DP_TRANS_P0_FLDMASK 0x40
2983
#define FEC_INSERT_FIFO_FULL_DP_TRANS_P0_FLDMASK_POS 6
2984
#define FEC_INSERT_FIFO_FULL_DP_TRANS_P0_FLDMASK_LEN 1
2985
2986
#define FEC_INSERT_FIFO_FULL_CLR_DP_TRANS_P0_FLDMASK 0x80
2987
#define FEC_INSERT_FIFO_FULL_CLR_DP_TRANS_P0_FLDMASK_POS 7
2988
#define FEC_INSERT_FIFO_FULL_CLR_DP_TRANS_P0_FLDMASK_LEN 1
2989
2990
#define PARITY_INTERLEAVER_DATA_INVERT_PIPE_SEL_DP_TRANS_P0_FLDMASK 0x700
2991
#define PARITY_INTERLEAVER_DATA_INVERT_PIPE_SEL_DP_TRANS_P0_FLDMASK_POS 8
2992
#define PARITY_INTERLEAVER_DATA_INVERT_PIPE_SEL_DP_TRANS_P0_FLDMASK_LEN 3
2993
2994
#define PAT_INIT_DISPARITY_FEC_DP_TRANS_P0_FLDMASK 0x800
2995
#define PAT_INIT_DISPARITY_FEC_DP_TRANS_P0_FLDMASK_POS 11
2996
#define PAT_INIT_DISPARITY_FEC_DP_TRANS_P0_FLDMASK_LEN 1
2997
2998
#define FEC_PARITY_DATA_LANE_SWAP_DP_TRANS_P0_FLDMASK 0x1000
2999
#define FEC_PARITY_DATA_LANE_SWAP_DP_TRANS_P0_FLDMASK_POS 12
3000
#define FEC_PARITY_DATA_LANE_SWAP_DP_TRANS_P0_FLDMASK_LEN 1
3001
3002
#define REG_3548_DP_TRANS_P0 0x3548
3003
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE0_DP_TRANS_P0_FLDMASK 0x7
3004
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE0_DP_TRANS_P0_FLDMASK_POS 0
3005
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE0_DP_TRANS_P0_FLDMASK_LEN 3
3006
3007
#define FEC_INSERT_SYMBOL_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x8
3008
#define FEC_INSERT_SYMBOL_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 3
3009
#define FEC_INSERT_SYMBOL_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
3010
3011
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE1_DP_TRANS_P0_FLDMASK 0x70
3012
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE1_DP_TRANS_P0_FLDMASK_POS 4
3013
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE1_DP_TRANS_P0_FLDMASK_LEN 3
3014
3015
#define FEC_INSERT_SYMBOL_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x80
3016
#define FEC_INSERT_SYMBOL_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 7
3017
#define FEC_INSERT_SYMBOL_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
3018
3019
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE2_DP_TRANS_P0_FLDMASK 0x700
3020
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE2_DP_TRANS_P0_FLDMASK_POS 8
3021
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE2_DP_TRANS_P0_FLDMASK_LEN 3
3022
3023
#define FEC_INSERT_SYMBOL_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x800
3024
#define FEC_INSERT_SYMBOL_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 11
3025
#define FEC_INSERT_SYMBOL_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
3026
3027
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE3_DP_TRANS_P0_FLDMASK 0x7000
3028
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE3_DP_TRANS_P0_FLDMASK_POS 12
3029
#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE3_DP_TRANS_P0_FLDMASK_LEN 3
3030
3031
#define FEC_INSERT_SYMBOL_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x8000
3032
#define FEC_INSERT_SYMBOL_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 15
3033
#define FEC_INSERT_SYMBOL_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
3034
3035
#define REG_354C_DP_TRANS_P0 0x354C
3036
#define FEC_CP_HIT_LANE0_DP_TRANS_P0_FLDMASK 0x1
3037
#define FEC_CP_HIT_LANE0_DP_TRANS_P0_FLDMASK_POS 0
3038
#define FEC_CP_HIT_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
3039
3040
#define FEC_CP_HIT_LANE1_DP_TRANS_P0_FLDMASK 0x2
3041
#define FEC_CP_HIT_LANE1_DP_TRANS_P0_FLDMASK_POS 1
3042
#define FEC_CP_HIT_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
3043
3044
#define FEC_CP_HIT_LANE2_DP_TRANS_P0_FLDMASK 0x4
3045
#define FEC_CP_HIT_LANE2_DP_TRANS_P0_FLDMASK_POS 2
3046
#define FEC_CP_HIT_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
3047
3048
#define FEC_CP_HIT_LANE3_DP_TRANS_P0_FLDMASK 0x8
3049
#define FEC_CP_HIT_LANE3_DP_TRANS_P0_FLDMASK_POS 3
3050
#define FEC_CP_HIT_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
3051
3052
#define FEC_CP_HIT_CLR_DP_TRANS_P0_FLDMASK 0x10
3053
#define FEC_CP_HIT_CLR_DP_TRANS_P0_FLDMASK_POS 4
3054
#define FEC_CP_HIT_CLR_DP_TRANS_P0_FLDMASK_LEN 1
3055
3056
#define FEC_ENCODE_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK 0x300
3057
#define FEC_ENCODE_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_POS 8
3058
#define FEC_ENCODE_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_LEN 2
3059
3060
#define FEC_INSERT_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK 0xc00
3061
#define FEC_INSERT_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_POS 10
3062
#define FEC_INSERT_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_LEN 2
3063
3064
#define REG_3550_DP_TRANS_P0 0x3550
3065
#define FEC_INSERT_FIFO_WCNT_DP_TRANS_P0_FLDMASK 0x1f
3066
#define FEC_INSERT_FIFO_WCNT_DP_TRANS_P0_FLDMASK_POS 0
3067
#define FEC_INSERT_FIFO_WCNT_DP_TRANS_P0_FLDMASK_LEN 5
3068
3069
#define FEC_INSERT_FIFO_RCNT_DP_TRANS_P0_FLDMASK 0x1f00
3070
#define FEC_INSERT_FIFO_RCNT_DP_TRANS_P0_FLDMASK_POS 8
3071
#define FEC_INSERT_FIFO_RCNT_DP_TRANS_P0_FLDMASK_LEN 5
3072
3073
#define REG_3554_DP_TRANS_P0 0x3554
3074
#define FEC_CLK_GATE_DATA_CNT_0_DP_TRANS_P0_FLDMASK 0x7f
3075
#define FEC_CLK_GATE_DATA_CNT_0_DP_TRANS_P0_FLDMASK_POS 0
3076
#define FEC_CLK_GATE_DATA_CNT_0_DP_TRANS_P0_FLDMASK_LEN 7
3077
3078
#define REG_3558_DP_TRANS_P0 0x3558
3079
#define FEC_CLK_GATE_DATA_CNT_1_0_DP_TRANS_P0_FLDMASK 0xffff
3080
#define FEC_CLK_GATE_DATA_CNT_1_0_DP_TRANS_P0_FLDMASK_POS 0
3081
#define FEC_CLK_GATE_DATA_CNT_1_0_DP_TRANS_P0_FLDMASK_LEN 16
3082
3083
#define REG_355C_DP_TRANS_P0 0x355C
3084
#define FEC_CLK_GATE_DATA_CNT_1_1_DP_TRANS_P0_FLDMASK 0x3
3085
#define FEC_CLK_GATE_DATA_CNT_1_1_DP_TRANS_P0_FLDMASK_POS 0
3086
#define FEC_CLK_GATE_DATA_CNT_1_1_DP_TRANS_P0_FLDMASK_LEN 2
3087
3088
#define REG_3580_DP_TRANS_P0 0x3580
3089
#define DP_TX_TRANS_TESTBUS_SEL_DP_TRANS_P0_FLDMASK 0x1f
3090
#define DP_TX_TRANS_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_POS 0
3091
#define DP_TX_TRANS_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_LEN 5
3092
3093
#define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_FLDMASK 0x100
3094
#define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_FLDMASK_POS 8
3095
#define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_FLDMASK_LEN 1
3096
3097
#define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_FLDMASK 0x200
3098
#define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_FLDMASK_POS 9
3099
#define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_FLDMASK_LEN 1
3100
3101
#define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_FLDMASK 0x400
3102
#define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_FLDMASK_POS 10
3103
#define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_FLDMASK_LEN 1
3104
3105
#define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_FLDMASK 0x800
3106
#define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_FLDMASK_POS 11
3107
#define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_FLDMASK_LEN 1
3108
3109
#define REG_3584_DP_TRANS_P0 0x3584
3110
#define POST_MISC_DATA_LANE0_0_DP_TRANS_P0_FLDMASK 0xffff
3111
#define POST_MISC_DATA_LANE0_0_DP_TRANS_P0_FLDMASK_POS 0
3112
#define POST_MISC_DATA_LANE0_0_DP_TRANS_P0_FLDMASK_LEN 16
3113
3114
#define REG_3588_DP_TRANS_P0 0x3588
3115
#define POST_MISC_DATA_LANE0_1_DP_TRANS_P0_FLDMASK 0xffff
3116
#define POST_MISC_DATA_LANE0_1_DP_TRANS_P0_FLDMASK_POS 0
3117
#define POST_MISC_DATA_LANE0_1_DP_TRANS_P0_FLDMASK_LEN 16
3118
3119
#define REG_358C_DP_TRANS_P0 0x358C
3120
#define POST_MISC_DATA_LANE0_2_DP_TRANS_P0_FLDMASK 0xff
3121
#define POST_MISC_DATA_LANE0_2_DP_TRANS_P0_FLDMASK_POS 0
3122
#define POST_MISC_DATA_LANE0_2_DP_TRANS_P0_FLDMASK_LEN 8
3123
3124
#define REG_3590_DP_TRANS_P0 0x3590
3125
#define POST_MISC_DATA_LANE1_0_DP_TRANS_P0_FLDMASK 0xffff
3126
#define POST_MISC_DATA_LANE1_0_DP_TRANS_P0_FLDMASK_POS 0
3127
#define POST_MISC_DATA_LANE1_0_DP_TRANS_P0_FLDMASK_LEN 16
3128
3129
#define REG_3594_DP_TRANS_P0 0x3594
3130
#define POST_MISC_DATA_LANE1_1_DP_TRANS_P0_FLDMASK 0xffff
3131
#define POST_MISC_DATA_LANE1_1_DP_TRANS_P0_FLDMASK_POS 0
3132
#define POST_MISC_DATA_LANE1_1_DP_TRANS_P0_FLDMASK_LEN 16
3133
3134
#define REG_3598_DP_TRANS_P0 0x3598
3135
#define POST_MISC_DATA_LANE1_2_DP_TRANS_P0_FLDMASK 0xff
3136
#define POST_MISC_DATA_LANE1_2_DP_TRANS_P0_FLDMASK_POS 0
3137
#define POST_MISC_DATA_LANE1_2_DP_TRANS_P0_FLDMASK_LEN 8
3138
3139
#define REG_359C_DP_TRANS_P0 0x359C
3140
#define POST_MISC_DATA_LANE2_0_DP_TRANS_P0_FLDMASK 0xffff
3141
#define POST_MISC_DATA_LANE2_0_DP_TRANS_P0_FLDMASK_POS 0
3142
#define POST_MISC_DATA_LANE2_0_DP_TRANS_P0_FLDMASK_LEN 16
3143
3144
#define REG_35A0_DP_TRANS_P0 0x35A0
3145
#define POST_MISC_DATA_LANE2_1_DP_TRANS_P0_FLDMASK 0xffff
3146
#define POST_MISC_DATA_LANE2_1_DP_TRANS_P0_FLDMASK_POS 0
3147
#define POST_MISC_DATA_LANE2_1_DP_TRANS_P0_FLDMASK_LEN 16
3148
3149
#define REG_35A4_DP_TRANS_P0 0x35A4
3150
#define POST_MISC_DATA_LANE2_2_DP_TRANS_P0_FLDMASK 0xff
3151
#define POST_MISC_DATA_LANE2_2_DP_TRANS_P0_FLDMASK_POS 0
3152
#define POST_MISC_DATA_LANE2_2_DP_TRANS_P0_FLDMASK_LEN 8
3153
3154
#define REG_35A8_DP_TRANS_P0 0x35A8
3155
#define POST_MISC_DATA_LANE3_0_DP_TRANS_P0_FLDMASK 0xffff
3156
#define POST_MISC_DATA_LANE3_0_DP_TRANS_P0_FLDMASK_POS 0
3157
#define POST_MISC_DATA_LANE3_0_DP_TRANS_P0_FLDMASK_LEN 16
3158
3159
#define REG_35AC_DP_TRANS_P0 0x35AC
3160
#define POST_MISC_DATA_LANE3_1_DP_TRANS_P0_FLDMASK 0xffff
3161
#define POST_MISC_DATA_LANE3_1_DP_TRANS_P0_FLDMASK_POS 0
3162
#define POST_MISC_DATA_LANE3_1_DP_TRANS_P0_FLDMASK_LEN 16
3163
3164
#define REG_35B0_DP_TRANS_P0 0x35B0
3165
#define POST_MISC_DATA_LANE3_2_DP_TRANS_P0_FLDMASK 0xff
3166
#define POST_MISC_DATA_LANE3_2_DP_TRANS_P0_FLDMASK_POS 0
3167
#define POST_MISC_DATA_LANE3_2_DP_TRANS_P0_FLDMASK_LEN 8
3168
3169
#define REG_35C0_DP_TRANS_P0 0x35C0
3170
#define SW_IRQ_SRC_DP_TRANS_P0_FLDMASK 0xffff
3171
#define SW_IRQ_SRC_DP_TRANS_P0_FLDMASK_POS 0
3172
#define SW_IRQ_SRC_DP_TRANS_P0_FLDMASK_LEN 16
3173
3174
#define REG_35C4_DP_TRANS_P0 0x35C4
3175
#define SW_IRQ_MASK_DP_TRANS_P0_FLDMASK 0xffff
3176
#define SW_IRQ_MASK_DP_TRANS_P0_FLDMASK_POS 0
3177
#define SW_IRQ_MASK_DP_TRANS_P0_FLDMASK_LEN 16
3178
3179
#define REG_35C8_DP_TRANS_P0 0x35C8
3180
#define SW_IRQ_CLR_DP_TRANS_P0_FLDMASK 0xffff
3181
#define SW_IRQ_CLR_DP_TRANS_P0_FLDMASK_POS 0
3182
#define SW_IRQ_CLR_DP_TRANS_P0_FLDMASK_LEN 16
3183
3184
#define REG_35CC_DP_TRANS_P0 0x35CC
3185
#define SW_IRQ_STATUS_DP_TRANS_P0_FLDMASK 0xffff
3186
#define SW_IRQ_STATUS_DP_TRANS_P0_FLDMASK_POS 0
3187
#define SW_IRQ_STATUS_DP_TRANS_P0_FLDMASK_LEN 16
3188
3189
#define REG_35D0_DP_TRANS_P0 0x35D0
3190
#define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_FLDMASK 0xffff
3191
#define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_FLDMASK_POS 0
3192
#define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_FLDMASK_LEN 16
3193
3194
#define REG_35D4_DP_TRANS_P0 0x35D4
3195
#define SW_IRQ_RAW_STATUS_DP_TRANS_P0_FLDMASK 0xffff
3196
#define SW_IRQ_RAW_STATUS_DP_TRANS_P0_FLDMASK_POS 0
3197
#define SW_IRQ_RAW_STATUS_DP_TRANS_P0_FLDMASK_LEN 16
3198
3199
#define REG_35D8_DP_TRANS_P0 0x35D8
3200
#define SW_IRQ_FORCE_DP_TRANS_P0_FLDMASK 0xffff
3201
#define SW_IRQ_FORCE_DP_TRANS_P0_FLDMASK_POS 0
3202
#define SW_IRQ_FORCE_DP_TRANS_P0_FLDMASK_LEN 16
3203
3204
#define REG_35F0_DP_TRANS_P0 0x35F0
3205
#define DP_TRANSMITTER_DUMMY_RW_0_DP_TRANS_P0_FLDMASK 0xffff
3206
#define DP_TRANSMITTER_DUMMY_RW_0_DP_TRANS_P0_FLDMASK_POS 0
3207
#define DP_TRANSMITTER_DUMMY_RW_0_DP_TRANS_P0_FLDMASK_LEN 16
3208
3209
#define REG_35F4_DP_TRANS_P0 0x35F4
3210
#define DP_TRANSMITTER_DUMMY_RW_1_DP_TRANS_P0_FLDMASK 0xffff
3211
#define DP_TRANSMITTER_DUMMY_RW_1_DP_TRANS_P0_FLDMASK_POS 0
3212
#define DP_TRANSMITTER_DUMMY_RW_1_DP_TRANS_P0_FLDMASK_LEN 16
3213
3214
#define REG_35F8_DP_TRANS_P0 0x35F8
3215
#define DP_TRANSMITTER_DUMMY_R_0_DP_TRANS_P0_FLDMASK 0xffff
3216
#define DP_TRANSMITTER_DUMMY_R_0_DP_TRANS_P0_FLDMASK_POS 0
3217
#define DP_TRANSMITTER_DUMMY_R_0_DP_TRANS_P0_FLDMASK_LEN 16
3218
3219
#define REG_35FC_DP_TRANS_P0 0x35FC
3220
#define DP_TRANSMITTER_DUMMY_R_1_DP_TRANS_P0_FLDMASK 0xffff
3221
#define DP_TRANSMITTER_DUMMY_R_1_DP_TRANS_P0_FLDMASK_POS 0
3222
#define DP_TRANSMITTER_DUMMY_R_1_DP_TRANS_P0_FLDMASK_LEN 16
3223
3224
#define REG_3600_AUX_TX_P0 0x3600
3225
#define DP_TX_SW_RESET_AUX_TX_P0_FLDMASK 0x1
3226
#define DP_TX_SW_RESET_AUX_TX_P0_FLDMASK_POS 0
3227
#define DP_TX_SW_RESET_AUX_TX_P0_FLDMASK_LEN 1
3228
3229
#define AUX_TOP_RESET_AUX_TX_P0_FLDMASK 0x2
3230
#define AUX_TOP_RESET_AUX_TX_P0_FLDMASK_POS 1
3231
#define AUX_TOP_RESET_AUX_TX_P0_FLDMASK_LEN 1
3232
3233
#define SOFTWARE_RESET_RESERVED_AUX_TX_P0_FLDMASK 0x1c
3234
#define SOFTWARE_RESET_RESERVED_AUX_TX_P0_FLDMASK_POS 2
3235
#define SOFTWARE_RESET_RESERVED_AUX_TX_P0_FLDMASK_LEN 3
3236
3237
#define AUX_CLK_EN_AUX_TX_P0_FLDMASK 0x100
3238
#define AUX_CLK_EN_AUX_TX_P0_FLDMASK_POS 8
3239
#define AUX_CLK_EN_AUX_TX_P0_FLDMASK_LEN 1
3240
3241
#define AUX_CLK_INV_AUX_TX_P0_FLDMASK 0x200
3242
#define AUX_CLK_INV_AUX_TX_P0_FLDMASK_POS 9
3243
#define AUX_CLK_INV_AUX_TX_P0_FLDMASK_LEN 1
3244
3245
#define AUX_CLK_SEL_AUX_TX_P0_FLDMASK 0xc00
3246
#define AUX_CLK_SEL_AUX_TX_P0_FLDMASK_POS 10
3247
#define AUX_CLK_SEL_AUX_TX_P0_FLDMASK_LEN 2
3248
3249
#define REG_3604_AUX_TX_P0 0x3604
3250
#define AUX_TX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK 0x8000
3251
#define AUX_TX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_POS 15
3252
#define AUX_TX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_LEN 1
3253
3254
#define AUX_TX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK 0x4000
3255
#define AUX_TX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_POS 14
3256
#define AUX_TX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_LEN 1
3257
3258
#define AUX_RX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK 0x2000
3259
#define AUX_RX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_POS 13
3260
#define AUX_RX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_LEN 1
3261
3262
#define AUX_RX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK 0x1000
3263
#define AUX_RX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_POS 12
3264
#define AUX_RX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_LEN 1
3265
3266
#define DP_TX_TESTBUS_SEL_AUX_TX_P0_FLDMASK 0xff
3267
#define DP_TX_TESTBUS_SEL_AUX_TX_P0_FLDMASK_POS 0
3268
#define DP_TX_TESTBUS_SEL_AUX_TX_P0_FLDMASK_LEN 8
3269
3270
#define REG_3608_AUX_TX_P0 0x3608
3271
#define DP_TX_INT_STATUS_AUX_TX_P0_FLDMASK 0xffff
3272
#define DP_TX_INT_STATUS_AUX_TX_P0_FLDMASK_POS 0
3273
#define DP_TX_INT_STATUS_AUX_TX_P0_FLDMASK_LEN 16
3274
3275
#define REG_360C_AUX_TX_P0 0x360C
3276
#define AUX_SWAP_AUX_TX_P0_FLDMASK 0x8000
3277
#define AUX_SWAP_AUX_TX_P0_FLDMASK_POS 15
3278
#define AUX_SWAP_AUX_TX_P0_FLDMASK_LEN 1
3279
3280
#define AUX_AUX_REPLY_MCU_AUX_TX_P0_FLDMASK 0x4000
3281
#define AUX_AUX_REPLY_MCU_AUX_TX_P0_FLDMASK_POS 14
3282
#define AUX_AUX_REPLY_MCU_AUX_TX_P0_FLDMASK_LEN 1
3283
3284
#define AUX_TIMEOUT_CMP_MASK_AUX_TX_P0_FLDMASK 0x2000
3285
#define AUX_TIMEOUT_CMP_MASK_AUX_TX_P0_FLDMASK_POS 13
3286
#define AUX_TIMEOUT_CMP_MASK_AUX_TX_P0_FLDMASK_LEN 1
3287
3288
#define AUX_TIMEOUT_THR_AUX_TX_P0_FLDMASK 0x1fff
3289
#define AUX_TIMEOUT_THR_AUX_TX_P0_FLDMASK_POS 0
3290
#define AUX_TIMEOUT_THR_AUX_TX_P0_FLDMASK_LEN 13
3291
3292
#define REG_3610_AUX_TX_P0 0x3610
3293
#define AUX_EDID_REPLY_MCU_AUX_TX_P0_FLDMASK 0x8000
3294
#define AUX_EDID_REPLY_MCU_AUX_TX_P0_FLDMASK_POS 15
3295
#define AUX_EDID_REPLY_MCU_AUX_TX_P0_FLDMASK_LEN 1
3296
3297
#define AUX_EDID_ADDR_AUX_TX_P0_FLDMASK 0x7f00
3298
#define AUX_EDID_ADDR_AUX_TX_P0_FLDMASK_POS 8
3299
#define AUX_EDID_ADDR_AUX_TX_P0_FLDMASK_LEN 7
3300
3301
#define AUX_MCCS_REPLY_MCU_AUX_TX_P0_FLDMASK 0x80
3302
#define AUX_MCCS_REPLY_MCU_AUX_TX_P0_FLDMASK_POS 7
3303
#define AUX_MCCS_REPLY_MCU_AUX_TX_P0_FLDMASK_LEN 1
3304
3305
#define AUX_MCCS_ADDR_AUX_TX_P0_FLDMASK 0x7f
3306
#define AUX_MCCS_ADDR_AUX_TX_P0_FLDMASK_POS 0
3307
#define AUX_MCCS_ADDR_AUX_TX_P0_FLDMASK_LEN 7
3308
3309
#define REG_3614_AUX_TX_P0 0x3614
3310
#define AUX_TIMEOUT_THR_EXTEN_AUX_TX_P0_FLDMASK 0x4000
3311
#define AUX_TIMEOUT_THR_EXTEN_AUX_TX_P0_FLDMASK_POS 14
3312
#define AUX_TIMEOUT_THR_EXTEN_AUX_TX_P0_FLDMASK_LEN 1
3313
3314
#define AUX_RX_AVERAGE_SEL_AUX_TX_P0_FLDMASK 0x3000
3315
#define AUX_RX_AVERAGE_SEL_AUX_TX_P0_FLDMASK_POS 12
3316
#define AUX_RX_AVERAGE_SEL_AUX_TX_P0_FLDMASK_LEN 2
3317
3318
#define AUX_RX_SYNC_PATTERN_THR_AUX_TX_P0_FLDMASK 0xf00
3319
#define AUX_RX_SYNC_PATTERN_THR_AUX_TX_P0_FLDMASK_POS 8
3320
#define AUX_RX_SYNC_PATTERN_THR_AUX_TX_P0_FLDMASK_LEN 4
3321
3322
#define AUX_RX_DECODE_SEL_AUX_TX_P0_FLDMASK 0x80
3323
#define AUX_RX_DECODE_SEL_AUX_TX_P0_FLDMASK_POS 7
3324
#define AUX_RX_DECODE_SEL_AUX_TX_P0_FLDMASK_LEN 1
3325
3326
#define AUX_RX_UI_CNT_THR_AUX_TX_P0_FLDMASK 0x7f
3327
#define AUX_RX_UI_CNT_THR_AUX_TX_P0_FLDMASK_POS 0
3328
#define AUX_RX_UI_CNT_THR_AUX_TX_P0_FLDMASK_LEN 7
3329
3330
#define REG_3618_AUX_TX_P0 0x3618
3331
#define AUX_RX_DP_REV_AUX_TX_P0_FLDMASK 0x400
3332
#define AUX_RX_DP_REV_AUX_TX_P0_FLDMASK_POS 10
3333
#define AUX_RX_DP_REV_AUX_TX_P0_FLDMASK_LEN 1
3334
3335
#define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK 0x200
3336
#define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK_POS 9
3337
#define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK_LEN 1
3338
3339
#define AUX_RX_FIFO_EMPTY_AUX_TX_P0_FLDMASK 0x100
3340
#define AUX_RX_FIFO_EMPTY_AUX_TX_P0_FLDMASK_POS 8
3341
#define AUX_RX_FIFO_EMPTY_AUX_TX_P0_FLDMASK_LEN 1
3342
3343
#define AUX_RX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK 0xf0
3344
#define AUX_RX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK_POS 4
3345
#define AUX_RX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK_LEN 4
3346
3347
#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK 0xf
3348
#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK_POS 0
3349
#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK_LEN 4
3350
3351
#define REG_361C_AUX_TX_P0 0x361C
3352
#define AUX_RX_DATA_BYTE_CNT_AUX_TX_P0_FLDMASK 0xff00
3353
#define AUX_RX_DATA_BYTE_CNT_AUX_TX_P0_FLDMASK_POS 8
3354
#define AUX_RX_DATA_BYTE_CNT_AUX_TX_P0_FLDMASK_LEN 8
3355
3356
#define AUX_RESERVED_RO_0_AUX_TX_P0_FLDMASK 0xff
3357
#define AUX_RESERVED_RO_0_AUX_TX_P0_FLDMASK_POS 0
3358
#define AUX_RESERVED_RO_0_AUX_TX_P0_FLDMASK_LEN 8
3359
3360
#define REG_3620_AUX_TX_P0 0x3620
3361
#define AUX_RD_MODE_AUX_TX_P0_FLDMASK 0x200
3362
#define AUX_RD_MODE_AUX_TX_P0_FLDMASK_POS 9
3363
#define AUX_RD_MODE_AUX_TX_P0_FLDMASK_LEN 1
3364
3365
#define AUX_RX_FIFO_READ_PULSE_TX_P0_FLDMASK 0x100
3366
#define AUX_RX_FIFO_R_PULSE_TX_P0_FLDMASK_POS 8
3367
#define AUX_RX_FIFO_READ_PULSE_AUX_TX_P0_FLDMASK_LEN 1
3368
3369
#define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_FLDMASK 0xff
3370
#define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_FLDMASK_POS 0
3371
#define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_FLDMASK_LEN 8
3372
3373
#define REG_3624_AUX_TX_P0 0x3624
3374
#define AUX_RX_REPLY_COMMAND_AUX_TX_P0_FLDMASK 0xf
3375
#define AUX_RX_REPLY_COMMAND_AUX_TX_P0_FLDMASK_POS 0
3376
#define AUX_RX_REPLY_COMMAND_AUX_TX_P0_FLDMASK_LEN 4
3377
3378
#define AUX_RX_REPLY_ADDRESS_NONE_AUX_TX_P0_FLDMASK 0xf00
3379
#define AUX_RX_REPLY_ADDRESS_NONE_AUX_TX_P0_FLDMASK_POS 8
3380
#define AUX_RX_REPLY_ADDRESS_NONE_AUX_TX_P0_FLDMASK_LEN 4
3381
3382
#define REG_3628_AUX_TX_P0 0x3628
3383
#define AUX_RESERVED_RO_1_AUX_TX_P0_FLDMASK 0xfc00
3384
#define AUX_RESERVED_RO_1_AUX_TX_P0_FLDMASK_POS 10
3385
#define AUX_RESERVED_RO_1_AUX_TX_P0_FLDMASK_LEN 6
3386
3387
#define AUX_RX_PHY_STATE_AUX_TX_P0_FLDMASK 0x3ff
3388
#define AUX_RX_PHY_STATE_AUX_TX_P0_FLDMASK_POS 0
3389
#define AUX_RX_PHY_STATE_AUX_TX_P0_FLDMASK_LEN 10
3390
3391
#define REG_362C_AUX_TX_P0 0x362C
3392
#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK 0x1
3393
#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_POS 0
3394
#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_LEN 1
3395
3396
#define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_FLDMASK 0x2
3397
#define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_FLDMASK_POS 1
3398
#define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_FLDMASK_LEN 1
3399
3400
#define AUX_RESERVED_RW_0_AUX_TX_P0_FLDMASK 0xfffc
3401
#define AUX_RESERVED_RW_0_AUX_TX_P0_FLDMASK_POS 2
3402
#define AUX_RESERVED_RW_0_AUX_TX_P0_FLDMASK_LEN 14
3403
3404
#define REG_3630_AUX_TX_P0 0x3630
3405
#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK 0x8
3406
#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_POS 3
3407
#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_LEN 1
3408
3409
#define AUX_TX_PRE_NUM_AUX_TX_P0_FLDMASK 0xff00
3410
#define AUX_TX_PRE_NUM_AUX_TX_P0_FLDMASK_POS 8
3411
#define AUX_TX_PRE_NUM_AUX_TX_P0_FLDMASK_LEN 8
3412
3413
#define REG_3634_AUX_TX_P0 0x3634
3414
#define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_FLDMASK 0xff00
3415
#define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_FLDMASK_POS 8
3416
#define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_FLDMASK_LEN 8
3417
3418
#define AUX_TX_FIFO_WRITE_DATA_AUX_TX_P0_FLDMASK 0xff
3419
#define AUX_TX_FIFO_WRITE_DATA_AUX_TX_P0_FLDMASK_POS 0
3420
#define AUX_TX_FIFO_WRITE_DATA_AUX_TX_P0_FLDMASK_LEN 8
3421
3422
#define REG_3638_AUX_TX_P0 0x3638
3423
#define AUX_TX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK 0xf0
3424
#define AUX_TX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK_POS 4
3425
#define AUX_TX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK_LEN 4
3426
3427
#define AUX_TX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK 0xf
3428
#define AUX_TX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK_POS 0
3429
#define AUX_TX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK_LEN 4
3430
3431
#define REG_363C_AUX_TX_P0 0x363C
3432
#define AUX_TX_FIFO_FULL_AUX_TX_P0_FLDMASK 0x1000
3433
#define AUX_TX_FIFO_FULL_AUX_TX_P0_FLDMASK_POS 12
3434
#define AUX_TX_FIFO_FULL_AUX_TX_P0_FLDMASK_LEN 1
3435
3436
#define AUX_TX_FIFO_EMPTY_AUX_TX_P0_FLDMASK 0x800
3437
#define AUX_TX_FIFO_EMPTY_AUX_TX_P0_FLDMASK_POS 11
3438
#define AUX_TX_FIFO_EMPTY_AUX_TX_P0_FLDMASK_LEN 1
3439
3440
#define AUX_TX_PHY_STATE_AUX_TX_P0_FLDMASK 0x7ff
3441
#define AUX_TX_PHY_STATE_AUX_TX_P0_FLDMASK_POS 0
3442
#define AUX_TX_PHY_STATE_AUX_TX_P0_FLDMASK_LEN 11
3443
3444
#define REG_3640_AUX_TX_P0 0x3640
3445
#define AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK 0x40
3446
#define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_POS 6
3447
#define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_LEN 1
3448
3449
#define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK 0x20
3450
#define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_POS 5
3451
#define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_LEN 1
3452
3453
#define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK 0x10
3454
#define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_POS 4
3455
#define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_LEN 1
3456
3457
#define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0_FLDMASK 0x8
3458
#define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0_FLDMASK_POS 3
3459
#define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0_FLDMASK_LEN 1
3460
3461
#define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_FLDMASK 0x4
3462
#define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_FLDMASK_POS 2
3463
#define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_FLDMASK_LEN 1
3464
3465
#define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_FLDMASK 0x2
3466
#define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_FLDMASK_POS 1
3467
#define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_FLDMASK_LEN 1
3468
3469
#define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK 0x1
3470
#define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK_POS 0
3471
#define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK_LEN 1
3472
3473
#define REG_3644_AUX_TX_P0 0x3644
3474
#define MCU_REQUEST_COMMAND_AUX_TX_P0_FLDMASK 0xf
3475
#define MCU_REQUEST_COMMAND_AUX_TX_P0_FLDMASK_POS 0
3476
#define MCU_REQUEST_COMMAND_AUX_TX_P0_FLDMASK_LEN 4
3477
3478
#define AUX_STATE_AUX_TX_P0_FLDMASK 0xf00
3479
#define AUX_STATE_AUX_TX_P0_FLDMASK_POS 8
3480
#define AUX_STATE_AUX_TX_P0_FLDMASK_LEN 4
3481
3482
#define REG_3648_AUX_TX_P0 0x3648
3483
#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_FLDMASK 0xffff
3484
#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_FLDMASK_POS 0
3485
#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_FLDMASK_LEN 16
3486
3487
#define REG_364C_AUX_TX_P0 0x364C
3488
#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_FLDMASK 0xf
3489
#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_FLDMASK_POS 0
3490
#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_FLDMASK_LEN 4
3491
3492
#define REG_3650_AUX_TX_P0 0x3650
3493
#define MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK 0xf000
3494
#define MCU_REQ_DATA_NUM_AUX_TX_P0_FLDMASK_POS 12
3495
#define MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK_LEN 4
3496
3497
#define PHY_FIFO_RST_AUX_TX_P0_FLDMASK 0x200
3498
#define PHY_FIFO_RST_AUX_TX_P0_FLDMASK_POS 9
3499
#define PHY_FIFO_RST_AUX_TX_P0_FLDMASK_LEN 1
3500
3501
#define MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK 0x100
3502
#define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS 8
3503
#define MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK_LEN 1
3504
3505
#define AUX_TEST_CONFIG_AUX_TX_P0_FLDMASK 0xff
3506
#define AUX_TEST_CONFIG_AUX_TX_P0_FLDMASK_POS 0
3507
#define AUX_TEST_CONFIG_AUX_TX_P0_FLDMASK_LEN 8
3508
3509
#define REG_3654_AUX_TX_P0 0x3654
3510
#define TST_AUXRX_AUX_TX_P0_FLDMASK 0xff
3511
#define TST_AUXRX_AUX_TX_P0_FLDMASK_POS 0
3512
#define TST_AUXRX_AUX_TX_P0_FLDMASK_LEN 8
3513
3514
#define REG_3658_AUX_TX_P0 0x3658
3515
#define AUX_TX_OV_EN_AUX_TX_P0_FLDMASK 0x1
3516
#define AUX_TX_OV_EN_AUX_TX_P0_FLDMASK_POS 0
3517
#define AUX_TX_OV_EN_AUX_TX_P0_FLDMASK_LEN 1
3518
3519
#define AUX_TX_VALUE_SET_AUX_TX_P0_FLDMASK 0x2
3520
#define AUX_TX_VALUE_SET_AUX_TX_P0_FLDMASK_POS 1
3521
#define AUX_TX_VALUE_SET_AUX_TX_P0_FLDMASK_LEN 1
3522
3523
#define AUX_TX_OEN_SET_AUX_TX_P0_FLDMASK 0x4
3524
#define AUX_TX_OEN_SET_AUX_TX_P0_FLDMASK_POS 2
3525
#define AUX_TX_OEN_SET_AUX_TX_P0_FLDMASK_LEN 1
3526
3527
#define AUX_TX_OV_MODE_AUX_TX_P0_FLDMASK 0x8
3528
#define AUX_TX_OV_MODE_AUX_TX_P0_FLDMASK_POS 3
3529
#define AUX_TX_OV_MODE_AUX_TX_P0_FLDMASK_LEN 1
3530
3531
#define AUX_TX_OFF_AUX_TX_P0_FLDMASK 0x10
3532
#define AUX_TX_OFF_AUX_TX_P0_FLDMASK_POS 4
3533
#define AUX_TX_OFF_AUX_TX_P0_FLDMASK_LEN 1
3534
3535
#define EXT_AUX_PHY_MODE_AUX_TX_P0_FLDMASK 0x20
3536
#define EXT_AUX_PHY_MODE_AUX_TX_P0_FLDMASK_POS 5
3537
#define EXT_AUX_PHY_MODE_AUX_TX_P0_FLDMASK_LEN 1
3538
3539
#define EXT_TX_OEN_POLARITY_AUX_TX_P0_FLDMASK 0x40
3540
#define EXT_TX_OEN_POLARITY_AUX_TX_P0_FLDMASK_POS 6
3541
#define EXT_TX_OEN_POLARITY_AUX_TX_P0_FLDMASK_LEN 1
3542
3543
#define AUX_RX_OEN_SET_AUX_TX_P0_FLDMASK 0x80
3544
#define AUX_RX_OEN_SET_AUX_TX_P0_FLDMASK_POS 7
3545
#define AUX_RX_OEN_SET_AUX_TX_P0_FLDMASK_LEN 1
3546
3547
#define REG_365C_AUX_TX_P0 0x365C
3548
#define AUX_RCTRL_AUX_TX_P0_FLDMASK 0x1f
3549
#define AUX_RCTRL_AUX_TX_P0_FLDMASK_POS 0
3550
#define AUX_RCTRL_AUX_TX_P0_FLDMASK_LEN 5
3551
3552
#define AUX_RPD_AUX_TX_P0_FLDMASK 0x20
3553
#define AUX_RPD_AUX_TX_P0_FLDMASK_POS 5
3554
#define AUX_RPD_AUX_TX_P0_FLDMASK_LEN 1
3555
3556
#define AUX_RX_SEL_AUX_TX_P0_FLDMASK 0x40
3557
#define AUX_RX_SEL_AUX_TX_P0_FLDMASK_POS 6
3558
#define AUX_RX_SEL_AUX_TX_P0_FLDMASK_LEN 1
3559
3560
#define AUXRX_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK 0x80
3561
#define AUXRX_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_POS 7
3562
#define AUXRX_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_LEN 1
3563
3564
#define AUXRXVALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK 0x100
3565
#define AUXRXVALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_POS 8
3566
#define AUXRXVALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_LEN 1
3567
3568
#define AUX_DEBOUNCE_CLKSEL_AUX_TX_P0_FLDMASK 0xe00
3569
#define AUX_DEBOUNCE_CLKSEL_AUX_TX_P0_FLDMASK_POS 9
3570
#define AUX_DEBOUNCE_CLKSEL_AUX_TX_P0_FLDMASK_LEN 3
3571
3572
#define DATA_VALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK 0x1000
3573
#define DATA_VALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_POS 12
3574
#define DATA_VALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_LEN 1
3575
3576
#define REG_3660_AUX_TX_P0 0x3660
3577
#define DP_TX_INT_MASK_AUX_TX_P0_FLDMASK 0xffff
3578
#define DP_TX_INT_MASK_AUX_TX_P0_FLDMASK_POS 0
3579
#define DP_TX_INT_MASK_AUX_TX_P0_FLDMASK_LEN 16
3580
3581
#define REG_3664_AUX_TX_P0 0x3664
3582
#define DP_TX_INT_FORCE_AUX_TX_P0_FLDMASK 0xffff
3583
#define DP_TX_INT_FORCE_AUX_TX_P0_FLDMASK_POS 0
3584
#define DP_TX_INT_FORCE_AUX_TX_P0_FLDMASK_LEN 16
3585
3586
#define REG_3668_AUX_TX_P0 0x3668
3587
#define DP_TX_INT_CLR_AUX_TX_P0_FLDMASK 0xffff
3588
#define DP_TX_INT_CLR_AUX_TX_P0_FLDMASK_POS 0
3589
#define DP_TX_INT_CLR_AUX_TX_P0_FLDMASK_LEN 16
3590
3591
#define REG_366C_AUX_TX_P0 0x366C
3592
#define XTAL_FREQ_AUX_TX_P0_FLDMASK 0xff00
3593
#define XTAL_FREQ_AUX_TX_P0_FLDMASK_POS 8
3594
#define XTAL_FREQ_AUX_TX_P0_FLDMASK_LEN 8
3595
3596
#define REG_3670_AUX_TX_P0 0x3670
3597
#define DPTX_GPIO_OEN_AUX_TX_P0_FLDMASK 0x7
3598
#define DPTX_GPIO_OEN_AUX_TX_P0_FLDMASK_POS 0
3599
#define DPTX_GPIO_OEN_AUX_TX_P0_FLDMASK_LEN 3
3600
3601
#define DPTX_GPIO_OUT_AUX_TX_P0_FLDMASK 0x38
3602
#define DPTX_GPIO_OUT_AUX_TX_P0_FLDMASK_POS 3
3603
#define DPTX_GPIO_OUT_AUX_TX_P0_FLDMASK_LEN 3
3604
3605
#define DPTX_GPIO_IN_AUX_TX_P0_FLDMASK 0x1c0
3606
#define DPTX_GPIO_IN_AUX_TX_P0_FLDMASK_POS 6
3607
#define DPTX_GPIO_IN_AUX_TX_P0_FLDMASK_LEN 3
3608
3609
#define AUX_IN_AUX_TX_P0_FLDMASK 0x200
3610
#define AUX_IN_AUX_TX_P0_FLDMASK_POS 9
3611
#define AUX_IN_AUX_TX_P0_FLDMASK_LEN 1
3612
3613
#define PD_AUX_RTERM_AUX_TX_P0_FLDMASK 0x400
3614
#define PD_AUX_RTERM_AUX_TX_P0_FLDMASK_POS 10
3615
#define PD_AUX_RTERM_AUX_TX_P0_FLDMASK_LEN 1
3616
3617
#define DPTX_GPIO_EN_AUX_TX_P0_FLDMASK 0x7000
3618
#define DPTX_GPIO_EN_AUX_TX_P0_FLDMASK_POS 12
3619
#define DPTX_GPIO_EN_AUX_TX_P0_FLDMASK_LEN 3
3620
3621
#define REG_3674_AUX_TX_P0 0x3674
3622
#define AUXTX_ISEL_AUX_TX_P0_FLDMASK 0x1f
3623
#define AUXTX_ISEL_AUX_TX_P0_FLDMASK_POS 0
3624
#define AUXTX_ISEL_AUX_TX_P0_FLDMASK_LEN 5
3625
3626
#define AUXRX_VTH_AUX_TX_P0_FLDMASK 0x60
3627
#define AUXRX_VTH_AUX_TX_P0_FLDMASK_POS 5
3628
#define AUXRX_VTH_AUX_TX_P0_FLDMASK_LEN 2
3629
3630
#define EN_RXCM_BOOST_AUX_TX_P0_FLDMASK 0x80
3631
#define EN_RXCM_BOOST_AUX_TX_P0_FLDMASK_POS 7
3632
#define EN_RXCM_BOOST_AUX_TX_P0_FLDMASK_LEN 1
3633
3634
#define DPTX_AUX_R_CTRL_AUX_TX_P0_FLDMASK 0x1f00
3635
#define DPTX_AUX_R_CTRL_AUX_TX_P0_FLDMASK_POS 8
3636
#define DPTX_AUX_R_CTRL_AUX_TX_P0_FLDMASK_LEN 5
3637
3638
#define I2C_EN_AUXN_AUX_TX_P0_FLDMASK 0x2000
3639
#define I2C_EN_AUXN_AUX_TX_P0_FLDMASK_POS 13
3640
#define I2C_EN_AUXN_AUX_TX_P0_FLDMASK_LEN 1
3641
3642
#define I2C_EN_AUXP_AUX_TX_P0_FLDMASK 0x4000
3643
#define I2C_EN_AUXP_AUX_TX_P0_FLDMASK_POS 14
3644
#define I2C_EN_AUXP_AUX_TX_P0_FLDMASK_LEN 1
3645
3646
#define REG_3678_AUX_TX_P0 0x3678
3647
#define TEST_AUXTX_AUX_TX_P0_FLDMASK 0xff00
3648
#define TEST_AUXTX_AUX_TX_P0_FLDMASK_POS 8
3649
#define TEST_AUXTX_AUX_TX_P0_FLDMASK_LEN 8
3650
3651
#define REG_367C_AUX_TX_P0 0x367C
3652
#define DPTX_AUXRX_AUX_TX_P0_FLDMASK 0x4
3653
#define DPTX_AUXRX_AUX_TX_P0_FLDMASK_POS 2
3654
#define DPTX_AUXRX_AUX_TX_P0_FLDMASK_LEN 1
3655
3656
#define DPTX_AUXRX_VALID_AUX_TX_P0_FLDMASK 0x8
3657
#define DPTX_AUXRX_VALID_AUX_TX_P0_FLDMASK_POS 3
3658
#define DPTX_AUXRX_VALID_AUX_TX_P0_FLDMASK_LEN 1
3659
3660
#define DPTX_AUXRX_WO_TH_AUX_TX_P0_FLDMASK 0x10
3661
#define DPTX_AUXRX_WO_TH_AUX_TX_P0_FLDMASK_POS 4
3662
#define DPTX_AUXRX_WO_TH_AUX_TX_P0_FLDMASK_LEN 1
3663
3664
#define DPTX_AUXRX_L_TEST_AUX_TX_P0_FLDMASK 0x20
3665
#define DPTX_AUXRX_L_TEST_AUX_TX_P0_FLDMASK_POS 5
3666
#define DPTX_AUXRX_L_TEST_AUX_TX_P0_FLDMASK_LEN 1
3667
3668
#define EN_AUXRX_AUX_TX_P0_FLDMASK 0x400
3669
#define EN_AUXRX_AUX_TX_P0_FLDMASK_POS 10
3670
#define EN_AUXRX_AUX_TX_P0_FLDMASK_LEN 1
3671
3672
#define EN_AUXTX_AUX_TX_P0_FLDMASK 0x800
3673
#define EN_AUXTX_AUX_TX_P0_FLDMASK_POS 11
3674
#define EN_AUXTX_AUX_TX_P0_FLDMASK_LEN 1
3675
3676
#define EN_AUX_AUX_TX_P0_FLDMASK 0x1000
3677
#define EN_AUX_AUX_TX_P0_FLDMASK_POS 12
3678
#define EN_AUX_AUX_TX_P0_FLDMASK_LEN 1
3679
3680
#define EN_5V_TOL_AUX_TX_P0_FLDMASK 0x2000
3681
#define EN_5V_TOL_AUX_TX_P0_FLDMASK_POS 13
3682
#define EN_5V_TOL_AUX_TX_P0_FLDMASK_LEN 1
3683
3684
#define AUXP_I_AUX_TX_P0_FLDMASK 0x4000
3685
#define AUXP_I_AUX_TX_P0_FLDMASK_POS 14
3686
#define AUXP_I_AUX_TX_P0_FLDMASK_LEN 1
3687
3688
#define AUXN_I_AUX_TX_P0_FLDMASK 0x8000
3689
#define AUXN_I_AUX_TX_P0_FLDMASK_POS 15
3690
#define AUXN_I_AUX_TX_P0_FLDMASK_LEN 1
3691
3692
#define REG_3680_AUX_TX_P0 0x3680
3693
#define AUX_SWAP_TX_AUX_TX_P0_FLDMASK 0x1
3694
#define AUX_SWAP_TX_AUX_TX_P0_FLDMASK_POS 0
3695
#define AUX_SWAP_TX_AUX_TX_P0_FLDMASK_LEN 1
3696
3697
#define REG_3684_AUX_TX_P0 0x3684
3698
#define TEST_IO_LOOPBK_AUX_TX_P0_FLDMASK 0x1f
3699
#define TEST_IO_LOOPBK_AUX_TX_P0_FLDMASK_POS 0
3700
#define TEST_IO_LOOPBK_AUX_TX_P0_FLDMASK_LEN 5
3701
3702
#define RO_IO_LOOPBKT_AUX_TX_P0_FLDMASK 0x300
3703
#define RO_IO_LOOPBKT_AUX_TX_P0_FLDMASK_POS 8
3704
#define RO_IO_LOOPBKT_AUX_TX_P0_FLDMASK_LEN 2
3705
3706
#define SEL_TCLK_AUX_TX_P0_FLDMASK 0x3000
3707
#define SEL_TCLK_AUX_TX_P0_FLDMASK_POS 12
3708
#define SEL_TCLK_AUX_TX_P0_FLDMASK_LEN 2
3709
3710
#define TESTEN_ASIO_AUX_TX_P0_FLDMASK 0x4000
3711
#define TESTEN_ASIO_AUX_TX_P0_FLDMASK_POS 14
3712
#define TESTEN_ASIO_AUX_TX_P0_FLDMASK_LEN 1
3713
3714
#define REG_3688_AUX_TX_P0 0x3688
3715
#define TEST_AUXRX_VTH_AUX_TX_P0_FLDMASK 0x7
3716
#define TEST_AUXRX_VTH_AUX_TX_P0_FLDMASK_POS 0
3717
#define TEST_AUXRX_VTH_AUX_TX_P0_FLDMASK_LEN 3
3718
3719
#define REG_368C_AUX_TX_P0 0x368C
3720
#define RX_FIFO_DONE_AUX_TX_P0_FLDMASK 0x1
3721
#define RX_FIFO_DONE_AUX_TX_P0_FLDMASK_POS 0
3722
#define RX_FIFO_DONE_AUX_TX_P0_FLDMASK_LEN 1
3723
3724
#define RX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK 0x2
3725
#define RX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK_POS 1
3726
#define RX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK_LEN 1
3727
3728
#define TX_FIFO_DONE_AUX_TX_P0_FLDMASK 0x4
3729
#define TX_FIFO_DONE_AUX_TX_P0_FLDMASK_POS 2
3730
#define TX_FIFO_DONE_AUX_TX_P0_FLDMASK_LEN 1
3731
3732
#define TX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK 0x8
3733
#define TX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK_POS 3
3734
#define TX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK_LEN 1
3735
3736
#define REG_3690_AUX_TX_P0 0x3690
3737
#define DATA_LOW_CNT_THRD_AUX_TX_P0_FLDMASK 0x7f
3738
#define DATA_LOW_CNT_THRD_AUX_TX_P0_FLDMASK_POS 0
3739
#define DATA_LOW_CNT_THRD_AUX_TX_P0_FLDMASK_LEN 7
3740
3741
#define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_FLDMASK 0x100
3742
#define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_FLDMASK_POS 8
3743
#define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_FLDMASK_LEN 1
3744
3745
#define REG_36C0_AUX_TX_P0 0x36C0
3746
#define RX_GTC_VALUE_0_AUX_TX_P0_FLDMASK 0xffff
3747
#define RX_GTC_VALUE_0_AUX_TX_P0_FLDMASK_POS 0
3748
#define RX_GTC_VALUE_0_AUX_TX_P0_FLDMASK_LEN 16
3749
3750
#define REG_36C4_AUX_TX_P0 0x36C4
3751
#define RX_GTC_VALUE_1_AUX_TX_P0_FLDMASK 0xffff
3752
#define RX_GTC_VALUE_1_AUX_TX_P0_FLDMASK_POS 0
3753
#define RX_GTC_VALUE_1_AUX_TX_P0_FLDMASK_LEN 16
3754
3755
#define REG_36C8_AUX_TX_P0 0x36C8
3756
#define RX_GTC_MASTER_REQ_AUX_TX_P0_FLDMASK 0x1
3757
#define RX_GTC_MASTER_REQ_AUX_TX_P0_FLDMASK_POS 0
3758
#define RX_GTC_MASTER_REQ_AUX_TX_P0_FLDMASK_LEN 1
3759
3760
#define TX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK 0x2
3761
#define TX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK_POS 1
3762
#define TX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK_LEN 1
3763
3764
#define RX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK 0x4
3765
#define RX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK_POS 2
3766
#define RX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK_LEN 1
3767
3768
#define REG_36CC_AUX_TX_P0 0x36CC
3769
#define RX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK 0xffff
3770
#define RX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK_POS 0
3771
#define RX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK_LEN 16
3772
3773
#define REG_36D0_AUX_TX_P0 0x36D0
3774
#define TX_GTC_VALUE_0_AUX_TX_P0_FLDMASK 0xffff
3775
#define TX_GTC_VALUE_0_AUX_TX_P0_FLDMASK_POS 0
3776
#define TX_GTC_VALUE_0_AUX_TX_P0_FLDMASK_LEN 16
3777
3778
#define REG_36D4_AUX_TX_P0 0x36D4
3779
#define TX_GTC_VALUE_1_AUX_TX_P0_FLDMASK 0xffff
3780
#define TX_GTC_VALUE_1_AUX_TX_P0_FLDMASK_POS 0
3781
#define TX_GTC_VALUE_1_AUX_TX_P0_FLDMASK_LEN 16
3782
3783
#define REG_36D8_AUX_TX_P0 0x36D8
3784
#define RX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK 0x1
3785
#define RX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK_POS 0
3786
#define RX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK_LEN 1
3787
3788
#define TX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK 0x2
3789
#define TX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK_POS 1
3790
#define TX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK_LEN 1
3791
3792
#define TX_GTC_VALUE_PHASE_ADJUST_EN_AUX_TX_P0_FLDMASK 0x4
3793
#define TX_GTC_VALUE_PHASE_ADJUST_EN_AUX_TX_P0_FLDMASK_POS 2
3794
#define TX_GTC_VALUE_PHASE_ADJUST_EN_AUX_TX_P0_FLDMASK_LEN 1
3795
3796
#define REG_36DC_AUX_TX_P0 0x36DC
3797
#define TX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK 0xffff
3798
#define TX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK_POS 0
3799
#define TX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK_LEN 16
3800
3801
#define REG_36E0_AUX_TX_P0 0x36E0
3802
#define GTC_STATE_AUX_TX_P0_FLDMASK 0xf
3803
#define GTC_STATE_AUX_TX_P0_FLDMASK_POS 0
3804
#define GTC_STATE_AUX_TX_P0_FLDMASK_LEN 4
3805
3806
#define RX_MASTER_LOCK_ACCQUI_CHKTIME_AUX_TX_P0_FLDMASK 0xf0
3807
#define RX_MASTER_LOCK_ACCQUI_CHKTIME_AUX_TX_P0_FLDMASK_POS 4
3808
#define RX_MASTER_LOCK_ACCQUI_CHKTIME_AUX_TX_P0_FLDMASK_LEN 4
3809
3810
#define FREQ_AUX_TX_P0_FLDMASK 0xff00
3811
#define FREQ_AUX_TX_P0_FLDMASK_POS 8
3812
#define FREQ_AUX_TX_P0_FLDMASK_LEN 8
3813
3814
#define REG_36E4_AUX_TX_P0 0x36E4
3815
#define GTC_TX_1M_ADD_VAL_AUX_TX_P0_FLDMASK 0x3ff
3816
#define GTC_TX_1M_ADD_VAL_AUX_TX_P0_FLDMASK_POS 0
3817
#define GTC_TX_1M_ADD_VAL_AUX_TX_P0_FLDMASK_LEN 10
3818
3819
#define GTC_TX_10M_ADD_VAL_AUX_TX_P0_FLDMASK 0xf000
3820
#define GTC_TX_10M_ADD_VAL_AUX_TX_P0_FLDMASK_POS 12
3821
#define GTC_TX_10M_ADD_VAL_AUX_TX_P0_FLDMASK_LEN 4
3822
3823
#define REG_36E8_AUX_TX_P0 0x36E8
3824
#define CHK_TX_PH_ADJUST_CHK_EN_AUX_TX_P0_FLDMASK 0x1
3825
#define CHK_TX_PH_ADJUST_CHK_EN_AUX_TX_P0_FLDMASK_POS 0
3826
#define CHK_TX_PH_ADJUST_CHK_EN_AUX_TX_P0_FLDMASK_LEN 1
3827
3828
#define TX_SLAVE_WAIT_SKEW_EN_AUX_TX_P0_FLDMASK 0x2
3829
#define TX_SLAVE_WAIT_SKEW_EN_AUX_TX_P0_FLDMASK_POS 1
3830
#define TX_SLAVE_WAIT_SKEW_EN_AUX_TX_P0_FLDMASK_LEN 1
3831
3832
#define GTC_SEND_RCV_EN_AUX_TX_P0_FLDMASK 0x4
3833
#define GTC_SEND_RCV_EN_AUX_TX_P0_FLDMASK_POS 2
3834
#define GTC_SEND_RCV_EN_AUX_TX_P0_FLDMASK_LEN 1
3835
3836
#define AUXTX_HW_ACCS_EN_AUX_TX_P0_FLDMASK 0x8
3837
#define AUXTX_HW_ACCS_EN_AUX_TX_P0_FLDMASK_POS 3
3838
#define AUXTX_HW_ACCS_EN_AUX_TX_P0_FLDMASK_LEN 1
3839
3840
#define GTC_TX_MASTER_EN_AUX_TX_P0_FLDMASK 0x10
3841
#define GTC_TX_MASTER_EN_AUX_TX_P0_FLDMASK_POS 4
3842
#define GTC_TX_MASTER_EN_AUX_TX_P0_FLDMASK_LEN 1
3843
3844
#define GTC_TX_SLAVE_EN_AUX_TX_P0_FLDMASK 0x20
3845
#define GTC_TX_SLAVE_EN_AUX_TX_P0_FLDMASK_POS 5
3846
#define GTC_TX_SLAVE_EN_AUX_TX_P0_FLDMASK_LEN 1
3847
3848
#define OFFSET_TRY_NUM_AUX_TX_P0_FLDMASK 0xf00
3849
#define OFFSET_TRY_NUM_AUX_TX_P0_FLDMASK_POS 8
3850
#define OFFSET_TRY_NUM_AUX_TX_P0_FLDMASK_LEN 4
3851
3852
#define HW_SW_ARBIT_AUX_TX_P0_FLDMASK 0xc000
3853
#define HW_SW_ARBIT_AUX_TX_P0_FLDMASK_POS 14
3854
#define HW_SW_ARBIT_AUX_TX_P0_FLDMASK_LEN 2
3855
3856
#define REG_36EC_AUX_TX_P0 0x36EC
3857
#define GTC_DB_OPTION_AUX_TX_P0_FLDMASK 0x7
3858
#define GTC_DB_OPTION_AUX_TX_P0_FLDMASK_POS 0
3859
#define GTC_DB_OPTION_AUX_TX_P0_FLDMASK_LEN 3
3860
3861
#define TX_SLAVE_CHK_RX_LCK_EN_AUX_TX_P0_FLDMASK 0x8
3862
#define TX_SLAVE_CHK_RX_LCK_EN_AUX_TX_P0_FLDMASK_POS 3
3863
#define TX_SLAVE_CHK_RX_LCK_EN_AUX_TX_P0_FLDMASK_LEN 1
3864
3865
#define GTC_PUL_DELAY_AUX_TX_P0_FLDMASK 0xff00
3866
#define GTC_PUL_DELAY_AUX_TX_P0_FLDMASK_POS 8
3867
#define GTC_PUL_DELAY_AUX_TX_P0_FLDMASK_LEN 8
3868
3869
#define REG_36F0_AUX_TX_P0 0x36F0
3870
#define GTC_TX_LCK_ACQ_SEND_NUM_AUX_TX_P0_FLDMASK 0x1f
3871
#define GTC_TX_LCK_ACQ_SEND_NUM_AUX_TX_P0_FLDMASK_POS 0
3872
#define GTC_TX_LCK_ACQ_SEND_NUM_AUX_TX_P0_FLDMASK_LEN 5
3873
3874
#define REG_3700_AUX_TX_P0 0x3700
3875
#define AUX_PHYWAKE_MODE_AUX_TX_P0_FLDMASK 0x1
3876
#define AUX_PHYWAKE_MODE_AUX_TX_P0_FLDMASK_POS 0
3877
#define AUX_PHYWAKE_MODE_AUX_TX_P0_FLDMASK_LEN 1
3878
3879
#define AUX_PHYWAKE_ONLY_AUX_TX_P0_FLDMASK 0x2
3880
#define AUX_PHYWAKE_ONLY_AUX_TX_P0_FLDMASK_POS 1
3881
#define AUX_PHYWAKE_ONLY_AUX_TX_P0_FLDMASK_LEN 1
3882
3883
#define PHYWAKE_PRE_NUM_AUX_TX_P0_FLDMASK 0x70
3884
#define PHYWAKE_PRE_NUM_AUX_TX_P0_FLDMASK_POS 4
3885
#define PHYWAKE_PRE_NUM_AUX_TX_P0_FLDMASK_LEN 3
3886
3887
#define REG_3704_AUX_TX_P0 0x3704
3888
#define AUX_PHYWAKE_ACK_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK 0x1
3889
#define AUX_PHYWAKE_ACK_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_POS 0
3890
#define AUX_PHYWAKE_ACK_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_LEN 1
3891
3892
#define AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK 0x2
3893
#define AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK_POS 1
3894
#define AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK_LEN 1
3895
3896
#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK 0x4
3897
#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_POS 2
3898
#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_LEN 1
3899
3900
#define REG_3708_AUX_TX_P0 0x3708
3901
#define AUX_TX_FIFO_WRITE_DATA_BYTE0_AUX_TX_P0_FLDMASK 0xff
3902
#define AUX_TX_FIFO_WRITE_DATA_BYTE0_AUX_TX_P0_FLDMASK_POS 0
3903
#define AUX_TX_FIFO_WRITE_DATA_BYTE0_AUX_TX_P0_FLDMASK_LEN 8
3904
3905
#define AUX_TX_FIFO_WRITE_DATA_BYTE1_AUX_TX_P0_FLDMASK 0xff00
3906
#define AUX_TX_FIFO_WRITE_DATA_BYTE1_AUX_TX_P0_FLDMASK_POS 8
3907
#define AUX_TX_FIFO_WRITE_DATA_BYTE1_AUX_TX_P0_FLDMASK_LEN 8
3908
3909
#define REG_370C_AUX_TX_P0 0x370C
3910
#define AUX_TX_FIFO_WRITE_DATA_BYTE2_AUX_TX_P0_FLDMASK 0xff
3911
#define AUX_TX_FIFO_WRITE_DATA_BYTE2_AUX_TX_P0_FLDMASK_POS 0
3912
#define AUX_TX_FIFO_WRITE_DATA_BYTE2_AUX_TX_P0_FLDMASK_LEN 8
3913
3914
#define AUX_TX_FIFO_WRITE_DATA_BYTE3_AUX_TX_P0_FLDMASK 0xff00
3915
#define AUX_TX_FIFO_WRITE_DATA_BYTE3_AUX_TX_P0_FLDMASK_POS 8
3916
#define AUX_TX_FIFO_WRITE_DATA_BYTE3_AUX_TX_P0_FLDMASK_LEN 8
3917
3918
#define REG_3710_AUX_TX_P0 0x3710
3919
#define AUX_TX_FIFO_WRITE_DATA_BYTE4_AUX_TX_P0_FLDMASK 0xff
3920
#define AUX_TX_FIFO_WRITE_DATA_BYTE4_AUX_TX_P0_FLDMASK_POS 0
3921
#define AUX_TX_FIFO_WRITE_DATA_BYTE4_AUX_TX_P0_FLDMASK_LEN 8
3922
3923
#define AUX_TX_FIFO_WRITE_DATA_BYTE5_AUX_TX_P0_FLDMASK 0xff00
3924
#define AUX_TX_FIFO_WRITE_DATA_BYTE5_AUX_TX_P0_FLDMASK_POS 8
3925
#define AUX_TX_FIFO_WRITE_DATA_BYTE5_AUX_TX_P0_FLDMASK_LEN 8
3926
3927
#define REG_3714_AUX_TX_P0 0x3714
3928
#define AUX_TX_FIFO_WRITE_DATA_BYTE6_AUX_TX_P0_FLDMASK 0xff
3929
#define AUX_TX_FIFO_WRITE_DATA_BYTE6_AUX_TX_P0_FLDMASK_POS 0
3930
#define AUX_TX_FIFO_WRITE_DATA_BYTE6_AUX_TX_P0_FLDMASK_LEN 8
3931
3932
#define AUX_TX_FIFO_WRITE_DATA_BYTE7_AUX_TX_P0_FLDMASK 0xff00
3933
#define AUX_TX_FIFO_WRITE_DATA_BYTE7_AUX_TX_P0_FLDMASK_POS 8
3934
#define AUX_TX_FIFO_WRITE_DATA_BYTE7_AUX_TX_P0_FLDMASK_LEN 8
3935
3936
#define REG_3718_AUX_TX_P0 0x3718
3937
#define AUX_TX_FIFO_WRITE_DATA_BYTE8_AUX_TX_P0_FLDMASK 0xff
3938
#define AUX_TX_FIFO_WRITE_DATA_BYTE8_AUX_TX_P0_FLDMASK_POS 0
3939
#define AUX_TX_FIFO_WRITE_DATA_BYTE8_AUX_TX_P0_FLDMASK_LEN 8
3940
3941
#define AUX_TX_FIFO_WRITE_DATA_BYTE9_AUX_TX_P0_FLDMASK 0xff00
3942
#define AUX_TX_FIFO_WRITE_DATA_BYTE9_AUX_TX_P0_FLDMASK_POS 8
3943
#define AUX_TX_FIFO_WRITE_DATA_BYTE9_AUX_TX_P0_FLDMASK_LEN 8
3944
3945
#define REG_371C_AUX_TX_P0 0x371C
3946
#define AUX_TX_FIFO_WRITE_DATA_BYTE10_AUX_TX_P0_FLDMASK 0xff
3947
#define AUX_TX_FIFO_WRITE_DATA_BYTE10_AUX_TX_P0_FLDMASK_POS 0
3948
#define AUX_TX_FIFO_WRITE_DATA_BYTE10_AUX_TX_P0_FLDMASK_LEN 8
3949
3950
#define AUX_TX_FIFO_WRITE_DATA_BYTE11_AUX_TX_P0_FLDMASK 0xff00
3951
#define AUX_TX_FIFO_WRITE_DATA_BYTE11_AUX_TX_P0_FLDMASK_POS 8
3952
#define AUX_TX_FIFO_WRITE_DATA_BYTE11_AUX_TX_P0_FLDMASK_LEN 8
3953
3954
#define REG_3720_AUX_TX_P0 0x3720
3955
#define AUX_TX_FIFO_WRITE_DATA_BYTE12_AUX_TX_P0_FLDMASK 0xff
3956
#define AUX_TX_FIFO_WRITE_DATA_BYTE12_AUX_TX_P0_FLDMASK_POS 0
3957
#define AUX_TX_FIFO_WRITE_DATA_BYTE12_AUX_TX_P0_FLDMASK_LEN 8
3958
3959
#define AUX_TX_FIFO_WRITE_DATA_BYTE13_AUX_TX_P0_FLDMASK 0xff00
3960
#define AUX_TX_FIFO_WRITE_DATA_BYTE13_AUX_TX_P0_FLDMASK_POS 8
3961
#define AUX_TX_FIFO_WRITE_DATA_BYTE13_AUX_TX_P0_FLDMASK_LEN 8
3962
3963
#define REG_3724_AUX_TX_P0 0x3724
3964
#define AUX_TX_FIFO_WRITE_DATA_BYTE14_AUX_TX_P0_FLDMASK 0xff
3965
#define AUX_TX_FIFO_WRITE_DATA_BYTE14_AUX_TX_P0_FLDMASK_POS 0
3966
#define AUX_TX_FIFO_WRITE_DATA_BYTE14_AUX_TX_P0_FLDMASK_LEN 8
3967
3968
#define AUX_TX_FIFO_WRITE_DATA_BYTE15_AUX_TX_P0_FLDMASK 0xff00
3969
#define AUX_TX_FIFO_WRITE_DATA_BYTE15_AUX_TX_P0_FLDMASK_POS 8
3970
#define AUX_TX_FIFO_WRITE_DATA_BYTE15_AUX_TX_P0_FLDMASK_LEN 8
3971
3972
#define REG_3740_AUX_TX_P0 0x3740
3973
#define HPD_OEN_AUX_TX_P0_FLDMASK 0x1
3974
#define HPD_OEN_AUX_TX_P0_FLDMASK_POS 0
3975
#define HPD_OEN_AUX_TX_P0_FLDMASK_LEN 1
3976
3977
#define HPD_I_AUX_TX_P0_FLDMASK 0x2
3978
#define HPD_I_AUX_TX_P0_FLDMASK_POS 1
3979
#define HPD_I_AUX_TX_P0_FLDMASK_LEN 1
3980
3981
#define REG_3744_AUX_TX_P0 0x3744
3982
#define TEST_AUXRX_AUX_TX_P0_FLDMASK 0xffff
3983
#define TEST_AUXRX_AUX_TX_P0_FLDMASK_POS 0
3984
#define TEST_AUXRX_AUX_TX_P0_FLDMASK_LEN 16
3985
3986
#define REG_3748_AUX_TX_P0 0x3748
3987
#define CK_XTAL_AUX_TX_P0_FLDMASK 0x1
3988
#define CK_XTAL_AUX_TX_P0_FLDMASK_POS 0
3989
#define CK_XTAL_AUX_TX_P0_FLDMASK_LEN 1
3990
3991
#define EN_FT_MUX_AUX_TX_P0_FLDMASK 0x2
3992
#define EN_FT_MUX_AUX_TX_P0_FLDMASK_POS 1
3993
#define EN_FT_MUX_AUX_TX_P0_FLDMASK_LEN 1
3994
3995
#define EN_GPIO_AUX_TX_P0_FLDMASK 0x4
3996
#define EN_GPIO_AUX_TX_P0_FLDMASK_POS 2
3997
#define EN_GPIO_AUX_TX_P0_FLDMASK_LEN 1
3998
3999
#define EN_HBR3_AUX_TX_P0_FLDMASK 0x8
4000
#define EN_HBR3_AUX_TX_P0_FLDMASK_POS 3
4001
#define EN_HBR3_AUX_TX_P0_FLDMASK_LEN 1
4002
4003
#define PD_NGATE_OV_AUX_TX_P0_FLDMASK 0x10
4004
#define PD_NGATE_OV_AUX_TX_P0_FLDMASK_POS 4
4005
#define PD_NGATE_OV_AUX_TX_P0_FLDMASK_LEN 1
4006
4007
#define PD_NGATE_OVEN_AUX_TX_P0_FLDMASK 0x20
4008
#define PD_NGATE_OVEN_AUX_TX_P0_FLDMASK_POS 5
4009
#define PD_NGATE_OVEN_AUX_TX_P0_FLDMASK_LEN 1
4010
4011
#define PD_VCM_OP_AUX_TX_P0_FLDMASK 0x40
4012
#define PD_VCM_OP_AUX_TX_P0_FLDMASK_POS 6
4013
#define PD_VCM_OP_AUX_TX_P0_FLDMASK_LEN 1
4014
4015
#define CK_XTAL_SW_AUX_TX_P0_FLDMASK 0x80
4016
#define CK_XTAL_SW_AUX_TX_P0_FLDMASK_POS 7
4017
#define CK_XTAL_SW_AUX_TX_P0_FLDMASK_LEN 1
4018
4019
#define SEL_FTMUX_AUX_TX_P0_FLDMASK 0x300
4020
#define SEL_FTMUX_AUX_TX_P0_FLDMASK_POS 8
4021
#define SEL_FTMUX_AUX_TX_P0_FLDMASK_LEN 2
4022
4023
#define GTC_EN_AUX_TX_P0_FLDMASK 0x400
4024
#define GTC_EN_AUX_TX_P0_FLDMASK_POS 10
4025
#define GTC_EN_AUX_TX_P0_FLDMASK_LEN 1
4026
4027
#define GTC_DATA_IN_MODE_AUX_TX_P0_FLDMASK 0x800
4028
#define GTC_DATA_IN_MODE_AUX_TX_P0_FLDMASK_POS 11
4029
#define GTC_DATA_IN_MODE_AUX_TX_P0_FLDMASK_LEN 1
4030
4031
#define REG_374C_AUX_TX_P0 0x374C
4032
#define AUX_VALID_DB_TH_AUX_TX_P0_FLDMASK 0xf
4033
#define AUX_VALID_DB_TH_AUX_TX_P0_FLDMASK_POS 0
4034
#define AUX_VALID_DB_TH_AUX_TX_P0_FLDMASK_LEN 4
4035
4036
#define CLK_AUX_MUX_VALID_EN_AUX_TX_P0_FLDMASK 0x100
4037
#define CLK_AUX_MUX_VALID_EN_AUX_TX_P0_FLDMASK_POS 8
4038
#define CLK_AUX_MUX_VALID_EN_AUX_TX_P0_FLDMASK_LEN 1
4039
4040
#define CLK_AUX_MUX_VALID_INV_AUX_TX_P0_FLDMASK 0x200
4041
#define CLK_AUX_MUX_VALID_INV_AUX_TX_P0_FLDMASK_POS 9
4042
#define CLK_AUX_MUX_VALID_INV_AUX_TX_P0_FLDMASK_LEN 1
4043
4044
#define CLK_AUX_MUX_VALID_SEL_AUX_TX_P0_FLDMASK 0xc00
4045
#define CLK_AUX_MUX_VALID_SEL_AUX_TX_P0_FLDMASK_POS 10
4046
#define CLK_AUX_MUX_VALID_SEL_AUX_TX_P0_FLDMASK_LEN 2
4047
4048
#define CLK_AUX_MUX_DATA_EN_AUX_TX_P0_FLDMASK 0x1000
4049
#define CLK_AUX_MUX_DATA_EN_AUX_TX_P0_FLDMASK_POS 12
4050
#define CLK_AUX_MUX_DATA_EN_AUX_TX_P0_FLDMASK_LEN 1
4051
4052
#define CLK_AUX_MUX_DATA_INV_AUX_TX_P0_FLDMASK 0x2000
4053
#define CLK_AUX_MUX_DATA_INV_AUX_TX_P0_FLDMASK_POS 13
4054
#define CLK_AUX_MUX_DATA_INV_AUX_TX_P0_FLDMASK_LEN 1
4055
4056
#define CLK_AUX_MUX_DATA_SEL_AUX_TX_P0_FLDMASK 0xc000
4057
#define CLK_AUX_MUX_DATA_SEL_AUX_TX_P0_FLDMASK_POS 14
4058
#define CLK_AUX_MUX_DATA_SEL_AUX_TX_P0_FLDMASK_LEN 2
4059
4060
#define REG_3780_AUX_TX_P0 0x3780
4061
#define AUX_RX_FIFO_DATA0_AUX_TX_P0_FLDMASK 0xff
4062
#define AUX_RX_FIFO_DATA0_AUX_TX_P0_FLDMASK_POS 0
4063
#define AUX_RX_FIFO_DATA0_AUX_TX_P0_FLDMASK_LEN 8
4064
4065
#define AUX_RX_FIFO_DATA1_AUX_TX_P0_FLDMASK 0xff00
4066
#define AUX_RX_FIFO_DATA1_AUX_TX_P0_FLDMASK_POS 8
4067
#define AUX_RX_FIFO_DATA1_AUX_TX_P0_FLDMASK_LEN 8
4068
4069
#define REG_3784_AUX_TX_P0 0x3784
4070
#define AUX_RX_FIFO_DATA2_AUX_TX_P0_FLDMASK 0xff
4071
#define AUX_RX_FIFO_DATA2_AUX_TX_P0_FLDMASK_POS 0
4072
#define AUX_RX_FIFO_DATA2_AUX_TX_P0_FLDMASK_LEN 8
4073
4074
#define AUX_RX_FIFO_DATA3_AUX_TX_P0_FLDMASK 0xff00
4075
#define AUX_RX_FIFO_DATA3_AUX_TX_P0_FLDMASK_POS 8
4076
#define AUX_RX_FIFO_DATA3_AUX_TX_P0_FLDMASK_LEN 8
4077
4078
#define REG_3788_AUX_TX_P0 0x3788
4079
#define AUX_RX_FIFO_DATA4_AUX_TX_P0_FLDMASK 0xff
4080
#define AUX_RX_FIFO_DATA4_AUX_TX_P0_FLDMASK_POS 0
4081
#define AUX_RX_FIFO_DATA4_AUX_TX_P0_FLDMASK_LEN 8
4082
4083
#define AUX_RX_FIFO_DATA5_AUX_TX_P0_FLDMASK 0xff00
4084
#define AUX_RX_FIFO_DATA5_AUX_TX_P0_FLDMASK_POS 8
4085
#define AUX_RX_FIFO_DATA5_AUX_TX_P0_FLDMASK_LEN 8
4086
4087
#define REG_378C_AUX_TX_P0 0x378C
4088
#define AUX_RX_FIFO_DATA6_AUX_TX_P0_FLDMASK 0xff
4089
#define AUX_RX_FIFO_DATA6_AUX_TX_P0_FLDMASK_POS 0
4090
#define AUX_RX_FIFO_DATA6_AUX_TX_P0_FLDMASK_LEN 8
4091
4092
#define AUX_RX_FIFO_DATA7_AUX_TX_P0_FLDMASK 0xff00
4093
#define AUX_RX_FIFO_DATA7_AUX_TX_P0_FLDMASK_POS 8
4094
#define AUX_RX_FIFO_DATA7_AUX_TX_P0_FLDMASK_LEN 8
4095
4096
#define REG_3790_AUX_TX_P0 0x3790
4097
#define AUX_RX_FIFO_DATA8_AUX_TX_P0_FLDMASK 0xff
4098
#define AUX_RX_FIFO_DATA8_AUX_TX_P0_FLDMASK_POS 0
4099
#define AUX_RX_FIFO_DATA8_AUX_TX_P0_FLDMASK_LEN 8
4100
4101
#define AUX_RX_FIFO_DATA9_AUX_TX_P0_FLDMASK 0xff00
4102
#define AUX_RX_FIFO_DATA9_AUX_TX_P0_FLDMASK_POS 8
4103
#define AUX_RX_FIFO_DATA9_AUX_TX_P0_FLDMASK_LEN 8
4104
4105
#define REG_3794_AUX_TX_P0 0x3794
4106
#define AUX_RX_FIFO_DATA10_AUX_TX_P0_FLDMASK 0xff
4107
#define AUX_RX_FIFO_DATA10_AUX_TX_P0_FLDMASK_POS 0
4108
#define AUX_RX_FIFO_DATA10_AUX_TX_P0_FLDMASK_LEN 8
4109
4110
#define AUX_RX_FIFO_DATA11_AUX_TX_P0_FLDMASK 0xff00
4111
#define AUX_RX_FIFO_DATA11_AUX_TX_P0_FLDMASK_POS 8
4112
#define AUX_RX_FIFO_DATA11_AUX_TX_P0_FLDMASK_LEN 8
4113
4114
#define REG_3798_AUX_TX_P0 0x3798
4115
#define AUX_RX_FIFO_DATA12_AUX_TX_P0_FLDMASK 0xff
4116
#define AUX_RX_FIFO_DATA12_AUX_TX_P0_FLDMASK_POS 0
4117
#define AUX_RX_FIFO_DATA12_AUX_TX_P0_FLDMASK_LEN 8
4118
4119
#define AUX_RX_FIFO_DATA13_AUX_TX_P0_FLDMASK 0xff00
4120
#define AUX_RX_FIFO_DATA13_AUX_TX_P0_FLDMASK_POS 8
4121
#define AUX_RX_FIFO_DATA13_AUX_TX_P0_FLDMASK_LEN 8
4122
4123
#define REG_379C_AUX_TX_P0 0x379C
4124
#define AUX_RX_FIFO_DATA14_AUX_TX_P0_FLDMASK 0xff
4125
#define AUX_RX_FIFO_DATA14_AUX_TX_P0_FLDMASK_POS 0
4126
#define AUX_RX_FIFO_DATA14_AUX_TX_P0_FLDMASK_LEN 8
4127
4128
#define AUX_RX_FIFO_DATA15_AUX_TX_P0_FLDMASK 0xff00
4129
#define AUX_RX_FIFO_DATA15_AUX_TX_P0_FLDMASK_POS 8
4130
#define AUX_RX_FIFO_DATA15_AUX_TX_P0_FLDMASK_LEN 8
4131
4132
#define REG_37C0_AUX_TX_P0 0x37C0
4133
#define AUX_DRV_EN_TIME_THRD_AUX_TX_P0_FLDMASK 0x1f
4134
#define AUX_DRV_EN_TIME_THRD_AUX_TX_P0_FLDMASK_POS 0
4135
#define AUX_DRV_EN_TIME_THRD_AUX_TX_P0_FLDMASK_LEN 5
4136
4137
#define AUX_DRV_DIS_TIME_THRD_AUX_TX_P0_FLDMASK 0x1f00
4138
#define AUX_DRV_DIS_TIME_THRD_AUX_TX_P0_FLDMASK_POS 8
4139
#define AUX_DRV_DIS_TIME_THRD_AUX_TX_P0_FLDMASK_LEN 5
4140
4141
#define REG_37C4_AUX_TX_P0 0x37C4
4142
#define AUX_WAIT_TRANSFER_TIME_THRD_AUX_TX_P0_FLDMASK 0xff
4143
#define AUX_WAIT_TRANSFER_TIME_THRD_AUX_TX_P0_FLDMASK_POS 0
4144
#define AUX_WAIT_TRANSFER_TIME_THRD_AUX_TX_P0_FLDMASK_LEN 8
4145
4146
#define AUX_WAIT_RECEIVE_TIME_THRD_AUX_TX_P0_FLDMASK 0xff00
4147
#define AUX_WAIT_RECEIVE_TIME_THRD_AUX_TX_P0_FLDMASK_POS 8
4148
#define AUX_WAIT_RECEIVE_TIME_THRD_AUX_TX_P0_FLDMASK_LEN 8
4149
4150
#define REG_37C8_AUX_TX_P0 0x37C8
4151
#define MTK_ATOP_EN_AUX_TX_P0_FLDMASK 0x1
4152
#define MTK_ATOP_EN_AUX_TX_P0_FLDMASK_POS 0
4153
#define MTK_ATOP_EN_AUX_TX_P0_FLDMASK_LEN 1
4154
4155
/*-----------------------------------------------------*/
4156
#define DP_TX_TOP_PWR_STATE (TOP_OFFSET + 0x00)
4157
#define DP_PWR_STATE_FLDMASK 0x3
4158
#define DP_PWR_STATE_FLDMASK_POS 0
4159
#define DP_PWR_STATE_FLDMASK_LEN 2
4160
4161
#define DP_SCRAMB_EN_FLDMASK 0x4
4162
#define DP_SCRAMB_EN_FLDMASK_POS 2
4163
#define DP_SCRAMB_EN_FLDMASK_LEN 1
4164
4165
#define DP_DISP_RST_FLDMASK 0x8
4166
#define DP_DISP_RST_FLDMASK_POS 3
4167
#define DP_DISP_RST_FLDMASK_LEN 1
4168
4169
#define DP_TX_TOP_SWING_EMP (TOP_OFFSET + 0x04)
4170
#define DP_TX0_VOLT_SWING_FLDMASK 0x3
4171
#define DP_TX0_VOLT_SWING_FLDMASK_POS 0
4172
#define DP_TX0_VOLT_SWING_FLDMASK_LEN 2
4173
4174
#define DP_TX0_PRE_EMPH_FLDMASK 0xc
4175
#define DP_TX0_PRE_EMPH_FLDMASK_POS 2
4176
#define DP_TX0_PRE_EMPH_FLDMASK_LEN 2
4177
4178
#define DP_TX0_DATAK_FLDMASK 0xf0
4179
#define DP_TX0_DATAK_FLDMASK_POS 4
4180
#define DP_TX0_DATAK_FLDMASK_LEN 4
4181
4182
#define DP_TX1_VOLT_SWING_FLDMASK 0x300
4183
#define DP_TX1_VOLT_SWING_FLDMASK_POS 8
4184
#define DP_TX1_VOLT_SWING_FLDMASK_LEN 2
4185
4186
#define DP_TX1_PRE_EMPH_FLDMASK 0xc00
4187
#define DP_TX1_PRE_EMPH_FLDMASK_POS 10
4188
#define DP_TX1_PRE_EMPH_FLDMASK_LEN 2
4189
4190
#define DP_TX1_DATAK_FLDMASK 0xf000
4191
#define DP_TX1_DATAK_FLDMASK_POS 12
4192
#define DP_TX1_DATAK_FLDMASK_LEN 4
4193
4194
#define DP_TX2_VOLT_SWING_FLDMASK 0x30000
4195
#define DP_TX2_VOLT_SWING_FLDMASK_POS 16
4196
#define DP_TX2_VOLT_SWING_FLDMASK_LEN 2
4197
4198
#define DP_TX2_PRE_EMPH_FLDMASK 0xc0000
4199
#define DP_TX2_PRE_EMPH_FLDMASK_POS 18
4200
#define DP_TX2_PRE_EMPH_FLDMASK_LEN 2
4201
4202
#define DP_TX2_DATAK_FLDMASK 0xf00000
4203
#define DP_TX2_DATAK_FLDMASK_POS 20
4204
#define DP_TX2_DATAK_FLDMASK_LEN 4
4205
4206
#define DP_TX3_VOLT_SWING_FLDMASK 0x3000000
4207
#define DP_TX3_VOLT_SWING_FLDMASK_POS 24
4208
#define DP_TX3_VOLT_SWING_FLDMASK_LEN 2
4209
4210
#define DP_TX3_PRE_EMPH_FLDMASK 0xc000000
4211
#define DP_TX3_PRE_EMPH_FLDMASK_POS 26
4212
#define DP_TX3_PRE_EMPH_FLDMASK_LEN 2
4213
4214
#define DP_TX3_DATAK_FLDMASK 0xf0000000L
4215
#define DP_TX3_DATAK_FLDMASK_POS 28
4216
#define DP_TX3_DATAK_FLDMASK_LEN 4
4217
4218
#define DP_TX_TOP_APB_WSTRB (TOP_OFFSET + 0x10)
4219
#define APB_WSTRB_FLDMASK 0xf
4220
#define APB_WSTRB_FLDMASK_POS 0
4221
#define APB_WSTRB_FLDMASK_LEN 4
4222
4223
#define APB_WSTRB_EN_FLDMASK 0x10
4224
#define APB_WSTRB_EN_FLDMASK_POS 4
4225
#define APB_WSTRB_EN_FLDMASK_LEN 1
4226
4227
#define DP_TX_TOP_RESERVED (TOP_OFFSET + 0x14)
4228
#define RESERVED_FLDMASK 0xffffffffL
4229
#define RESERVED_FLDMASK_POS 0
4230
#define RESERVED_FLDMASK_LEN 32
4231
4232
#define DP_TX_TOP_RESET_AND_PROBE (TOP_OFFSET + 0x20)
4233
#define SW_RST_B_FLDMASK 0x1f
4234
#define SW_RST_B_FLDMASK_POS 0
4235
#define SW_RST_B_FLDMASK_LEN 5
4236
4237
#define PROBE_LOW_SEL_FLDMASK 0x38000
4238
#define PROBE_LOW_SEL_FLDMASK_POS 15
4239
#define PROBE_LOW_SEL_FLDMASK_LEN 3
4240
4241
#define PROBE_HIGH_SEL_FLDMASK 0x1c0000
4242
#define PROBE_HIGH_SEL_FLDMASK_POS 18
4243
#define PROBE_HIGH_SEL_FLDMASK_LEN 3
4244
4245
#define PROBE_LOW_HIGH_SWAP_FLDMASK 0x200000
4246
#define PROBE_LOW_HIGH_SWAP_FLDMASK_POS 21
4247
#define PROBE_LOW_HIGH_SWAP_FLDMASK_LEN 1
4248
4249
#define DP_TX_TOP_SOFT_PROBE (TOP_OFFSET + 0x24)
4250
#define SW_PROBE_VALUE_FLDMASK 0xffffffffL
4251
#define SW_PROBE_VALUE_FLDMASK_POS 0
4252
#define SW_PROBE_VALUE_FLDMASK_LEN 32
4253
4254
#define DP_TX_TOP_IRQ_STATUS (TOP_OFFSET + 0x28)
4255
#define RGS_IRQ_STATUS_FLDMASK 0x7
4256
#define RGS_IRQ_STATUS_FLDMASK_POS 0
4257
#define RGS_IRQ_STATUS_FLDMASK_LEN 3
4258
4259
#define DP_TX_TOP_IRQ_MASK (TOP_OFFSET + 0x2C)
4260
#define IRQ_MASK_FLDMASK 0x7
4261
#define IRQ_MASK_FLDMASK_POS 0
4262
#define IRQ_MASK_FLDMASK_LEN 3
4263
4264
#define IRQ_OUT_HIGH_ACTIVE_FLDMASK 0x100
4265
#define IRQ_OUT_HIGH_ACTIVE_FLDMASK_POS 8
4266
#define IRQ_OUT_HIGH_ACTIVE_FLDMASK_LEN 1
4267
4268
#define DP_TX_TOP_BLACK_SCREEN (TOP_OFFSET + 0x30)
4269
#define BLACK_SCREEN_ENABLE_FLDMASK 0x1
4270
#define BLACK_SCREEN_ENABLE_FLDMASK_POS 0
4271
#define BLACK_SCREEN_ENABLE_FLDMASK_LEN 1
4272
4273
#define DP_TX_TOP_MEM_PD (TOP_OFFSET + 0x38)
4274
#define MEM_ISO_EN_FLDMASK 0x1
4275
#define MEM_ISO_EN_FLDMASK_POS 0
4276
#define MEM_ISO_EN_FLDMASK_LEN 1
4277
4278
#define MEM_PD_FLDMASK 0x2
4279
#define MEM_PD_FLDMASK_POS 1
4280
#define MEM_PD_FLDMASK_LEN 1
4281
4282
#define FUSE_SEL_FLDMASK 0x4
4283
#define FUSE_SEL_FLDMASK_POS 2
4284
#define FUSE_SEL_FLDMASK_LEN 1
4285
4286
#define LOAD_PREFUSE_FLDMASK 0x8
4287
#define LOAD_PREFUSE_FLDMASK_POS 3
4288
#define LOAD_PREFUSE_FLDMASK_LEN 1
4289
4290
#define DP_TX_TOP_MBIST_PREFUSE (TOP_OFFSET + 0x3C)
4291
#define RGS_PREFUSE_FLDMASK 0xffff
4292
#define RGS_PREFUSE_FLDMASK_POS 0
4293
#define RGS_PREFUSE_FLDMASK_LEN 16
4294
4295
#define DP_TX_TOP_MEM_DELSEL_0 (TOP_OFFSET + 0x40)
4296
#define DELSEL_0_FLDMASK 0xfffff
4297
#define DELSEL_0_FLDMASK_POS 0
4298
#define DELSEL_0_FLDMASK_LEN 20
4299
4300
#define USE_DEFAULT_DELSEL_0_FLDMASK 0x100000
4301
#define USE_DEFAULT_DELSEL_0_FLDMASK_POS 20
4302
#define USE_DEFAULT_DELSEL_0_FLDMASK_LEN 1
4303
4304
#define DP_TX_TOP_MEM_DELSEL_1 (TOP_OFFSET + 0x44)
4305
#define DELSEL_1_FLDMASK 0xfffff
4306
#define DELSEL_1_FLDMASK_POS 0
4307
#define DELSEL_1_FLDMASK_LEN 20
4308
4309
#define USE_DEFAULT_DELSEL_1_FLDMASK 0x100000
4310
#define USE_DEFAULT_DELSEL_1_FLDMASK_POS 20
4311
#define USE_DEFAULT_DELSEL_1_FLDMASK_LEN 1
4312
4313
#define DP_TX_TOP_MEM_DELSEL_2 (TOP_OFFSET + 0x48)
4314
#define DELSEL_2_FLDMASK 0xfffff
4315
#define DELSEL_2_FLDMASK_POS 0
4316
#define DELSEL_2_FLDMASK_LEN 20
4317
4318
#define USE_DEFAULT_DELSEL_2_FLDMASK 0x100000
4319
#define USE_DEFAULT_DELSEL_2_FLDMASK_POS 20
4320
#define USE_DEFAULT_DELSEL_2_FLDMASK_LEN 1
4321
4322
#define DP_TX_TOP_MEM_DELSEL_3 (TOP_OFFSET + 0x4C)
4323
#define DELSEL_3_FLDMASK 0xfffff
4324
#define DELSEL_3_FLDMASK_POS 0
4325
#define DELSEL_3_FLDMASK_LEN 20
4326
4327
#define USE_DEFAULT_DELSEL_3_FLDMASK 0x100000
4328
#define USE_DEFAULT_DELSEL_3_FLDMASK_POS 20
4329
#define USE_DEFAULT_DELSEL_3_FLDMASK_LEN 1
4330
4331
#define DP_TX_TOP_MEM_DELSEL_4 (TOP_OFFSET + 0x50)
4332
#define DELSEL_4_FLDMASK 0xfffff
4333
#define DELSEL_4_FLDMASK_POS 0
4334
#define DELSEL_4_FLDMASK_LEN 20
4335
4336
#define USE_DEFAULT_DELSEL_4_FLDMASK 0x100000
4337
#define USE_DEFAULT_DELSEL_4_FLDMASK_POS 20
4338
#define USE_DEFAULT_DELSEL_4_FLDMASK_LEN 1
4339
4340
#define DP_TX_TOP_MEM_DELSEL_5 (TOP_OFFSET + 0x54)
4341
#define DELSEL_5_FLDMASK 0xfffff
4342
#define DELSEL_5_FLDMASK_POS 0
4343
#define DELSEL_5_FLDMASK_LEN 20
4344
4345
#define USE_DEFAULT_DELSEL_5_FLDMASK 0x100000
4346
#define USE_DEFAULT_DELSEL_5_FLDMASK_POS 20
4347
#define USE_DEFAULT_DELSEL_5_FLDMASK_LEN 1
4348
4349
#define DP_TX_TOP_MEM_DELSEL_6 (TOP_OFFSET + 0x58)
4350
#define DELSEL_6_FLDMASK 0xfffff
4351
#define DELSEL_6_FLDMASK_POS 0
4352
#define DELSEL_6_FLDMASK_LEN 20
4353
4354
#define USE_DEFAULT_DELSEL_6_FLDMASK 0x100000
4355
#define USE_DEFAULT_DELSEL_6_FLDMASK_POS 20
4356
#define USE_DEFAULT_DELSEL_6_FLDMASK_LEN 1
4357
4358
#define DP_TX_TOP_MEM_DELSEL_7 (TOP_OFFSET + 0x5C)
4359
#define DELSEL_7_FLDMASK 0xfffff
4360
#define DELSEL_7_FLDMASK_POS 0
4361
#define DELSEL_7_FLDMASK_LEN 20
4362
4363
#define USE_DEFAULT_DELSEL_7_FLDMASK 0x100000
4364
#define USE_DEFAULT_DELSEL_7_FLDMASK_POS 20
4365
#define USE_DEFAULT_DELSEL_7_FLDMASK_LEN 1
4366
4367
#define DP_TX_TOP_MEM_DELSEL_8 (TOP_OFFSET + 0x60)
4368
#define DELSEL_8_FLDMASK 0xfffff
4369
#define DELSEL_8_FLDMASK_POS 0
4370
#define DELSEL_8_FLDMASK_LEN 20
4371
4372
#define USE_DEFAULT_DELSEL_8_FLDMASK 0x100000
4373
#define USE_DEFAULT_DELSEL_8_FLDMASK_POS 20
4374
#define USE_DEFAULT_DELSEL_8_FLDMASK_LEN 1
4375
4376
#define DP_TX_TOP_MEM_DELSEL_9 (TOP_OFFSET + 0x64)
4377
#define DELSEL_9_FLDMASK 0xfffff
4378
#define DELSEL_9_FLDMASK_POS 0
4379
#define DELSEL_9_FLDMASK_LEN 20
4380
4381
#define USE_DEFAULT_DELSEL_9_FLDMASK 0x100000
4382
#define USE_DEFAULT_DELSEL_9_FLDMASK_POS 20
4383
#define USE_DEFAULT_DELSEL_9_FLDMASK_LEN 1
4384
4385
#define DP_TX_TOP_MEM_DELSEL_10 (TOP_OFFSET + 0x68)
4386
#define DELSEL_10_FLDMASK 0xfffff
4387
#define DELSEL_10_FLDMASK_POS 0
4388
#define DELSEL_10_FLDMASK_LEN 20
4389
4390
#define USE_DEFAULT_DELSEL_10_FLDMASK 0x100000
4391
#define USE_DEFAULT_DELSEL_10_FLDMASK_POS 20
4392
#define USE_DEFAULT_DELSEL_10_FLDMASK_LEN 1
4393
4394
#define DP_TX_TOP_MEM_DELSEL_11 (TOP_OFFSET + 0x6C)
4395
#define DELSEL_11_FLDMASK 0xfffff
4396
#define DELSEL_11_FLDMASK_POS 0
4397
#define DELSEL_11_FLDMASK_LEN 20
4398
4399
#define USE_DEFAULT_DELSEL_11_FLDMASK 0x100000
4400
#define USE_DEFAULT_DELSEL_11_FLDMASK_POS 20
4401
#define USE_DEFAULT_DELSEL_11_FLDMASK_LEN 1
4402
4403
#define DP_TX_TOP_MEM_DELSEL_12 (TOP_OFFSET + 0x70)
4404
#define DELSEL_12_FLDMASK 0xfffff
4405
#define DELSEL_12_FLDMASK_POS 0
4406
#define DELSEL_12_FLDMASK_LEN 20
4407
4408
#define USE_DEFAULT_DELSEL_12_FLDMASK 0x100000
4409
#define USE_DEFAULT_DELSEL_12_FLDMASK_POS 20
4410
#define USE_DEFAULT_DELSEL_12_FLDMASK_LEN 1
4411
4412
#define DP_TX_TOP_PWR_ACK (TOP_OFFSET + 0x80)
4413
#define RGS_DP_TX_PWR_ACK_FLDMASK 0x1
4414
#define RGS_DP_TX_PWR_ACK_FLDMASK_POS 0
4415
#define RGS_DP_TX_PWR_ACK_FLDMASK_LEN 1
4416
4417
#define RGS_DP_TX_PWR_ACK_2ND_FLDMASK 0x2
4418
#define RGS_DP_TX_PWR_ACK_2ND_FLDMASK_POS 1
4419
#define RGS_DP_TX_PWR_ACK_2ND_FLDMASK_LEN 1
4420
4421
#define DP_TX_SECURE_REG0 (SEC_OFFSET + 0x00)
4422
#define HDCP22_KS_XOR_LC128_KEY_0_FLDMASK 0xffffffffL
4423
#define HDCP22_KS_XOR_LC128_KEY_0_FLDMASK_POS 0
4424
#define HDCP22_KS_XOR_LC128_KEY_0_FLDMASK_LEN 32
4425
4426
#define DP_TX_SECURE_REG1 (SEC_OFFSET + 0x04)
4427
#define HDCP22_KS_XOR_LC128_KEY_1_FLDMASK 0xffffffffL
4428
#define HDCP22_KS_XOR_LC128_KEY_1_FLDMASK_POS 0
4429
#define HDCP22_KS_XOR_LC128_KEY_1_FLDMASK_LEN 32
4430
4431
#define DP_TX_SECURE_REG2 (SEC_OFFSET + 0x08)
4432
#define HDCP22_KS_XOR_LC128_KEY_2_FLDMASK 0xffffffffL
4433
#define HDCP22_KS_XOR_LC128_KEY_2_FLDMASK_POS 0
4434
#define HDCP22_KS_XOR_LC128_KEY_2_FLDMASK_LEN 32
4435
4436
#define DP_TX_SECURE_REG3 (SEC_OFFSET + 0x0c)
4437
#define HDCP22_KS_XOR_LC128_KEY_3_FLDMASK 0xffffffffL
4438
#define HDCP22_KS_XOR_LC128_KEY_3_FLDMASK_POS 0
4439
#define HDCP22_KS_XOR_LC128_KEY_3_FLDMASK_LEN 32
4440
4441
#define DP_TX_SECURE_REG4 (SEC_OFFSET + 0x10)
4442
#define HDCP22_RIV_0_FLDMASK 0xffffffffL
4443
#define HDCP22_RIV_0_FLDMASK_POS 0
4444
#define HDCP22_RIV_0_FLDMASK_LEN 32
4445
4446
#define DP_TX_SECURE_REG5 (SEC_OFFSET + 0x14)
4447
#define HDCP22_RIV_1_FLDMASK 0xffffffffL
4448
#define HDCP22_RIV_1_FLDMASK_POS 0
4449
#define HDCP22_RIV_1_FLDMASK_LEN 32
4450
4451
#define DP_TX_SECURE_REG6 (SEC_OFFSET + 0x18)
4452
#define HDCP13_LN_SEED_FLDMASK 0xff
4453
#define HDCP13_LN_SEED_FLDMASK_POS 0
4454
#define HDCP13_LN_SEED_FLDMASK_LEN 8
4455
4456
#define DP_TX_SECURE_REG7 (SEC_OFFSET + 0x1C)
4457
#define HDCP13_LN_CODE_0_FLDMASK 0xffffffffL
4458
#define HDCP13_LN_CODE_0_FLDMASK_POS 0
4459
#define HDCP13_LN_CODE_0_FLDMASK_LEN 32
4460
4461
#define DP_TX_SECURE_REG8 (SEC_OFFSET + 0x20)
4462
#define HDCP13_LN_CODE_1_FLDMASK 0xffffff
4463
#define HDCP13_LN_CODE_1_FLDMASK_POS 0
4464
#define HDCP13_LN_CODE_1_FLDMASK_LEN 24
4465
4466
#define DP_TX_SECURE_REG9 (SEC_OFFSET + 0x24)
4467
#define HDCP13_AN_CODE_0_FLDMASK 0xffffffffL
4468
#define HDCP13_AN_CODE_0_FLDMASK_POS 0
4469
#define HDCP13_AN_CODE_0_FLDMASK_LEN 32
4470
4471
#define DP_TX_SECURE_REG10 (SEC_OFFSET + 0x28)
4472
#define HDCP13_AN_CODE_1_FLDMASK 0xffffffffL
4473
#define HDCP13_AN_CODE_1_FLDMASK_POS 0
4474
#define HDCP13_AN_CODE_1_FLDMASK_LEN 32
4475
4476
#define DP_TX_SECURE_REG11 (SEC_OFFSET + 0x2C)
4477
#define DP_TX_TRANSMITTER_4P_RESET_SW_SECURE_FLDMASK 0x1
4478
#define DP_TX_TRANSMITTER_4P_RESET_SW_SECURE_FLDMASK_POS 0
4479
#define DP_TX_TRANSMITTER_4P_RESET_SW_SECURE_FLDMASK_LEN 1
4480
4481
#define HDCP22_RST_SW_SECURE_FLDMASK 0x2
4482
#define HDCP22_RST_SW_SECURE_FLDMASK_POS 1
4483
#define HDCP22_RST_SW_SECURE_FLDMASK_LEN 1
4484
4485
#define HDCP13_RST_SW_SECURE_FLDMASK 0x4
4486
#define HDCP13_RST_SW_SECURE_FLDMASK_POS 2
4487
#define HDCP13_RST_SW_SECURE_FLDMASK_LEN 1
4488
4489
#define VIDEO_MUTE_SW_SECURE_FLDMASK 0x8
4490
#define VIDEO_MUTE_SW_SECURE_FLDMASK_POS 3
4491
#define VIDEO_MUTE_SW_SECURE_FLDMASK_LEN 1
4492
4493
#define VIDEO_MUTE_SEL_SECURE_FLDMASK 0x10
4494
#define VIDEO_MUTE_SEL_SECURE_FLDMASK_POS 4
4495
#define VIDEO_MUTE_SEL_SECURE_FLDMASK_LEN 1
4496
4497
#define HDCP_FRAME_EN_SECURE_FLDMASK 0x20
4498
#define HDCP_FRAME_EN_SECURE_FLDMASK_POS 5
4499
#define HDCP_FRAME_EN_SECURE_FLDMASK_LEN 1
4500
4501
#define HDCP_FRAME_EN_SEL_SECURE_FLDMASK 0x40
4502
#define HDCP_FRAME_EN_SEL_SECURE_FLDMASK_POS 6
4503
#define HDCP_FRAME_EN_SEL_SECURE_FLDMASK_LEN 1
4504
4505
#define VSC_SEL_SECURE_FLDMASK 0x80
4506
#define VSC_SEL_SECURE_FLDMASK_POS 7
4507
#define VSC_SEL_SECURE_FLDMASK_LEN 1
4508
4509
#define VSC_DATA_TOGGLE_VESA_SECURE_FLDMASK 0x100
4510
#define VSC_DATA_TOGGLE_VESA_SECURE_FLDMASK_POS 8
4511
#define VSC_DATA_TOGGLE_VESA_SECURE_FLDMASK_LEN 1
4512
4513
#define VSC_DATA_RDY_VESA_SECURE_FLDMASK 0x200
4514
#define VSC_DATA_RDY_VESA_SECURE_FLDMASK_POS 9
4515
#define VSC_DATA_RDY_VESA_SECURE_FLDMASK_LEN 1
4516
4517
#define VSC_DATA_TOGGLE_CEA_SECURE_FLDMASK 0x400
4518
#define VSC_DATA_TOGGLE_CEA_SECURE_FLDMASK_POS 10
4519
#define VSC_DATA_TOGGLE_CEA_SECURE_FLDMASK_LEN 1
4520
4521
#define VSC_DATA_RDY_CEA_SECURE_FLDMASK 0x800
4522
#define VSC_DATA_RDY_CEA_SECURE_FLDMASK_POS 11
4523
#define VSC_DATA_RDY_CEA_SECURE_FLDMASK_LEN 1
4524
4525
#define DP_TX_SECURE_REG12 (SEC_OFFSET + 0x30)
4526
#define VSC_DATA_BYTE7_CEA_SECURE_FLDMASK 0xff000000L
4527
#define VSC_DATA_BYTE7_CEA_SECURE_FLDMASK_POS 24
4528
#define VSC_DATA_BYTE7_CEA_SECURE_FLDMASK_LEN 8
4529
4530
#define VSC_DATA_BYTE6_CEA_SECURE_FLDMASK 0xff0000
4531
#define VSC_DATA_BYTE6_CEA_SECURE_FLDMASK_POS 16
4532
#define VSC_DATA_BYTE6_CEA_SECURE_FLDMASK_LEN 8
4533
4534
#define VSC_DATA_BYTE5_CEA_SECURE_FLDMASK 0xff00
4535
#define VSC_DATA_BYTE5_CEA_SECURE_FLDMASK_POS 8
4536
#define VSC_DATA_BYTE5_CEA_SECURE_FLDMASK_LEN 8
4537
4538
#define VSC_DATA_BYTE4_CEA_SECURE_FLDMASK 0xff
4539
#define VSC_DATA_BYTE4_CEA_SECURE_FLDMASK_POS 0
4540
#define VSC_DATA_BYTE4_CEA_SECURE_FLDMASK_LEN 8
4541
4542
#define DP_TX_SECURE_REG13 (SEC_OFFSET + 0x34)
4543
#define VSC_DATA_BYTE3_CEA_SECURE_FLDMASK 0xff000000L
4544
#define VSC_DATA_BYTE3_CEA_SECURE_FLDMASK_POS 24
4545
#define VSC_DATA_BYTE3_CEA_SECURE_FLDMASK_LEN 8
4546
4547
#define VSC_DATA_BYTE2_CEA_SECURE_FLDMASK 0xff0000
4548
#define VSC_DATA_BYTE2_CEA_SECURE_FLDMASK_POS 16
4549
#define VSC_DATA_BYTE2_CEA_SECURE_FLDMASK_LEN 8
4550
4551
#define VSC_DATA_BYTE1_CEA_SECURE_FLDMASK 0xff00
4552
#define VSC_DATA_BYTE1_CEA_SECURE_FLDMASK_POS 8
4553
#define VSC_DATA_BYTE1_CEA_SECURE_FLDMASK_LEN 8
4554
4555
#define VSC_DATA_BYTE0_CEA_SECURE_FLDMASK 0xff
4556
#define VSC_DATA_BYTE0_CEA_SECURE_FLDMASK_POS 0
4557
#define VSC_DATA_BYTE0_CEA_SECURE_FLDMASK_LEN 8
4558
4559
#define DP_TX_SECURE_REG14 (SEC_OFFSET + 0x38)
4560
#define VSC_DATA_BYTE7_VESA_SECURE_FLDMASK 0xff000000L
4561
#define VSC_DATA_BYTE7_VESA_SECURE_FLDMASK_POS 24
4562
#define VSC_DATA_BYTE7_VESA_SECURE_FLDMASK_LEN 8
4563
4564
#define VSC_DATA_BYTE6_VESA_SECURE_FLDMASK 0xff0000
4565
#define VSC_DATA_BYTE6_VESA_SECURE_FLDMASK_POS 16
4566
#define VSC_DATA_BYTE6_VESA_SECURE_FLDMASK_LEN 8
4567
4568
#define VSC_DATA_BYTE5_VESA_SECURE_FLDMASK 0xff00
4569
#define VSC_DATA_BYTE5_VESA_SECURE_FLDMASK_POS 8
4570
#define VSC_DATA_BYTE5_VESA_SECURE_FLDMASK_LEN 8
4571
4572
#define VSC_DATA_BYTE4_VESA_SECURE_FLDMASK 0xff
4573
#define VSC_DATA_BYTE4_VESA_SECURE_FLDMASK_POS 0
4574
#define VSC_DATA_BYTE4_VESA_SECURE_FLDMASK_LEN 8
4575
4576
#define DP_TX_SECURE_REG15 (SEC_OFFSET + 0x3C)
4577
#define VSC_DATA_BYTE3_VESA_SECURE_FLDMASK 0xff000000L
4578
#define VSC_DATA_BYTE3_VESA_SECURE_FLDMASK_POS 24
4579
#define VSC_DATA_BYTE3_VESA_SECURE_FLDMASK_LEN 8
4580
4581
#define VSC_DATA_BYTE2_VESA_SECURE_FLDMASK 0xff0000
4582
#define VSC_DATA_BYTE2_VESA_SECURE_FLDMASK_POS 16
4583
#define VSC_DATA_BYTE2_VESA_SECURE_FLDMASK_LEN 8
4584
4585
#define VSC_DATA_BYTE1_VESA_SECURE_FLDMASK 0xff00
4586
#define VSC_DATA_BYTE1_VESA_SECURE_FLDMASK_POS 8
4587
#define VSC_DATA_BYTE1_VESA_SECURE_FLDMASK_LEN 8
4588
4589
#define VSC_DATA_BYTE0_VESA_SECURE_FLDMASK 0xff
4590
#define VSC_DATA_BYTE0_VESA_SECURE_FLDMASK_POS 0
4591
#define VSC_DATA_BYTE0_VESA_SECURE_FLDMASK_LEN 8
4592
4593
#define DP_TX_SECURE_STATUS_0 (SEC_OFFSET + 0x80)
4594
#define RGS_DP_TX_HDCP13_HDCP_AN_0_FLDMASK 0xffffffffL
4595
#define RGS_DP_TX_HDCP13_HDCP_AN_0_FLDMASK_POS 0
4596
#define RGS_DP_TX_HDCP13_HDCP_AN_0_FLDMASK_LEN 32
4597
4598
#define DP_TX_SECURE_STATUS_1 (SEC_OFFSET + 0x84)
4599
#define RGS_DP_TX_HDCP13_HDCP_AN_1_FLDMASK 0xffffffffL
4600
#define RGS_DP_TX_HDCP13_HDCP_AN_1_FLDMASK_POS 0
4601
#define RGS_DP_TX_HDCP13_HDCP_AN_1_FLDMASK_LEN 32
4602
4603
#define DP_TX_SECURE_STATUS_2 (SEC_OFFSET + 0x88)
4604
#define RGS_DP_TX_HDCP13_HDCP_R0_FLDMASK 0xffff
4605
#define RGS_DP_TX_HDCP13_HDCP_R0_FLDMASK_POS 0
4606
#define RGS_DP_TX_HDCP13_HDCP_R0_FLDMASK_LEN 16
4607
4608
#define DP_TX_SECURE_STATUS_3 (SEC_OFFSET + 0x8C)
4609
#define RGS_DP_TX_HDCP13_HDCP_M0_0_FLDMASK 0xffffffffL
4610
#define RGS_DP_TX_HDCP13_HDCP_M0_0_FLDMASK_POS 0
4611
#define RGS_DP_TX_HDCP13_HDCP_M0_0_FLDMASK_LEN 32
4612
4613
#define DP_TX_SECURE_STATUS_4 (SEC_OFFSET + 0x90)
4614
#define RGS_DP_TX_HDCP13_HDCP_M0_1_FLDMASK 0xffffffffL
4615
#define RGS_DP_TX_HDCP13_HDCP_M0_1_FLDMASK_POS 0
4616
#define RGS_DP_TX_HDCP13_HDCP_M0_1_FLDMASK_LEN 32
4617
4618
#define DP_TX_SECURE_ACC_FAIL (SEC_OFFSET + 0xf0)
4619
#define NO_AUTH_READ_VALUE_FLDMASK 0xffffffffL
4620
#define NO_AUTH_READ_VALUE_FLDMASK_POS 0
4621
#define NO_AUTH_READ_VALUE_FLDMASK_LEN 32
4622
4623
#define DPCD_00000 0x00000
4624
#define DPCD_00001 0x00001
4625
#define DPCD_00002 0x00002
4626
#define DPCD_00003 0x00003
4627
#define DPCD_00004 0x00004
4628
#define DPCD_00005 0x00005
4629
#define DPCD_0000A 0x0000A
4630
#define DPCD_0000E 0x0000E
4631
#define DPCD_00021 0x00021
4632
#define DPCD_00030 0x00030
4633
#define DPCD_00060 0x00060
4634
#define DPCD_00080 0x00080
4635
#define DPCD_00090 0x00090
4636
#define DPCD_00100 0x00100
4637
#define DPCD_00101 0x00101
4638
#define DPCD_00102 0x00102
4639
#define DPCD_00103 0x00103
4640
#define DPCD_00104 0x00104
4641
#define DPCD_00105 0x00105
4642
#define DPCD_00106 0x00106
4643
#define DPCD_00107 0x00107
4644
#define DPCD_00111 0x00111
4645
#define DPCD_00120 0x00120
4646
#define DPCD_00160 0x00160
4647
#define DPCD_001A1 0x001A1
4648
#define DPCD_001C0 0x001C0
4649
#define DPCD_00200 0x00200
4650
#define DPCD_00201 0x00201
4651
#define DPCD_00202 0x00202
4652
#define DPCD_00203 0x00203
4653
#define DPCD_00204 0x00204
4654
#define DPCD_00205 0x00205
4655
#define DPCD_00206 0x00206
4656
#define DPCD_00210 0x00210
4657
#define DPCD_00218 0x00218
4658
#define DPCD_00219 0x00219
4659
#define DPCD_00220 0x00220
4660
#define DPCD_00230 0x00230
4661
#define DPCD_00250 0x00250
4662
#define DPCD_00260 0x00260
4663
#define DPCD_00261 0x00261
4664
#define DPCD_00271 0x00271
4665
#define DPCD_00280 0x00280
4666
#define DPCD_00281 0x00281
4667
#define DPCD_00282 0x00282
4668
#define DPCD_002C0 0x002C0
4669
#define DPCD_00600 0x00600
4670
#define DPCD_01000 0x01000
4671
#define DPCD_01200 0x01200
4672
#define DPCD_01400 0x01400
4673
#define DPCD_01600 0x01600
4674
#define DPCD_02002 0x02002
4675
#define DPCD_02003 0x02003
4676
#define DPCD_0200C 0x0200C
4677
#define DPCD_0200D 0x0200D
4678
#define DPCD_0200E 0x0200E
4679
#define DPCD_0200F 0x0200F
4680
#define DPCD_02200 0x02200
4681
#define DPCD_02201 0x02201
4682
#define DPCD_02202 0x02202
4683
#define DPCD_02203 0x02203
4684
#define DPCD_02204 0x02204
4685
#define DPCD_02205 0x02205
4686
#define DPCD_02206 0x02206
4687
#define DPCD_02207 0x02207
4688
#define DPCD_02208 0x02208
4689
#define DPCD_02209 0x02209
4690
#define DPCD_0220A 0x0220A
4691
#define DPCD_0220B 0x0220B
4692
#define DPCD_0220C 0x0220C
4693
#define DPCD_0220D 0x0220D
4694
#define DPCD_0220E 0x0220E
4695
#define DPCD_0220F 0x0220F
4696
#define DPCD_02210 0x02210
4697
#define DPCD_02211 0x02211
4698
#define DPCD_68000 0x68000
4699
#define DPCD_68005 0x68005
4700
#define DPCD_68007 0x68007
4701
#define DPCD_6800C 0x6800C
4702
#define DPCD_68014 0x68014
4703
#define DPCD_68018 0x68018
4704
#define DPCD_6801C 0x6801C
4705
#define DPCD_68020 0x68020
4706
#define DPCD_68024 0x68024
4707
#define DPCD_68028 0x68028
4708
#define DPCD_68029 0x68029
4709
#define DPCD_6802A 0x6802A
4710
#define DPCD_6802C 0x6802C
4711
#define DPCD_6803B 0x6803B
4712
#define DPCD_6921D 0x6921D
4713
#define DPCD_69000 0x69000
4714
#define DPCD_69008 0x69008
4715
#define DPCD_6900B 0x6900B
4716
#define DPCD_69215 0x69215
4717
#define DPCD_6921D 0x6921D
4718
#define DPCD_69220 0x69220
4719
#define DPCD_692A0 0x692A0
4720
#define DPCD_692B0 0x692B0
4721
#define DPCD_692C0 0x692C0
4722
#define DPCD_692E0 0x692E0
4723
#define DPCD_692F0 0x692F0
4724
#define DPCD_692F8 0x692F8
4725
#define DPCD_69318 0x69318
4726
#define DPCD_69328 0x69328
4727
#define DPCD_69330 0x69330
4728
#define DPCD_69332 0x69332
4729
#define DPCD_69335 0x69335
4730
#define DPCD_69345 0x69345
4731
#define DPCD_693E0 0x693E0
4732
#define DPCD_693F0 0x693F0
4733
#define DPCD_693F3 0x693F3
4734
#define DPCD_693F5 0x693F5
4735
#define DPCD_69473 0x69473
4736
#define DPCD_69493 0x69493
4737
#define DPCD_69494 0x69494
4738
#define DPCD_69518 0x69518
4739
4740
#endif
/* SOC_MEDIATEK_MT8195_DRTX_REG_H */
src
soc
mediatek
mt8195
include
soc
dptx_reg.h
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